KR0131723B1 - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor deviceInfo
- Publication number
- KR0131723B1 KR0131723B1 KR1019940012821A KR19940012821A KR0131723B1 KR 0131723 B1 KR0131723 B1 KR 0131723B1 KR 1019940012821 A KR1019940012821 A KR 1019940012821A KR 19940012821 A KR19940012821 A KR 19940012821A KR 0131723 B1 KR0131723 B1 KR 0131723B1
- Authority
- KR
- South Korea
- Prior art keywords
- well region
- semiconductor substrate
- well
- conductivity type
- type
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 75
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000012535 impurity Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
제1a도 내지 제1c도는 종래 3중 웰 구조를 갖는 반도체소자의 제조 공정도.1A to 1C are conventional process steps for manufacturing a semiconductor device having a triple well structure.
제2a도 내지 제2d도는 본 발명에 따른 3중 웰구조를 갖는 반도체소자의 제조 공정도.2a to 2d is a manufacturing process diagram of a semiconductor device having a triple well structure according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체기판 2 : N형 웰영역1: semiconductor substrate 2: N-type well region
2A : N형 매립 웰영역 3A : 제1P형 웰영역2A: N type buried well region 3A: 1P type well region
3B : 제 2P형 웰영역 4 : 소자분리절연막3B: 2P type well region 4: device isolation insulating film
5 : 게이트산화막 6 : 게이트전극5: gate oxide film 6: gate electrode
7 : N형 소오스/드레인전극 8 : P형 소오스/드레인전극7: N-type source / drain electrode 8: P-type source / drain electrode
9 : 트랜치 10 : 절연막9: trench 10: insulating film
본 발명은 반도체소자 및 그 제조방법에 관한 것으로서, 특히 서로 다른 도전형의 웰영역 내부에 고립되는 웰영역을 갖는 3중 웰 구조의 반도체소자에서 P형 반도체기판 일측의 서로 다른 도전형의 웰영역의 경계부분으로 예정되어 있는 부분에 소정 깊이의 트랜치를 형성하고 이를 절연막으로 메워 소자를 분리하고, 상기 트랜치에 의해 고립되어 있는 반도체기판의 일측에 소정 깊이의 N형 웰영역을 형성하고, 상기 트랜치에 의해 고립되어 있는 반도체기판의 타측에 N형 매립 웰영역을 형성하며, 그 상측에 P웰영역을 형성하여 상기 P형의 웰영역상에 형성되는 소자의 신뢰성을 향상시키고 소자를 고집적화할 수 있는 반도체소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, in a triple well structure semiconductor device having a well region isolated inside a well region of a different conductivity type, different conductivity type well regions on one side of a P-type semiconductor substrate are provided. A trench having a predetermined depth is formed in a portion defined as a boundary portion of the trench, and the device is filled with an insulating film to separate the device. An N-type well region having a predetermined depth is formed on one side of the semiconductor substrate isolated by the trench. N-type buried well region is formed on the other side of the semiconductor substrate, which is isolated by P-type, and P well region is formed on the upper side thereof, thereby improving the reliability of the device formed on the P-type well region and making the device highly integrated. A semiconductor device and a method of manufacturing the same.
일반적으로 반도체소자가 고집적화되어 감에 따라 하나의 반도체기판에 P형 및 N형 웰영역을 형성하고, 서로 다른 도전형의 웰영역내에도 별도의 웰영역을 형성하여 3중 웰구조를 갖도록 하여 소자를 고집적화한다.In general, as semiconductor devices become more integrated, P-type and N-type well regions are formed on one semiconductor substrate, and separate well regions are formed in well-conducting well regions of different conductivity types to have a triple well structure. Highly integrated
그 예로서, P 및 N모스 트랜지스터를 함께 가지는 씨모스(complementrymos) 트랜지스터는 소비전력이 매우 적고, 동작속도가 매우 빠른 이점이 있다.As an example, complementarymos transistors having both P and NMOS transistors have advantages of very low power consumption and very high operating speed.
종래 3중 웰 구조를 갖는 반도체소자의 제조방법을 제1a도 내지 제1c도를 참조하여 살펴보면 다음과 같다.A method of manufacturing a semiconductor device having a conventional triple well structure will now be described with reference to FIGS. 1A to 1C.
먼저, P형 반도체기판(1)의 일측에 통상의 감광막 패턴을 마스크로 이온주입하여 N형 웰영역(2)을 형성한후, 제(1a도 참조), 상기 반도체기판(1)에서 상기 N형 웰영역(2)이 형성되지 않은 타측 및 상기 N형 웰영역(2)내의 소정 부분에 각각 제1 및 제2P형 웰영역(3A),(3B)을 상기 N형 웰영역(2) 보다 얕은 깊이로 형성한다. (제1b도 참조).First, an N-type well region 2 is formed by ion implantation of a conventional photoresist pattern with a mask on one side of the P-type semiconductor substrate 1 (see FIG. 1a), and then the N in the semiconductor substrate 1 The first and second P-type well regions 3A and 3B are disposed on the other side where the well type region 2 is not formed and the predetermined portions in the N-type well region 2, respectively, than the N-type well region 2. Form to shallow depth. (See also Figure 1b).
그 다음 상기 N형 웰영역(2)과 상기 제1 및 제2P형 웰영역(3A), (3B)들간의 경계 부분상에 소자분리를 위한 소자분리절연막(4)을 형성하고, 상기 반도체기판(1)상에 게이트산화막(5)과 게이트전극(6)을 순차적으로 형성한 후, 상기 게이트전극(6) 양측의 N형 웰영역(2)과 상기 제1 및 제2P형 웰영역(3A),(3B)에 P 및 N형 불순물을 이온주입하여 P 및 N 형 소오스/드레인전극(7),(8)을 형성하여 P 및 N모스 전계효과 트랜지스터를 완성한다. (제1c도 참조).Then, a device isolation insulating film 4 for device isolation is formed on the boundary portion between the N-type well region 2 and the first and second P-type well regions 3A and 3B. After sequentially forming the gate oxide film 5 and the gate electrode 6 on (1), the N type well region 2 on both sides of the gate electrode 6 and the first and second P type well regions 3A are formed. The P and N type source / drain electrodes 7 and 8 are formed by ion-implanting P and N type impurities into 3B) to complete the P and NMOS field effect transistors. (See also Figure 1c).
상기와 같은 종래 방법에 따른 3중 웰 구조를 갖는 반도체소자는 P형 반도체기판상의 일측에 N형 웰영역을 형성하고, 상기 반도체기판의 타측 및 N형 웰영역의 소정부분에 각각 P형 웰영역을 형성한 후, 각각의 웰영역에 모스 전계효과 트랜지스터를 형성하므로, 상기 N형 웰영역 내부에 형성되는 P형 웰영역에는 N형 불순물이 이미 이온주입되어 있어 N모스 전계효과 트랜지스터의 이동도등의 특성을 떨어뜨리는 문제점이 있다.A semiconductor device having a triple well structure according to the conventional method as described above forms an N-type well region on one side of a P-type semiconductor substrate, and a P-type well region on predetermined portions of the other side and the N-type well region of the semiconductor substrate, respectively. After forming the MOS field effect transistor in each well region, N-type impurities are already implanted into the P-type well region formed inside the N-type well region, and thus the mobility of the NMOS field effect transistor, etc. There is a problem that degrades the characteristics of.
또한 종래의 3중 웰 구조를 갖는 반도체소자는 소자분리영역을 필드산화막등으로 형성하여 소자의 고집적화가 어려운 문제점이 있다.In addition, a conventional semiconductor device having a triple well structure has a problem in that the device isolation region is formed of a field oxide film or the like, so that the integration of the device is difficult.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 3중 웰 구조를 갖는 반도체소자에서 반도체기판 일측에 오픈영역을 갖는 소정 깊이의 트랜치를 형성하고 이를 절연막으로 메워 소자를 분리하고, 상기 트랜치에 의해 고립되어 있는 반도체기판에 소정 깊이의 제1도전형의 매립 웰영역을 형성하고, 그 상측에 제2도전형의 웰영역을 형성하여 상기 제2도전형의 웰영역상에 형성되는 소자의 신뢰성을 향상시키고 소자의 고집적화에 유리한 반도체소자를 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a trench having a predetermined depth having an open area on one side of a semiconductor substrate having a triple well structure, and separating the device by filling it with an insulating film. And forming a buried well region of a first conductivity type having a predetermined depth on the semiconductor substrate isolated by the trench, and forming a well region of a second conductivity type on an upper side thereof and forming a well region of the second conductive type. It is to provide a semiconductor device which is advantageous in improving the reliability of the device and high integration of the device.
본 발명의 다른 목적은 3중 웰영역을 갖는 반도체소자에서 트랜치에 의해 분리되어 있는 반도체기판상의 소정깊이에 고에너지 이온주입으로 N형매립 웰영역을 형성하고 그 상측에 P형 웰영역을 형성하여 상기 P형 웰영역을 고립시켜 N모스 전계효과 트랜지스터의 특성을 향상시킬수 있는 반도체소자의 제조방법을 제공함에 있다.Another object of the present invention is to form an N-type buried well region by high energy ion implantation at a predetermined depth on a semiconductor substrate separated by a trench in a semiconductor device having a triple well region, and to form a P-type well region on the upper side thereof. The present invention provides a method for fabricating a semiconductor device capable of improving the characteristics of an NMOS field effect transistor by isolating the P-type well region.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 특징은, 제1도전형의 반도체기판의 일측에 형성되어 있는 제2도전형의 제1웰영역과, 상기 제1웰영역과 접하는 반도체기판의 다른 부분에 형성되어 있으며, 깊이가 상기 제1웰영역 보다 얕게 형성되어 있는 제1도전형의 제 2 웰영역과, 상기 제1 및 제 2 웰영역 이외의 반도체기판에 형성되어 있는 제 2 도전형의 매립 웰영역과, 상기 제1 및 제2 웰영역 이외의 반도체기판에 형성되어 있는 제1도전형의 제3웰영역과, 상기 제1, 제2 및 제3 웰영역의 경계 부분상의 반도체기판이 소정의 깊이로 제거되어 상기 웰영역들을 분리시키는 트랜치를 구비함에 있다.A semiconductor device according to the present invention for achieving the above object is, the first well region of the second conductive type formed on one side of the semiconductor substrate of the first conductive type, and the semiconductor in contact with the first well region A second well region of a first conductivity type formed in another portion of the substrate, the depth being shallower than the first well region, and a second formed in a semiconductor substrate other than the first and second well regions; On a conductive well-filled well region, a third well region of a first conductive type formed in a semiconductor substrate other than the first and second well regions, and a boundary portion between the first, second and third well regions. A semiconductor substrate is removed to a predetermined depth to provide a trench for separating the well regions.
본 발명에 따른 3중 웰구조를 갖는 반도체소자의 다른 특징은, 제1도전형의 반도체기판의 일측에 형성되어 있는 제2도전형의 제1웰영역과, 상기 제1웰영역과 접하는 반도체기판의 다른 부분에 형성되어 있으며, 깊이가 상기 제1웰영역보다 얕게 형성되어 있는 제1도전형의 제2웰영역과, 상기 제2웰영역의 하부에서 형성되어 있는 제2도전형의 매립 웰영역과, 상기 제1 및 제2웰영역 이외의 반도체기판에 형성되어 있는 제1도전형의 제3웰영과, 상기 제1, 제2 및 제3웰영역의 경계 부분상의 반도체기판이 소정의 깊이로 제거되어 상기 웰영역들을 분리시키는 트랜치와, 상기 반도체기판상에 형성되어 있는 게이트산화막과, 상기 게이트 산화막상에 형성되어 있는 게이트전극과, 상기 게이트전극 양측의 제 1 웰영역 및 제 2 , 제 3 웰영역상에 각각 제 1 및 제 2 도전형의 불순물로 형성되어 있는 확산영역을 구비함에 있다.According to another aspect of the present invention, a semiconductor device having a triple well structure includes a first well region of a second conductive type formed on one side of a semiconductor substrate of a first conductive type, and a semiconductor substrate in contact with the first well region. A second well region of a first conductivity type formed at a different portion of the second well region and having a depth smaller than that of the first well region, and a buried well region of a second conductive type formed below the second well region. And a third well young of a first conductivity type formed in semiconductor substrates other than the first and second well regions, and the semiconductor substrate on the boundary portion of the first, second and third well regions, to a predetermined depth. A trench to remove the well regions, a gate oxide film formed on the semiconductor substrate, a gate electrode formed on the gate oxide film, and first gates on both sides of the gate electrode. It consists in an area and the second and first respectively on the third well region and the first diffusion region is formed with an impurity of a second conductivity type.
다른 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은, 제 1 도전형의 반도체기판의 일측에 반도체기판의 소정 부분을 두 개의 오픈영역을 갖도록 분리시키는 트랜치를 형성하는 공정과, 상기 트랜치를 절연층으로 메우는 공정과, 상기 트랜치에 의해 분리된 오픈영역의 일측에 제 2 도전형의 제 1 웰영역을 형성하는 공정과, 상기 타측 오픈영역의 반도체기판에 소정 깊이로 제 2 도전형의 매립 웰영역을 형성하는 공정과, 상기 매립 웰영역의 상측에 깊이가 상기 제 1 웰영역 보다 얕게 제 1 도전형의 제 2 웰영역을 형성하는 공정과, 상기 반도체기판의 다른 부분에 제 1 도전형의 제 3 웰영역을 형성하는 공정을 구비함에 있다.In another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a trench for separating a predetermined portion of a semiconductor substrate to have two open regions on one side of the first conductive semiconductor substrate; Filling the trench with an insulating layer, forming a first well region of a second conductivity type on one side of the open region separated by the trench, and forming a second conductivity type at a predetermined depth in the semiconductor substrate of the other open region. Forming a buried well region of the semiconductor substrate, forming a second well region of a first conductivity type on the upper side of the buried well region and having a depth smaller than that of the first well region, and forming a first well region on another portion of the semiconductor substrate. And forming a third well region of a conductivity type.
이하, 본 발명에 따른 반도체소자 및 그 제조방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.
제2a 및 제2d도는 본 발명에 따른 3중 웰 구조를 갖는 반도체소자의 제조 공정도로서, P형 웰영역에 의해 N형 웰영역이 고립되어 있는 경우의 예이며, 제2d도는 본 발명에 따른 3중 웰 구조를 갖는 반도체소자의 완성된 구조의 단면도이므로, 구조는 중복설명하지 않는다.2A and 2D are manufacturing process diagrams of a semiconductor device having a triple well structure according to the present invention, in which an N type well region is isolated by a P type well region, and FIG. Since it is sectional drawing of the completed structure of the semiconductor element which has a well structure, a structure is not overlapped.
먼저, 제 1 도전형인 P형 반도체기판(1)의 일측에 두부분의 오픈영역을 분리하는 소정깊이, 예를들어 2.0 - 6.0㎛ 깊이의 트랜치(9)를 형성한 후, 상기 트랜치(9)를 산화막이나 질화막등의 절연층(10)으로 메운다.(제2a도 참조).First, a trench 9 having a predetermined depth, for example, 2.0 to 6.0 μm, is formed on one side of the first conductivity type P-type semiconductor substrate 1, and then the trench 9 is formed. It is filled with insulating layers 10, such as an oxide film and a nitride film (refer also to FIG. 2a).
그다음 상기 트랜치(9)에 의해 분리되어 있는 반도체기판(1)의 일측에 제 2 도전형인 N형 웰영역(2)을 소정깊이, 예를들어 1.5 - 5.0㎛ 정도의 깊이 및 소정 농도, 예를들어 1016- 1018㎝-3정도의 도핑농도로 형성한 후 상기 트랜치(9)에 의해 분리되어 있는 타측의 반도체기판(1)에 소정 깊이로 N형 불순물이 이온주입하고 활성화시켜 N형 매립 웰영역(2A)을 형성한다.(제2b도 참조).Next, the second conductivity type N-type well region 2 is formed on one side of the semiconductor substrate 1 separated by the trench 9 at a predetermined depth, for example, a depth and a predetermined concentration, for example, 1.5 to 5.0 μm. g 10 16 - 10 18 ㎝-3 was formed with a doping concentration of about N-type to a predetermined depth in the semiconductor substrate (1) on the other side which are separated by the trench 9, the impurity ion implantation and to activate the N-type buried A well region 2A is formed (see also FIG. 2b).
그다음 상기 반도체기판(1)의 타측과 N형 매립 웰영역(2A)의 상측에 각각 제 1 및 제 2 P형 웰영역(3A), (3B)을 형성한다. 이때 상기 제 1 및 제 2 P형 웰영역(3A), (3B)의 깊이는 상기 N형 웰영역(2) 보다 얕은 깊이, 예를들어 1.0-4.5㎛ 정도의 깊이로 형성하며, 상기 제 1 및 제 2 P형 웰영역(3A), (3B)의 도핑농도는 서로 같거나 다른수 있고, 약 1016-1018㎝-3정도의 도핑농도로 형성하며 3중 웰 구조를 완성한다.Then, first and second P-type well regions 3A and 3B are formed on the other side of the semiconductor substrate 1 and above the N-type buried well region 2A, respectively. In this case, the depths of the first and second P-type well regions 3A and 3B are formed to have a depth smaller than that of the N-type well region 2, for example, about 1.0-4.5 μm. And the doping concentrations of the second P-type well regions 3A and 3B may be the same or different from each other, and are formed with a doping concentration of about 10 16 -10 18 cm -3 to complete the triple well structure.
따라서 상기 제 2 P형 웰영역(3B)은 N형 불순물 1015㎝-3정도이하의 저농도로 포함된다.(제2c도 참조).Therefore, the second P-type well region 3B is included at a low concentration of about 10 15 cm -3 or less of N-type impurities (see also FIG. 2C).
그후, 상기 제 1 P형 웰영역(3A)의 소정 부분에 소자분리를 위한 소자 분리절연막(4)을 형성하고 상기 반도체기판(1) 상에 게이트산화막(5)과 게이트전극(6)을 형성한 후, 상기 게이트전극(6) 양측의 N형 웰영역(2)과 제 1 및 제 2P형 웰영역(3A),(3B)에 각각 P 및 N형 불순물을 이온주입하여 P 및 N형 소오스/드레인전극(7),(8)을 형성하여 P 및 N형 모스 전계효과 트랜지스터를 완성한다.(제2d도 참조).Thereafter, a device isolation insulating film 4 for device isolation is formed in a predetermined portion of the first P-type well region 3A, and a gate oxide film 5 and a gate electrode 6 are formed on the semiconductor substrate 1. Then, P and N type impurities are ion-implanted into the N type well region 2 and the first and second P type well regions 3A and 3B on both sides of the gate electrode 6, respectively, to form a P and N type source. Drain electrodes 7 and 8 are formed to complete P and N-type MOS field effect transistors (see also FIG. 2D).
이상에서 설명한 바와 같이, 본 발명에 따른 3중 웰 구조를 갖는 반도체소자 및 그 제조방법은 P형 반도체기판의 일측에 두곳의 오픈영역을 고립시키는 트랜치를 형성하고, 상기 트랜치에 의해 분리되어 있는 반도체기판의 일측에 N형 웰영역을 하며, 상기 트랜치에 의해 분리되어 있는 반도체기판의 타측에 소정깊이로 N형 매립 웰영역을 형성한 후, 상기 N형 매립 웰영역의 상측에 P형 웰영역을 형성하고, 상기 반도체기판상에 각각 모스 전계효과 트랜지스터를 형성하였으므로, 상기 고립되어 있는 P형 웰영역내의 N형 불순물 농도가 최소화되어 상기 고립된 P형 웰영역상에 형성되는 N모스 전계효과 트랜지스터의 이동도가 증가되는 등 특성이 개선되어 공정수율 및 소자동작의 신뢰성이 향상되는 이점이 있다.As described above, a semiconductor device having a triple well structure and a method of manufacturing the same according to the present invention form a trench to isolate two open regions on one side of a P-type semiconductor substrate, and are separated by the trench. An N-type well region is formed on one side of the substrate, and an N-type buried well region is formed on the other side of the semiconductor substrate separated by the trench at a predetermined depth, and then a P-type well region is formed on the N-type buried well region. And the MOS field effect transistors are formed on the semiconductor substrate, respectively, so that the concentration of N-type impurities in the isolated P-type well region is minimized, thereby forming the NMOS field effect transistors formed on the isolated P-type well region. The characteristics are improved, such as increased mobility, there is an advantage that the process yield and device operation reliability are improved.
Claims (6)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019940012821A KR0131723B1 (en) | 1994-06-08 | 1994-06-08 | Manufacturing method for semiconductor device |
| US08/468,552 US5525532A (en) | 1994-06-08 | 1995-06-06 | Method for fabricating a semiconductor device |
| GB9511563A GB2290165B (en) | 1994-06-08 | 1995-06-07 | Semiconductor device and method of fabrication thereof |
| CN95106329A CN1037923C (en) | 1994-06-08 | 1995-06-08 | Semiconductor device and method for fabricating the same |
| DE19520958A DE19520958C2 (en) | 1994-06-08 | 1995-06-08 | Semiconductor device with well regions and method for producing the semiconductor device |
| US08/598,551 US5726476A (en) | 1994-06-08 | 1996-02-08 | Semiconductor device having a particular CMOS structure |
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| KR1019940012821A KR0131723B1 (en) | 1994-06-08 | 1994-06-08 | Manufacturing method for semiconductor device |
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| KR960002556A KR960002556A (en) | 1996-01-26 |
| KR0131723B1 true KR0131723B1 (en) | 1998-04-14 |
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| KR1019940012821A KR0131723B1 (en) | 1994-06-08 | 1994-06-08 | Manufacturing method for semiconductor device |
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| US (2) | US5525532A (en) |
| KR (1) | KR0131723B1 (en) |
| CN (1) | CN1037923C (en) |
| DE (1) | DE19520958C2 (en) |
| GB (1) | GB2290165B (en) |
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| US5573963A (en) * | 1995-05-03 | 1996-11-12 | Vanguard International Semiconductor Corporation | Method of forming self-aligned twin tub CMOS devices |
| US5573962A (en) * | 1995-12-15 | 1996-11-12 | Vanguard International Semiconductor Corporation | Low cycle time CMOS process |
| US5753956A (en) * | 1996-01-11 | 1998-05-19 | Micron Technology, Inc. | Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry |
| US5612242A (en) * | 1996-03-11 | 1997-03-18 | United Microelectronics Corp. | Trench isolation method for CMOS transistor |
| DE69735323T2 (en) * | 1996-09-05 | 2006-11-02 | Matsushita Electric Industrial Co., Ltd., Kadoma | Semiconductor arrangement and its production method |
| KR100239402B1 (en) * | 1997-04-02 | 2000-02-01 | 김영환 | Method for manufacturing semiconductor device |
| GB2327146A (en) * | 1997-07-10 | 1999-01-13 | Ericsson Telefon Ab L M | Thermal insulation of integrated circuit components |
| JPH11274418A (en) * | 1998-03-25 | 1999-10-08 | Nec Corp | Semiconductor device |
| JP2000091443A (en) * | 1998-09-14 | 2000-03-31 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| GB2344689A (en) | 1998-12-07 | 2000-06-14 | Ericsson Telefon Ab L M | Analogue switch |
| US6144086A (en) * | 1999-04-30 | 2000-11-07 | International Business Machines Corporation | Structure for improved latch-up using dual depth STI with impurity implant |
| US6642583B2 (en) * | 2001-06-11 | 2003-11-04 | Fuji Electric Co., Ltd. | CMOS device with trench structure |
| US6885078B2 (en) * | 2001-11-09 | 2005-04-26 | Lsi Logic Corporation | Circuit isolation utilizing MeV implantation |
| AU2003258960A1 (en) | 2002-06-26 | 2004-01-19 | Semequip Inc. | Ion implantation device and method |
| US6686595B2 (en) | 2002-06-26 | 2004-02-03 | Semequip Inc. | Electron impact ion source |
| US7825488B2 (en) * | 2006-05-31 | 2010-11-02 | Advanced Analogic Technologies, Inc. | Isolation structures for integrated circuits and modular methods of forming the same |
| JP4755405B2 (en) * | 2004-10-13 | 2011-08-24 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP5375402B2 (en) | 2009-07-22 | 2013-12-25 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| KR102122244B1 (en) * | 2012-08-28 | 2020-06-15 | 얀센 사이언시즈 아일랜드 언리미티드 컴퍼니 | SUlfamoyl-arylamides and the use thereof as medicaments for the treatment of hepatitis B |
| CN104282734B (en) * | 2014-09-24 | 2018-02-06 | 上海华虹宏力半导体制造有限公司 | The primary device and its manufacture method of the channel isolation compatible with CMOS technology |
| CN104362095B (en) * | 2014-11-05 | 2017-12-01 | 北京大学 | A kind of preparation method of tunneling field-effect transistor |
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| GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
| JPS5275989A (en) * | 1975-12-22 | 1977-06-25 | Hitachi Ltd | Production of semiconductor device |
| US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
| JPS6083346A (en) * | 1983-10-14 | 1985-05-11 | Hitachi Ltd | Semiconductor integrated circuit device |
| KR900005124B1 (en) * | 1984-10-17 | 1990-07-19 | 가부시기가이샤 히다찌세이사꾸쇼 | Complementary semiconductor device |
| GB8426897D0 (en) * | 1984-10-24 | 1984-11-28 | Ferranti Plc | Fabricating semiconductor devices |
| US4808548A (en) * | 1985-09-18 | 1989-02-28 | Advanced Micro Devices, Inc. | Method of making bipolar and MOS devices on same integrated circuit substrate |
| US4825275A (en) * | 1987-05-28 | 1989-04-25 | Texas Instruments Incorporated | Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias |
| JP2666384B2 (en) * | 1988-06-30 | 1997-10-22 | ソニー株式会社 | Method for manufacturing semiconductor device |
| US5006476A (en) * | 1988-09-07 | 1991-04-09 | North American Philips Corp., Signetics Division | Transistor manufacturing process using three-step base doping |
| US5015594A (en) * | 1988-10-24 | 1991-05-14 | International Business Machines Corporation | Process of making BiCMOS devices having closely spaced device regions |
| US4960726A (en) * | 1989-10-19 | 1990-10-02 | International Business Machines Corporation | BiCMOS process |
| US5250837A (en) * | 1991-05-17 | 1993-10-05 | Delco Electronics Corporation | Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
| JP2740087B2 (en) * | 1992-08-15 | 1998-04-15 | 株式会社東芝 | Method for manufacturing semiconductor integrated circuit device |
-
1994
- 1994-06-08 KR KR1019940012821A patent/KR0131723B1/en not_active IP Right Cessation
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1995
- 1995-06-06 US US08/468,552 patent/US5525532A/en not_active Expired - Lifetime
- 1995-06-07 GB GB9511563A patent/GB2290165B/en not_active Expired - Fee Related
- 1995-06-08 CN CN95106329A patent/CN1037923C/en not_active Expired - Fee Related
- 1995-06-08 DE DE19520958A patent/DE19520958C2/en not_active Expired - Fee Related
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1996
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| Publication number | Publication date |
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| DE19520958C2 (en) | 1997-09-11 |
| GB9511563D0 (en) | 1995-08-02 |
| CN1037923C (en) | 1998-04-01 |
| US5726476A (en) | 1998-03-10 |
| DE19520958A1 (en) | 1995-12-14 |
| KR960002556A (en) | 1996-01-26 |
| GB2290165B (en) | 1998-07-29 |
| US5525532A (en) | 1996-06-11 |
| GB2290165A (en) | 1995-12-13 |
| CN1119347A (en) | 1996-03-27 |
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