KR0118760B1 - Transmission circuit - Google Patents

Abstract

The data transmission circuit by insulation in an electronic equipment system having a microprocessor(100) which is installed in the electronic equipment and outputs read, write, address and data signals for controlling the operation of the electronic equipment and peripheral equipments and a plurality of peripheral equipments which operate by the read, write, address and data signals of the microprocessor(100), has a data transmission circuit(400) for buffering and amplifying the read, write, address and data signals to be transmitted, transmitting the buffered and amplified signals by radio (optical transmission), buffering and amplifying the transmitted read, write, address and data signals and then applying the signals to the peripheral equipments, wherein the buffering and amplifying operation thereof is enabled by an enable signal which is generated on the basis of the read, write, address signals output from the microprocessor.

Description

Data transmission circuit by insulation

1 is a block diagram showing a general data transmission circuit of a microprocessor.

2 is a time chart for explaining a data transfer operation through a data transfer circuit of a microprocessor.

3 is a block diagram showing an isolated data transmission circuit of a microprocessor according to the present invention.

4 is a detailed circuit diagram of an isolated data transfer circuit of a microprocessor according to the present invention.

FIG. 5 is a detailed circuit diagram illustrating an example of the photocoupler of FIG. 4.

* Explanation of symbols for main parts of the drawings

100: microprocessor 200: address decoder

300: peripheral device 400: data transmission circuit

410,420,430,440,460,470,480,490: Buffer 450: Time delay control signal generator

500: time delay control signal generating circuit 600: address decoder

PC, PC ₁ PC ₂ : Photocoupler PT: Phototransistor

G ₁ , G ₂ , G ₃ , G ₄ : Ora gate D ₀ -D ₇ : D flip / flop

LED: Light Emitting Diode R: Resistance

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for controlling the operation of a peripheral device or a secondary microprocessor by transmitting write, read, address and data signals. More particularly, the present invention relates to a write, read and address transmitted from a microprocessor to a peripheral device or a secondary microprocessor. The data transmission circuit is isolated to prevent malfunction of peripherals or sub-microprocessors because noise signal enters the transmission line through which data signal is transmitted, or impedance matching is not performed due to difference of ground level between microprocessor and peripherals. It is about.

In order to meet the needs of consumers, as the structure of electronic devices becomes more complicated and the functions are diversified, the number of constituent parts that make up electronic devices increases accordingly, but the mechanical control method is used to control electronic devices composed of multiple parts. In order to overcome this limitation, each component is connected to a microprocessor capable of collectively controlling the operation of a plurality of components configured inside the electronic device. Recognizing the operation state of the electronic device to control the operation of the electronic device.

As described above, a schematic internal structure of a conventional electronic device controlling a electronic device by embedding a microprocessor inside the electronic device is configured as shown in FIG.

The microprocessor 100 to which the operation state data of the electronic device is applied from a microprocessor of a peripheral device including a keypad or an electronic device and an auxiliary microprocessor, which is not shown, includes a peripheral device 300 (secondary microprocessor). ), An output port for outputting an address, a write, a read and a data signal for controlling the operation of _1- L ₂ is configured with an address decoder 200 for designating the address of the peripheral device 300 as an address signal and a write signal output, and selectively operates as an output of the address decoder 200 to and between the D flip / flop to transmit data signals from the processor 100 to peripherals _{(300) (D 0 -D 7} ) and a microprocessor 100, three microprocessor Is the transmission line in the ground between the ground and the peripheral device 300 of _{(100) (L 3 -L 4} ) configuration.

In the peripheral device control circuit by the conventional microprocessor configured as described above, the microprocessor 100 embedded in the electronic device is based on the manipulation of the keypad or the operation state data of the peripheral device and the electronic device. Recognizing the operation state, and outputs the address signal, read signal, and write signal for controlling the operation of the electronic device and the peripheral device to the address decoder 200 through the transmission line (L _1- L ₂ ), and transmits the data signal to the transmission line Output to D terminal of D flip / flop (D ₀ -D ₇ ) through furnace (L ₃ ).

In the address decoder 200 to which an address signal, a write signal, and a read signal (not shown) are applied, the address decoder 200 reads the address signal, the write signal, and the read signal to generate a chip selector signal, thereby generating a D flip / flip (D _0). and -D is a drive signal of the D flip / flop (D ₀ -D ₇₎ in each clock terminal (clock) of _7).

That is, while the address signal for selecting the driving of the D flip / flop D ₀ -D ₇ from the microprocessor 100 is applied to the address decoder 200 as shown in FIG. When a write signal such as (C) of FIG. 2 is applied, the address decoder 200 decodes the address signal and generates a chip selector signal such as (D) of FIG. 2 to generate a D flip / flop (D _0). applied to each clock terminal (clock) of -D ₇₎ to select the D flip / flop designated by the signal generating chip varactor cells of the D flip / flop (D ₀ -D _7).

Therefore, the D flip / flop (D ₀ -D _7), a microprocessor illustrative drawings second degree (B) data signals that are applied D- flip / flop (D ₀ -D _7), such as from 100 to the D terminal of the After the data signal is delayed for a predetermined time, the data signal is output to the input ports P ₀ -P ₇ of the peripheral device 300 as illustrated in FIG _. 2E, so that the peripheral device 300 corresponds to the applied data signal. Perform the action.

However, as described above, as the range of electronic devices that control the operation of electronic devices or peripherals incorporating auxiliary microprocessors increases, the distance between the microprocessor and the peripheral devices increases and a strong electric field is formed between the microprocessor and the peripheral devices. In order to control the operation of the electronic device, a number of components are included to control the operation of the microprocessor because noise signals are mixed into the data transmitted inside the transmission line established between the microprocessor and the peripheral device. There has been a case in which a peripheral device including a driving electronic device or an auxiliary microprocessor malfunctions.

That is, when the noise generated from the strong electric field or the adjacent transmission signal generated from the strong electric field element installed close to the transmission line is introduced into the data transmitted to the other transmission line, the chip selector signal not based on the address signal or the write signal output from the microprocessor. A noise signal is mixed into a data signal applied to a D flip / flip that generates a signal or a peripheral device from a microprocessor through a D flip / flop, and applied to a peripheral device along with a noise signal to abnormally select a chip or a peripheral data signal. There was a problem that the peripheral device malfunctions by outputting.

In addition, the ground terminals of the microprocessor and peripheral devices are connected to ground, respectively, and the impedance matching between the ground terminal of the microprocessor and the peripheral device is not matched, so that impedance matching between the ground of the microprocessor and the peripheral device is not performed, as well as lead, Impedance is also inherent between transmission lines through which write, address, and data signals are transmitted, so that impedance matching cannot be performed between the microprocessor and peripheral devices.

In particular, when using a microprocessor in which an address signal, a light signal, and a data signal output from a microprocessor are abnormally output to a peripheral device due to the mixing of noise signals, it is applied to an industrial electronic device such as a factory or a construction site. There was a problem that could cause a fatal result of harming people as well as property damage.

The present invention has been made to solve the conventional problems as described above, and amplifies the data signal to be transmitted from the output port of the microprocessor to a predetermined level buffer amplification to a predetermined level and then wirelessly transmits the level matched to the peripheral device It is an object of the present invention to provide a data transmission circuit with insulation to control the operation of peripheral devices by buffering and amplifying them.

In addition, another object of the present invention is to be able to recognize the data input / output by the microprocessor delayed by the time required for wireless transmission.

A data transmission circuit according to the present invention for realizing the above object is a system for controlling the operation of peripheral devices connected to the microprocessor by embedding a microprocessor for outputting read, write, address, and data signals in the electronic device. A buffer for amplifying the read, write, address, and data signals to be transmitted, and a photocoupler for wirelessly transmitting (optical transmission) the buffered amplified read, write, address, and data signals; A buffer for amplifying a read, write, address, and data signal transmitted wirelessly and applied to a peripheral device, wherein the buffer is enabled by an enable signal generated based on a read, write, and address signal output from a microprocessor. To enable it.

In addition, the data transmission circuit according to the present invention has a predetermined time delay for input / output read / write, address, and data signals in consideration of time delays caused by wireless transmission of read, write, address, and data signals to electronic devices. The time delay control signal is generated and output to the microprocessor based on the read, write, address, and data signals so as to be recognized.

Hereinafter, the configuration of the present invention in more detail with reference to the accompanying drawings as follows.

The data transmission circuit according to the present invention has a microprocessor 100 which is configured inside the electronic device as shown in FIG. 3 and outputs read, write, address, and data signals for controlling the operation of the electronic device or peripheral device. ) And a plurality of peripheral devices 300 that operate with read, write, address, and data signals of the microprocessor 100, and buffer amplify the read, write, address, and data signals to be transmitted. The buffered amplified read, write, address, and data signals are wirelessly transmitted (optical transmission), and the buffered amplified read, write, address, and data signals are applied to a peripheral device. Enable enable signal generated based on output read, write and address signals It is configured to include a data transfer circuit 400 to.

As shown in FIG. 4, the data transmission circuit 400 includes buffers 410, 420, 430, 440, and 450 for buffering the read, write, address, and data signals to be transmitted. A photocoupler (PC) that wirelessly transmits (optically transmits) the amplified read, write, address, and data signals, and a buffer that amplifies the wirelessly transmitted read, write, address, and data signals to the peripheral device 300 (460). 470, 480, 490 and the OR gate G ₁ combining the outputs of the read and write signals output from the microprocessor 100 and the address decoder 600 from which the address signals are decoded. ₂ ) and photocouplers (PC ₁ ) and (PC ₂ ) for wirelessly transmitting the combined enable signal to the buffers 420 and 460.

In addition, the data transmission circuit according to the present invention is a lead. An address that determines whether to designate a peripheral device to be controlled by decoding the address signal of the microprocessor 100 that generates and outputs a time delay control signal to the microprocessor based on the write, address, and data signals. The OR gate which inverts the decoder 600, the output of the OR gate G ₄ inverted after the logical sum of the read and write signals of the buffer 490 and the output of the address decoder 600. is (G ₃₎ and complaining Iowa gate (G ₃₎ consists of a microprocessor generated time delay control signal for outputting a time delay control signal (100) section 450 based on the output of.

5 is a detailed circuit diagram illustrating an embodiment of a photocoupler according to the present invention, and is provided at an output terminal of a buffer 410, 470, 430, 440 or OA gate G ₁ (G ₂ ). Connect the power supply B ⁺ to the anode side of the light emitting diode (LED) to which the cathode side is connected via a resistor (R), and the emitter side is grounded to the input terminals of the buffers 460, 420, 480, and 490. The collector side of the phototransistor PT is connected, but the power supply B ⁺ is connected to the collector side through a resistor R.

Here, the address decoder 600 which decodes the address signal has a low level when an address signal for wireless transmission (optical transmission) of various data is sent from the microprocessor 100 and a high level when an address signal for wired transmission is sent. The level is output to the input terminal of OR gate G ₁ (G ₂ ) (G ₃ ).

Hereinafter, the operational effects of the present invention will be described.

In the microprocessor 100, as shown in FIG. 2, an electronic device or a peripheral device to control read signals, write signals, and data signals for controlling operations of the electronic device and the peripheral device 300 connected to the microprocessor 100. Is installed close to the transmission line connected to the microprocessor 100, the electronic device and the peripheral period when there is no noise mixed by using a conventional method to control the electronic device or peripheral device by the address signal, the read signal, the write signal In this case, the data signal is directly transmitted to the electronic device or peripheral device via a line, and if the transmission line is long or a noise generating element is formed in the vicinity, the electronic device or peripheral device is selected by the address signal. Direct read signal, write signal and data signal Instead of transmitting, buffering and amplifying the read signal, the write signal, and the data signal through the buffers 410, 430, and 440 to the light emitting diodes (LEDs) of the photocoupler (PC) and emitting light from the photo coupler (PC) The read signal, the write signal, and the data signal applied to the diode LED are applied to the buffers 460, 480, and 490 while driving the photo transistor PT of the photo coupler PC, and then buffered and amplified. ) Is supplied to operate the peripheral device 300.

At this time, the address decoder 600 decodes the address signal and wirelessly transmits a read signal, a write signal, an address signal, and a data signal to a peripheral device to be controlled by the microprocessor 100, and the low level address decoder 600. this output is applied to an input terminal of Iowa gate (G _3), since the light signal of a low level applied to the input terminal of the Iowa gate (G ₃₎ Iowa gate (G _3), the output buffer 460 to the high level of The data signal supplied to the enable signal to control the peripheral device 300 is wirelessly transmitted to the peripheral device 300 via the buffer 410, the photo coupler (PC), and the buffer 46.

On the other hand, the address decoder 600 decodes an address signal and wirelessly transmits a read signal, a write signal, an address signal, and a data signal to a peripheral device to be controlled by the microprocessor 100. ) buffer output Iowa gate (G _2), the output of the input is applied to the terminal, so that the read signal of a low level applied to the other input terminal of the Iowa gate (G ₂₎ Iowa gate (G ₂₎ a low level of the ( The signal is supplied to the 420 as an enable signal, and a data signal according to an operation state of the peripheral device 300 is wirelessly transmitted to the microprocessor 100 via the buffer 470, the photo coupler (PC), and the buffer 420.

In addition, the address decoder 600 decodes an address signal and wirelessly transmits a read signal, a write signal, an address signal, and a data signal to a peripheral device to be controlled by the microprocessor 100. When the output of is applied to the input terminal of the OR gate (G ₁ ), the read signal and the write signal is logically summed at the OR gate (G ₄ ) and then inverted and applied to the input terminal of the OR gate (G ₁ ), the time delay control signal. The generator 450 determines this and transmits a time delay control signal to the microprocessor 100 so that the microprocessor 100 controls the operation of the peripheral device 300 or recognizes the operation of the peripheral device 300 based on this. Delay by the time according to the wireless transmission control / recognition to remove the time difference between the microprocessor 100 and the peripheral device 300.

Therefore, even if the transmission line is long in the microprocessor and peripheral period, the data is wirelessly transmitted (optical transmission), so noise generated from a strong electric field or other element is not mixed in the transmission line, so that the data can be transmitted accurately, as well as the impedance of the data transmission line This eliminates the need for separate impedance matching of ground between the connected microprocessor and the peripheral period.

As described above, the present invention wirelessly transmits (optical) data even when the transmission line is long in the microprocessor and the peripheral period, so that noise generated from a strong electric field or other element is not mixed in the transmission line, and thus, data can be transmitted accurately. The effect of eliminating the need to separately match the impedance of the ground in the impedance of the furnace or the microprocessor and the peripheral period connected to each other can be eliminated.

Claims (3)

In the electronic system in which the microprocessor 100 controls the plurality of peripheral devices 300 by outputting read, write, address, and data signals through the transmission circuit 400, the data transmission circuit 400 is intended to transmit. Buffers 410, 420, 430, 440 and 450 that buffer and amplify read, write, address and data signals, and perform wireless transmission (optical transmission) of the buffered amplified read, write, address and data signals. A photo coupler (PC), buffers 460, 470, 480 and 490 for buffering and amplifying the wirelessly transmitted read, write, address and data signals to the peripheral device 300, and the microprocessor 100 An OR gate G ₁ (G ₂ ) which combines the output of the read and write signals and the address decoder 600 obtained by decoding the address signal, and the combined enable signal from the buffer 420 ( photo coupler for radio transmission to _{460) (PC 1), (} PC 2) Data transmission circuit according to the insulation, characterized by doeeojim configuration. The microprocessor 100 of claim 1, wherein the microprocessor 100 controls the microprocessor 100 by decoding an address signal of the microprocessor 100 that generates and outputs a time delay control signal to the microprocessor based on the read, write, address, and data signals. The address decoder 600 for determining whether to designate a peripheral device, the output of the OR gate G ₄ inverted after the OR of the read and write signals of the buffer 490 and the address decoder 600 are inverted. An oar gate G ₃ for combining and inverting outputs, and a time delay control signal generator 450 for outputting a time delay control signal to the microprocessor 100 based on the output of the oar gate G ₃ . Data transmission circuit by insulation, characterized in that the configuration. The address decoder 600 of claim 2, wherein the address decoder 600 has a low level when an address signal for wireless transmission (optical transmission) of the microprocessor 100 is transmitted, and a high level when an address signal for wired transmission is sent. And outputs the signal to the input terminal of the gate (G ₁ ) (G ₂ ) (G | ₃ ).