KR0110411Y1 - Discharge lamp lighting device - Google Patents

Abstract

The present invention superimposes a low intensity mercury arc discharge lamp, a high frequency power supply for supplying a high frequency power to the discharge lamp, a means for controlling the high frequency power supplied to the discharge lamp, and a high frequency power supplied to the lamp from the high frequency power supply. The present invention relates to a discharge lamp lighting device comprising a DC power supply means for supplying a DC power supply having a level capable of maintaining a discharge during low luminous flux illumination to the discharge lamp.

Description

Discharge lamp lighting device

1 is a block diagram showing an embodiment of a discharge lamp lighting apparatus according to the present invention

2 is an explanatory diagram of the discharge lamp of the device of FIG.

3 is a block diagram showing different operating characteristics of the FIG. 1 apparatus.

4 is a detailed circuit diagram of the device of FIG.

5 (a) and 5 (b) are waveform diagrams of respective parts of the circuit of FIG.

6 is a waveform diagram of each part of the circuit of FIG.

7 (a) and 7 (b) are power waveform diagrams respectively applied to the discharge lamps in different states.

8 is a block diagram of other operating characteristics of the device of FIG.

9 is a block diagram showing another embodiment of a discharge lamp according to the present invention

10 is a block diagram of another embodiment of a dimming discharge lamp according to the present invention

FIG. 11 is a block diagram showing yet another operating characteristic of the FIG. 10 apparatus.

12 is a block diagram of another embodiment of a dimming discharge lamp according to the present invention;

FIG. 13 is a detailed circuit diagram of the main circuit of the device of FIG.

14 (a) and 14 (b) are detailed circuit diagrams of the control means of the apparatus of FIG.

FIG. 15 is a waveform diagram of each circuit of FIG.

FIG. 16 is a detailed circuit diagram of the main circuit of the apparatus having different operation characteristics shown in FIG.

FIG. 17 is a detailed circuit diagram of a device control means having another operating characteristic shown in FIG.

FIG. 18 is a detailed circuit diagram of an apparatus having different operating characteristics shown in FIG.

19 is a circuit diagram of another embodiment of the discharge lamp lighting apparatus according to the present invention

20 (a) and 20 (d) are the operational waveform diagram of the device of FIG. 19.

FIG. 21 is a block diagram of another operation characteristic of the FIG. 19 apparatus.

FIG. 22 is a detailed circuit diagram of the main circuit of the apparatus of FIG. 21. FIG.

FIG. 23 is a detailed circuit diagram of the control means of the apparatus of FIG.

24 (a) and 24 (c) are diagrams of the operating waveforms of the apparatus of FIG.

FIG. 25 is a block diagram of another operation characteristic of the FIG. 19 apparatus.

FIG. 26 is a diagram illustrating the operation of the device of FIG. 25

Figure 27 is a circuit diagram of the main part of the device of Figure 25.

28 is a block diagram of another embodiment of a dimming discharge lamp lighting apparatus according to the present invention

29 (a) and 29 (b) are explanatory diagrams of the FIG. 28 device.

30 is a detailed circuit diagram of the main part of the device.

FIG. 31 is a detailed circuit diagram of the control means of the device of FIG. 28. FIG.

FIG. 32 is a schematic view of the main parts of another form of the device.

33 is a block diagram of another form of the device of FIG.

34 is a circuit diagram of the main part of the apparatus.

35 is a view showing the relative lighting rate and the required voltage relationship of the dimming discharge lamp lighting apparatus according to the present invention

36 is a diagram showing the relative illumination rate and the required voltage relationship of the device without the DC power supply means according to the present invention.

The present invention can stably illuminate the discharge lamp even at a very low luminous flux level, and the discharge lamp illuminator enables to stably illuminate the discharge lamp of the dimming illuminator even when the luminous flux level is lowered from the arc discharge section to the glow discharge section. It is about.

In general, in a discharge lamp lighting apparatus, intentionally lowering the possible illumination level is subject to certain limitations because the lamp is not provided with a means for stably lighting the lamp at a low luminous flux. As the lamp current flowing through the lamp is lowered, the discharge lighting cannot keep the lamp ultimately off, i.e., the so-called flicker-off state, and can hardly maintain the illumination at a low luminous flux level.

If the relative illumination rate exceeds 20% for the illumination under rated current lighting, which is set at 100%, the flicker-off state can hardly occur.

Therefore, in the discharge lamp lighting apparatus, a device in which the relative illumination rate is set to 20% or more is commercially available, and there is a tendency for a lighting that can be obtained widely in practice.

When conditions such as the amount of preheating current supplied to discharge the lamp filament or the amount of voltage supplied to the discharge lamp are satisfied, low luminous flux lighting can be achieved and the discharge lamp can be illuminated up to 5% of the relative illumination rate. Discharge lamp lighting apparatus has already been provided.

However, in order to satisfy the conditions of the amount of preheating current and supply voltage, the structure of the device is complicated and the problem of raising the manufacturing cost has been raised.

An assembly has been proposed in which a discharge lamp that hardly flickers off, such as “F40SP35” manufactured by General Electric of the United States, is incorporated into a conventional dimming discharge lamp lighting device as described in US Pat. No. 4,663,570. Application of the discharge lamp is limited to the user to freely select the discharge lamp, there was a problem that can not easily purchase this discharge lamp on the market.

For example, Japanese Patent Laid-Open No. 61-296695 describes a means for preventing the discharge lamp from flickering by applying a high voltage pulse (for example, 1,000 V having a pulse width of 300 μsec) periodically (for example, every 10 msec) to the discharge lamp. .

This is very efficient in preventing the discharge lamp from flickering off, and since the high voltage pulse periodically applied is in the audible range, the circuit element forming the lighting device is subjected to excessive stress due to the high voltage pulse application.

In a discharge lamp lighting device having means for preventing flicker-off, when the device is operated at a low luminous flux level, the ultimate light emission becomes bright at the end of the lamp tube, not at the center of the lamp tube. In the case of a high frequency illumination type discharge lamp lighting apparatus using a system in which the inner tube is covered with a conductor, it is remarkably generated.

In addition, Japanese Laid-Open Patent Publication No. 57-118396 and West German Patent Publication No. 3,313,916 describe a device in which a high frequency power is supplied to a discharge lamp and a DC power source is superimposed on and applied to the high frequency power. In this discharge lamp lighting apparatus, the DC zircies resulting from the applied DC power supply are applied to the discharge lamp current of the supplied high frequency power supply, thereby eliminating phenomena such as streaks appearing in the discharge lamp tube, thereby achieving stable lighting.

However, in this lighting device, low luminous flux cannot be achieved at all.

That is, such a device cannot achieve the technical idea of providing a discharge lamp lighting device with a relative lighting rate of more than 20% for lighting under a rated current set to 100%, and cannot display stable discharge lamp lighting, The device for this could not be manufactured at low luminous flux levels.

Therefore, there is an urgent need to achieve stable illumination at a much lower luminous flux level, which is a relative illumination rate of 5% or much lower than that of conventional devices.

Therefore, the basic purpose of the present invention is to obtain a stable light at extremely low luminous flux level of 20% or less of the relative illumination rate, in particular 5% or less, for illumination under the rated condition set to 100%, and from 100% illumination under the rated condition. Disclosure of the Invention The present invention provides a discharge lamp lighting apparatus capable of stably obtaining a wide range of illumination of a discharge lamp up to a very low luminous flux level of 5% or less of relative lighting rate.

According to the present invention, the above object can be achieved by a discharge lamp lighting device supplied from a high frequency power supply to a low intensity mercury arc discharge lamp via a control means to operate a discharge lamp to be illuminated with a high frequency power source. The apparatus includes a DC power supply means for applying a DC power supply to a low intensity mercury arc discharge lamp at a level capable of maintaining a discharge during low luminous flux by superimposing a lamp on a high frequency power supply.

Other objects and advantages of the present invention will become apparent from the following description described in detail with reference to the embodiments of the present invention shown in the accompanying drawings.

Although the present invention has been described with reference to the respective embodiments shown in the accompanying drawings, the present invention is not limited to the embodiments, and there may be many changes and modifications within the scope of the following claims.

Referring to FIG. 1, which shows a basic embodiment of a dimming discharge lamp lighting apparatus according to the present invention, the apparatus generally has a low intensity mercury arc discharge lamp 10 and a high frequency power supplying high frequency power to the discharge lamp 10. FIG. The power supply unit 11, the dimming control means 12 for dimming the discharge lamp 10 from the arc discharge unit to the glow discharge unit, and the high frequency power supply from the high frequency power supply unit 11 overlap the discharge lamp 10. Therefore, it is composed of a DC power supply means 13 for supplying a DC power supply to the discharge lamp 10 of a level capable of maintaining a discharge during low luminous flux lighting, the DC power supply means 13 includes a DC power supply portion 14 do.

In this case, in the above structure, the control signal of the dimming control means 12 for controlling the dimming of the discharge lamp 10 is transmitted to the high frequency power supply section 11, the impedance elements Z ₁ , Z ₂ and the DC power supply section 14. Although each is configured to be provided simultaneously, this structure may not provide control signals to all such components at the same time.

For example, the control signal may be provided only to the high frequency power supply unit 11, and the high frequency output obtained from the high frequency power supply unit 11 may perform dimming by varying its frequency to control the voltage supplied to the discharge lamp 10.

In addition, the control signal may be input from the dimming control means 12 to the DC power supply 14 so that the DC component from the DC power supply means 13 is variable, and the DC component optimized according to the dimming rate is discharged. May be applied to the lamp 10.

In the impedance elements Z ₁ and Z ₂ respectively disposed between the high frequency power supply 11 and the discharge lamp 10 and between the DC power supply 14 and the discharge lamp 10, among them, the impedance element Z ₁ . By including the saturation inductance, the value of this inductance can be controlled by a control signal input therein to perform dimming. By forming another impedance element Z ₂ as a resistance element and a switching element, the switching element may be turned on / off by a control signal provided to the impedance element Z ₂ , and the DC power applied to the discharge lamp 10 may be It may be controlled as the amount of overlap.

In this case, the impedance element Z ₂ is composed only of the switching element, and the impedance of the discharge lamp 10 may be used as the impedance of the resistance element.

When AC high frequency power is applied to the discharge lamp 10, the current flowing in the discharge lamp 10 can be considered to be divided into a main current and a dark (dark) current.

Referring to the equivalent circuit of the discharge lamp 10 shown in FIG. 2, the discharge path is the negative resistance 1a, the negative resistance 1a and the capacitive impedance 1b disposed between the lamp tube wall, and It is assumed that it includes a capacitive impedance 1c disposed between the lamp filaments F ₁ , F ₂ and the lamp tube wall.

When the discharge lamp 10 emits light by the rated current applied thereto, the main current flows sufficiently through the filaments F ₁ and F ₂ to the discharge path to maintain the discharge path indicated by the negative resistance 1a. .

On the other hand, as the dimming is performed, the main current is decreased so that the ratio of the dark current is relatively increased. This dark current does not contribute to light emission, and as the dimming is performed above a predetermined level, a negative resistance for forming a discharge path is obtained. The current flowing through 1a flows only through the pipe wall impedance 1d through the capacitive impedance 1b between the negative resistance 1a and the pipe wall, so that the discharge path can no longer be maintained.

Therefore, all supply currents become dark currents, and flicker off occurs in the discharge lamp 10.

The relationship between the voltage and the relative illumination rate for illumination under 100% of the rated light is that the high-frequency power supply is 40 KH _Z high-frequency power supply, and the inner conductor-covered type (eg, FLR40W-F1MX ”) measured by supplying a straight 40W tube of low-intensity mercury arc discharge lamp to apply a preheating current (IP = 0.4A) to it and varying the high frequency power to the discharge lamp for its dimming operation. The measurement results are shown graphically in FIG.

As can be seen from the graph, the ramp voltage rises as the relative illumination rate decreases, and this rise suddenly changes when the relative illumination rate is about 10-20%, and the resulting ramp voltage rises about 5%. Since the lamp is suddenly lowered toward the relative illumination rate of the lamp, the discharge lamp illumination is flickered off when the relative illumination rate is about 5%.

This tendency is remarkable when the lamp temperature is lowered, and the lighting of the discharge lamp is difficult to maintain when the relative lighting rate is 20% or less regardless of the lamp temperature, and the lighting is about 5% relative lighting temperature at different lamp temperatures. Flicker off.

Similar measures are also taken for other types of low intensity mercury arc discharge lamps, with substantially the same results.

As described above, it is necessary to set a discharge path for performing dimming at a very low level of relative illumination, and for this purpose, it is necessary to supply a current so that it does not become a dark current. The applied current requires a DC current, and for this, the current is an impedance element 1b between the negative resistance 1a and the lamp tube wall, and an impedance element 1c between the filaments F ₁ and F ₂ and the lamp tube wall. Will not flow through a capacitive impedance element such as

According to the present invention, since the DC power at a level capable of maintaining the discharge at a low luminous flux is applied to the discharge lamp 10 when superimposed on the high frequency power by the DC power supply means 13, as shown in FIG. In order to limit or significantly reduce the dark current, no current flows through the capacitive impedance elements 1b and 1c so that the discharge path can be set.

Therefore, as shown in FIG. 36, the relationship between the lamp voltage and the relative illumination rate, that is, the luminous flux is an inner surface conductor such as the FLR 40S / MX-36 manufactured by a positive company that saw power through a high frequency power supply and an insulating transformer. Supply to the straight 40W tube of the clad low intensity mercury arc prevention lamp, apply DC power superimposed on the power by DC power supply means 13, provide preheating current (IP = 0.4A), and Obtained by performing illumination by varying. Such measurement results are shown in FIG. 35, and the discharge lamp lighting apparatus according to the present invention can realize lamp lighting at a very low luminous flux level without any flicker off, and the illumination has a weak relative illumination rate or luminous flux. Even lowering to 0.1% can be obtained.

The actual structure of the present invention will be described in detail.

Referring to FIG. 3, a high-frequency voltage by a commercial AC power source (V _S) of the AC voltage is the following, the high frequency conversion circuit (11B) converted to a DC voltage by a DC converting circuit (11A) of the high-frequency power source 11 The high frequency voltage is applied to the discharge lamp 10 through the resonant circuit 11C.

At the same time, the preheating current is supplied from the preheating circuit 11D in the filaments F ₁ and F ₂ of the discharge lamp 10. The high frequency voltage obtained by the high frequency conversion circuit 11B is converted into a DC voltage by the DC conversion circuit 13A in the DC power supply means 13, and this DC voltage is transferred through the impedance element 13B and the diode 13C. Since it is applied to the discharge lamp 10, the DC power supply of a level capable of maintaining the discharge during low luminous flux can be applied to the discharge lamp by overlapping the high frequency power supply.

4 also has a third Toba doeeotneun a detailed circuit diagram of the apparatus shown, in this case, a commercial AC power source (V _S) is a fuse (F) and a filter coil (FC _1, FC ₂₎ in the DC conversion circuit (11A) It is connected to the AC input terminal of the diode bridge (DB ₁ ).

A surge hop condenser (ZNR) and an anti-noise condenser (C ₁ ) are connected in parallel to the input side of the filter coil (FC ₁ ), and an anti-noise condenser (C ₂ , C ₃ ) on the input / output side of the filter coil (FC ₂ ). Each is connected in parallel. _One end of the inductor CH ₁ is connected to the positive output terminal of the diode bridge DB ₁ , and the other end of the inductor CH ₁ is connected to the drain terminal of the MOS transistor Q ₁ operating as a chopper.

The source terminal of the MOS transistor Q ₁ is connected to the negative output terminal of the diode bridge DB ₁ via a resistor R ₁ , and the anode and the cathode of the backflow prevention diode D ₁ are connected to the drain terminal thereof. One end of the series circuit of the condenser C ₄ , C ₅ is connected, and the other end of the series circuit is connected to the negative output terminal of the diode bridge DB ₁ .

In a series circuit composed of capacitors (C ₄ , C ₅ ), a direct connection circuit composed of resistors (R ₂ , R ₃ ) and variable resistor (VR ₁ ) is connected in parallel, and between resistors (R ₂ ) and (R ₃ ) The connection point "b" forms a detection terminal for detecting the DC voltage VDC obtained in the series circuit of the capacitors C ₄ and C ₅ .

In the DC conversion circuit 11A configured as described above, the MOS transistor Q ₁ is turned on / off at high speed by the oscillation output “Q” of the oscillation circuit to be described later.

When a MOS transistor (Q ₁₎ on first, DC output of the diode bridge (DB ₁₎ is so configured to short-circuit by the inductor (CH ₁₎ the current flowing through the inductor (CH ₁₎ is of the diode bridge (DB ₁₎ It is increased in proportion to the magnitude of the DC output voltage, and energy is accumulated in the inductor CH ₁ . When the MOS transistor Q ₁ is turned off, since the energy in the inductor CH ₁ is discharged, a boosting chopper circuit is formed to charge the capacitors C ₄ and C ₅ through the diode D ₁ . even if the voltage of the AC power source (V _S) is temporarily lowered to the charge current flows to the capacitor (C _4, C _5), capacitors (C _4, C ₅₎ DC voltage (VDC) is a sufficiently smooth.

By on / off at a high speed for a MOS transistor (Q ₁₎ in this way, the input current can always flow from the commercial AC power source (V _S) to the inductor (CH ₁₎ parameters, inductor (CH ₁₎ is a sine wave current Will have a waveform.

When these current waveforms are filtered and continuous by the filter coils FC ₁ and FC ₂ and the noise preventing capacitors C _{1 to} C ₃ , the current output from the commercial AC power supply unit V _S is applied to the input voltage V IN. The in-paint has a sine pie, and the input power factor will be substantially one.

In addition, the input current will have a low distortion rate, and the harmonic components will be low.

Here, the filter coils FC ₁ and FC ₂ and the noise preventing capacitors C _{1 to} C ₃ are set to time constants so that low impedance for commercial AC frequencies and high impedance for switching frequencies of the MOS transistors Q ₁ are provided. Will be displayed.

In the high frequency conversion circuit 11B, the positive output terminal of the DC conversion circuit 11A is connected to the drain terminal of the MOS transistor Q ₂ , and the source terminal of the MOS transistor Q _{3 is} connected through the resistor R ₆ . Since the drain terminal is connected, the source terminal of the MOS transistor Q ₃ is connected to the negative output terminal of the DC conversion circuit 11A via the resistor R ₉ .

Here, the resistors R ₁ , R ₆ , and R ₉ connected in series to the source terminals of the MOS transistors Q ₁ , Q ₂ , and Q ₃ are for overcurrent protection. The drain of the MOS transistor Q ₃ is connected to a next load circuit composed of a preheating circuit 11D, a resonant circuit 11C, and a discharge lamp 10 via a DC component blocking capacitor C ₆ . .

In the high frequency conversion circuit 11B, the MOS transistor Q _{2 at the} high potential side is turned on / off by a first drive signal applied to the high potential side driving terminals “C” and “D”, where the MOS transistor ( The gate terminal of Q ₂ ) is connected to the driving terminal “d” through the resistor R ₅ .

A resistor R ₄ is connected between the driving terminal “c” and the gate terminal of the MOS transistor Q _2. The resistor R ₄ has a series circuit composed of a resistor R ₃₀ and a diode D ₁ 6. Connected in parallel.

Since the high potential drive terminal "c" is controlled by the inverter control means described later, the "H" level and "L" level states will change the high frequency according to the high potential terminal "d".

When this driving terminal “c” is at the “H” level with respect to the high potential terminal “d”, the divided voltage of the “H” level voltage by the resistors R ₄ and R ₅ is the gate of the MOS transistor Q ₂ . bar is applied to the terminal, a voltage (VGS) between the gate and the source of the MOS transistor (Q ₂₎ is elevated so MOS transistor (Q ₂₎ is turned on.

When the driving terminal “c” is at the “L” level with respect to the high potential terminal “d”, the charge accumulated in the capacitor across the gate and the source of the MOS transistor Q ₂ is increased in the diode D ₁ and the resistor R _30. ), And the voltage VGS between the gate and the source of the MOS transistor Q ₂ is lowered, so that the MOS transistor is turned off.

At this time, the MOS transistor Q ₃ on the low potential side is turned on by the low potential side driving terminal “c” and the second driving signal applied through the ground.

Here another low potential drive terminal "e" is controlled to change between the "H" level and the "L" level state with respect to ground as reference by the inverter control means to describe the high frequency later.

The driving circuit of the MOS transistor Q ₃ and its operation are substantially the same as that of the MOS transistor Q ₂ , and the resistors R ₇ , R ₈ , R _{31 are} connected to the resistors R ₄ , R ₅ , R ₃₀ . And diode D ₇ corresponds to diode D ₆ .

In this case, the first and second drive signals do not become the "H" level at the same time, the first period in which the first drive signal is the "H" level and the second drive signal is the "L" level, and the first and second A second period in which the driving signals are all at the "L" level, a third period in which the first driving signals are at the "L" level, and a third period in which the second driving signals are at the "H" level, and both the first and driving signals are at the "L" level The fourth period, which is a level, is repeated continuously in this order.

In more detail, since the MOS transistor Q ₂ is turned on and the MOS transistor Q ₃ is turned off during the first cycle, the current flows from the constant output terminal of the DC conversion circuit 11A to the MOS transistor Q ₂ , It will flow through the path leading to the negative output terminal of the DC conversion circuit 11A via the resistor R ₆ , the DC component blocking capacitor C ₆ , and the load circuit.

In the second period, since the MOS transistors Q ₂ and Q ₃ are simultaneously turned off, the oscillation current will flow through the reverse parallel diode D ₁₀₂ parasiticly coupled to the drain and the source of the MOS transistor Q ₃ . In the third cycle, the MOS transistor Q ₂ is turned off and the MOS transistor Q ₃ is turned on, so that a current is transferred from the capacitor C ₆ by the capacitor C ₆ for blocking the DC component formed as a power supply. It will flow through a path leading to capacitor C ₆ via transistor Q ₃ , resistor R ₉ and load circuit.

During the fourth cycle, since the MOS transistors Q ₂ and Q ₃ are simultaneously turned off, the oscillating current of the load circuit is transferred through the reverse parallel diode D ₁₀₁ parasiticly coupled to the drain and the source of the MOS transistor Q ₂ . As a result, a high frequency alternating current flows through the load circuit.

The MOS transistors Q ₂ and Q ₃ may set a switching frequency slightly higher than the non-oscillation frequency of the load circuit.

Then, the preheating circuit 11D is first and second connected to the primary winding connected to the high frequency output of the high frequency conversion circuit 11B and the first and second filaments F ₁ and F ₂ of the discharge lamp 10, respectively. It consists of a preheating transformer (T ₁ ) having a secondary winding of the bar, the high frequency voltage at which the high frequency output of the high frequency conversion circuit 11B is stepped down is applied to the filaments (F ₁ , F ₂ ) of the discharge lamp 10 Preheat them according to high frequency. The high frequency voltage obtained from the third secondary winding of the preheating transformer T ₁ is supplied to the DC conversion circuit 13A to be a power source of the DC power supply means 13.

The resonant circuit 11C includes a series circuit of an inductor CH ₂ and a capacitor C ₇ connected to the high frequency output of the high frequency conversion circuit 11B, and the discharge lamp 10 includes a C ₈ and a filter FC. ₃ ) is connected to the capacitor (C ₇ ) via a medium, so the lamp 10 will be activated and emit light by resonating the high frequency output of the high frequency conversion circuit (11B). Here, the filter FC ₃ performs a noise protection function.

The DC conversion circuit 13A in the DC power supply means 13 includes a diode D ₉ for rectifying the high frequency voltage obtained in the third secondary winding of the preheating transformer T ₁ , and a smoothing voltage for the rectified voltage. Since it is composed of the smoothing capacitor (C ₉ ), the power supply will provide a power supply so that the high frequency voltage, which is the output of the high frequency conversion circuit 11B, is rectified and smoothed.

The DC voltage obtained at the smoothing capacitor C ₉ is applied to the discharge lamp through the inductor CH ₃ and the diode D ₂ . The inductor CH ₃ acting as the impedance element 13B may be an impedance due to its copper loss component with respect to direct current, but indicates an inductance value of the inductor CH ₃ with respect to the high frequency from the resonant circuit 11C. Since the inductive reactance JWL having L ″ is an impedance, it is possible to achieve a function of preventing a certain avoidance for high frequency.

In FIG. 3, the diode D ₂ corresponding to the diode 13c prevents the smoothing capacitor C ₉ from being charged by the voltage applied to the discharge lamp 10.

The DC voltage from the DC power supply means 13 is blocked by the condenser C ₈ so as not to flow into the preheating transformer T ₁ of the preheating circuit 11D, but only to the main current path to the discharge lamp 10. do.

As described above, the high frequency voltage from the high frequency conversion circuit 11B is applied to the discharge lamp 10, and the DC voltage from the DC power supply means 13 is superimposed there.

Since the voltage obtained from the capacitors C ₄ and C ₅ of the DC conversion circuit 11A is the smoothed DC voltage, the envelope of the high frequency voltage from the high frequency conversion circuit 11B becomes flat, so that the discharge lamp 10 The light output of does not substantially generate flicker.

Referring to the dimming control means 12, this dimming control means 12 is a chopper control circuit part for controlling the MOS transistor Q ₁ used as a chopper for voltage boosting of the DC conversion circuit 11A, and a high frequency conversion circuit. An inverter control circuit section for controlling the MOS transistors Q ₂ , Q ₃ of 11B, and a control power supply circuit section for supplying the control voltage Vcc to these circuit sections.

First, the control power circuit unit includes a primary winding connected to both ends of the capacitor C ₂ of the DC conversion circuit 11A, and a diode bridge DB in which the capacitor C ₁₀ and the zener diode ZD ₁ are connected in parallel to the DC output terminal. ₂ ) a step-down transformer (T ₂ ) having a secondary winding connected to the AC input of the bar, the anode of the zener diode (ZD ₁ ) is connected to ground, and its cathode has an operating voltage (Vcc) for the circuit parts. ) Is applied.

The chopper control circuit section includes an oscillation circuit (IC1) such as an IC for controlling a switching regulator such as "μPC 494C" manufactured by NEC of Japan. The control IC receives the control voltage (Vcc) through the power supply terminal (pin 12) and the ground terminal (pin 7), and a capacitor (C ₁₄ ) connected between the condenser terminal (pin 5) and the ground terminal. An oscillator that oscillates at a predetermined frequency according to a time constant determined by a resistor R ₁₄ connected between the resistor terminal (No. 6 pin) and the ground terminal is embedded.

The first oscillation output is obtained by a change between the short-circuit state and the open state via the first open collector terminal (pin 8) and the first open emitter terminal (pin 9), and the second oscillation output is the second open collector terminal (11). Burn pin) and a short-circuit open state via the second open emitter terminal (pin 10).

When the output control terminal (pin 13) is at ground level, the IC performs a single completion operation of a single element, so the first oscillating output corresponds to the second oscillating output, and the output control terminal is connected to the reference voltage output terminal (pin 14). Since the push-pull operation for the two elements is performed when the reference voltage Vref is obtained, the first and second oscillation outputs are the reference voltages of the resistors R ₁₀ (R ₃₃ ) and the variable resistor VR ₂ . The divided voltage of (Vref) is input to the deadoff time control terminal (pin 4), and is generated in opposite states through a predetermined deadoff time that can be set.

Also, the non-inverting terminals (pins 1 and 16) and the inverting terminals (pins 2 and 15) are input terminals of an error amplifier circuit for pulse width control.

In this case, the first non-inverting terminal (pin ₁ ) receives the divided voltage of the output voltage VDC of the DC conversion circuit 11A by the resistors R _{2 and} R ₃ and the variable resistor VR ₁ . The terminal is connected to ground via a capacitor C ₁₂ . The first inverting terminal (pin 2) receives a divided voltage of the reference voltage Vref by the resistors R ₁₁ and R ₁₂ .

On the other hand, the second non-inverting input terminal (pin 16) is connected to the ground, the second inverting input terminal (pin 15) is connected to the control voltage (Vcc), these terminals are not used.

The feedback terminal (pin 3) is a feedback input terminal connected to the first inverting input terminal (pin 2) through a resistor (R ₁₃ ) and a capacitor (C ₁₃ ).

In the above-described structure, since the output control terminal (pin 13) is connected to the ground, the first and second oscillation outputs are generated at the same time, and their oscillation frequency is dependent on the time constant of the resistors (R ₁₄ and) capacitor C ₁₄ . The pulse width is controlled to eliminate a predetermined voltage change generated at the output voltage VDC of the DC conversion circuit 11A.

The oscillation output of the oscillation circuit IC ₁ is supplied to the driving terminal “a” of the MOS transistor Q ₁ through a driving circuit including the transistors Q _{4 to} Q ₆ . In a driving circuit including transistors Q _{4 to} Q ₆ , the first and second open emitter terminals (pins 9 and 10) are connected to ground, and the first and second open collector terminals (8 and 8). Pin 11) is connected to the base of transistor Q ₄ . When the first and second open collector terminals are in a non-conductive state together with the first and second open emitter terminals, the bias voltage obtained by dividing the control voltage Vcc by the resistors R ₁₅ and R ₁₆ is a transistor. Is applied to the base of (Q ₄ ).

On the other hand, the case is in the first and second open collector terminals of the first and second open-conductive state with the emitter terminal, the base of the transistor (Q ₄₎ is grounded because the transistor (Q ₄₎ is turned off.

The emitter of transistor Q ₄ is connected to ground, and its collector is connected to control power supply voltage Vcc and the base of transistor Q ₅ (Q ₆ ) via resistor R ₁₇ .

When the transistor Q ₄ is turned on, a low potential is applied to the base of the transistors Q ₅ Q ₆ to turn off the transistor Q ₄ , and the bases of the transistors Q ₅ and Q ₆ are biased in a high state. Voltage is applied. The collector of transistor Q ₅ is connected to control voltage Vcc and the collector of transistor Q ₆ is connected to ground.

The emitters of the transistors Q ₅ and Q ₆ are connected to the driving terminal “a” of the MOS transistor Q ₁ via a parallel circuit consisting of a resistor R ₁₈ and a diode D ₄ , which is grounded. Is connected to. Transistor Q ₅ is an NPN transistor and transistor Q ₆ is a PNP transistor. When the base potential of these transistors is raised, transistor Q ₅ is turned on and transistor Q ₆ is turned off so transistor Q ₅ ) and current flows from the control voltage (Vcc) via resistor (R ₁₈ ) (R ₃₃ ), and voltage is generated through resistor (R ₃₂ ).

The generated voltage of the gate bar, the transistor (Q ₁₎ to be applied to the drive terminal "a" of the MOS transistor (Q ₁₎ - is the source potential rises the transistor (Q ₁₎ is turned on.

As the transistor Q ₄ is turned on and the base potential of the transistors Q ₅ and Q ₆ is lowered, the transistor Q ₅ is turned off, and the charge accumulated through the gate-source of the MOS transistor Q ₁ is diode. Discharges through (D ₄ ), passes through the emitter-base of transistor Q ₆ , and passes through the collector-emitter of transistor Q ₄ , so that a base current flows through transistor Q ₆ . Therefore the collector of the transistor (Q ₆₎ -, and the conduction through the emitter, the gate of the MOS transistor (Q ₁₎ - the electric charge through the source storage since the rapid discharge is formed in the driving circuit of the MOS transistor (Q _1).

The inverter control circuit section includes an oscillation circuit IC ₃ which is a control IC (μPC494C of NEC) used for the switching regulator, each terminal of which is substantially the same as the function of the oscillation circuit IC ₁ described above. Do.

In this oscillation circuit (IC ₃ ), non-inverting input terminals (pins 1 and 16) and inverting input terminals (pins 2 and 15) for controlling the pulse width are not used, and the former terminals are connected to ground. The latter terminals are connected to the reference voltage Vref obtained from the reference voltage output terminal (pin 14). Since the reference voltage Vref is applied to the output control terminal (pin 13), the oscillation circuit IC ₃ performs the push-pull operation, and the reference voltage (V) by the resistor R ₂₅ and the variable resistor VR ₃ is applied. The divided voltage of Vref) is applied to the dead-off time terminal (pin 4) to set the dead-off time. The capacitor terminal (pin 5) is connected to ground through a capacitor (C ₁₉ ), the resistor terminal (pin 6) is connected to ground through a resistor (R ₂₄ ) and a variable resistor (VR ₄ ).

The oscillation frequency of the oscillation circuit IC ₃ is determined by the time constant by the capacitor C ₁₉ , the resistor R ₂₄ , and the variable resistor VR ₄ .

Since the variable resistor VR ₄ and the capacitor C ₁₈ are connected in parallel, the oscillation frequency of the oscillation circuit IC ₃ will gradually change even if the resistance value of the variable resistor VR ₄ changes rapidly. The control voltage Vcc is applied between the source terminal (pin 12) and the ground terminal (pin 7). The first and second open emitter terminals (pins 9 and 10) are connected to ground, and the first and second open collector terminals (pins 8 and 11) are connected to the control voltage through resistors R ₂₆ and R ₂₇ . Vcc is connected to the input terminals of the first and second inverters G1 and G2, respectively.

When the first open collector terminal (pin 8) is connected to the first open emitter terminal (pin 9), the first open collector terminal (pin 8) becomes “L” level, and the first inverter G1 is “H”. Generates a level output.

As the first open collector terminal (pin 8) is in a non-conductive state with the first open emitter terminal (pin 9), the first open collector terminal (pin 8) becomes the control voltage (Vcc) via a resistor (R ₂₆ ). ) Is at the "H" level, and the output of the first inverter G1 is at the "L" level.

Similarly, when the second open collector terminal (pin 11) is in a conductive state with the second open emitter terminal (pin 10), the output of the second inverter (G2) becomes the "H" level, but they are nonconductive When in the state, the output of the second inverter (G2) will be at the "L" level.

In addition, the inverter control circuit portion includes a drive circuit IC ₄ using a high speed, high breakdown voltage bridge driver IC (“IR 2110” manufactured by IR of USA).

Here, input terminals 12 and 10 are connected to output terminals of inverters G1 and G2, respectively, and a drive signal is provided to output terminals (pins 1 and 7) having the same waveform and dielectric strength of 500V. . One of these outputs obtained at the first output terminal (pin 1) is supplied to the drive terminal “e” of the MOS transistor Q ₃ at the low potential side via the inverter G3 and the inverter group BF1. The high potential terminal (pin 5) of the driving circuit IC ₄ is connected to the terminal “d” of the MOS transistor Q ₂ .

The other output obtained at the second output terminal (pin 7) is supplied to the driving terminal “c” of the MOS transistor Q ₂ at the high potential side via the inverted schmitt gate G5 and the inverter group BF2. The circuit of the diode D ₅ , the resistor R ₂₈ , and the capacitor C ₂₀ uses a so-called boost circuit for supplying a driving signal voltage to the high potential drive signal obtained from the second output terminal (pin 7). Form.

The voltage obtained through the capacitor C ₂₀ is limited to the constant voltage by the zener diode ZD ₂ . When the voltage of the capacitor C ₂₀ is lower than the predetermined level, the output of the Schmitt inverter G4 becomes the “L” level, and the signal is blocked to pass through the inverted Schmitt gate G5. As the voltage of the capacitor C ₂₀ rises and the voltage exceeding the threshold level is input to the Schmitt buffer G4 by the constant voltage circuit composed of the resistor R ₂₉ and the zener diode ZD ₃ , the Schmitt buffer The output of (G4) goes to the "H" level and the signal passes through the inverted Schmitt gate (G4).

In the discharge lamp lighting apparatus according to the present invention including the above-described dimming control means 12, the operating frequency of the high frequency conversion circuit 11B can be changed by changing the value of the variable resistor VR ₄ , so-called Frequency dimming is possible.

In this case, the switching frequency of the MOS transistors Q ₂ and Q ₃ is performed stably since the operating frequency of the high frequency conversion circuit 11B, which is changed to a range higher than the natural oscillation frequency of the load circuit, generates a mag current flowing through the load circuit. Can be.

In particular, the operating frequency of the conversion circuit 11B gradually reduces the value of the variable resistor VR ₄ , thereby gradually separating the natural oscillation frequency of the load circuit, thereby gradually weakening the resonance of the resonant circuit 11C. Thus, dimming of the discharge lamp 10 can be achieved.

Since the value of the variable resistor VR ₄ can be changed continuously, dimming of the discharge lamp can be obtained continuously.

The above-described high frequency operation of the circuit is shown in Figs. 5 (a) and 5 (b). Fig. 5 (a) shows the fully illuminated state of the discharge lamp 10. FIG. 10 shows a dimming illumination state of the discharge lamp 10.

As can be seen from the figure, the oscillation frequency is increased by decreasing the value of the variable resistor VR ₄ , and the resonant current ICH ₂ flowing in the inductor CH ₂ is small, and thus the lamp current ILa is also reduced. .

At this time, the ratio of the DC bias component occupied by the ramp voltage VLa is increased.

As can be seen from FIG. 6 showing the low frequency operation of the circuit, the value of the variable resistor VR ₄ is made small to increase the DC bias component ratio at the ramp voltage VLa.

The voltage waveform and the current waveform are positive in the directions shown by the arrows in FIG. 4, respectively.

In the discharge lamp lighting apparatus of the present embodiment, the outer conductor coating, the inner conductor coating, and PSC (a kind of inner conductor coating in which the krypton is sealed in the discharge lamp tube to store energy) are applied to various discharge lamps. The test was carried out and a result as shown in FIG. 35 was obtained. According to this, stably controlled dimming can be obtained by the device in each lamp for a low luminous flux level lower than a relative illumination rate of 5%.

Also, in addition to the object of the present invention that can be obtained in the above circuit, the DC voltage value applied to the discharge lamp 10 is selectively set, and the voltage value can be set relatively low as about 40V. Before mounting, the voltage across the lamp and socket can be set low for safety.

In addition, during the initial operation of the discharge lamp 10, the DC voltage from the DC power supply means 13 is superimposed on the high frequency voltage by the oscillation circuit 23 as shown in FIG. The peak value of the voltage applied to (10) becomes high as shown in FIG. 7 (b) to improve the maneuverability.

In the above embodiment, frequency dimming is used as the dimming means, but other dimming systems such as duty control may be used.

Although a so-called half-wave bridge inverter system has been described for the high frequency conversion circuit 11B, a single element inverter system or a full-wave bridge inverter system may be used.

The inductor was used as the impedance element 13B, but another impedance element such as a resistor may be used, and the preheating transformer T ₁ used in the preheating circuit 13D may be replaced by a capacitor that is preheated by the resonant capacitor. .

Referring to FIG. 8, which shows the different operating characteristics of the discharge lamp lighting apparatus of FIG. 1, one DC conversion circuit 21A is used instead of the two DC conversion circuits 11A and 13A in FIG. Is placed.

That is, the DC voltage of the DC conversion circuit 21A is applied to the discharge lamp 10 via the DC power supply means 23 composed of the impedance element 23B and the diode 23C, and is superimposed on the high frequency power supply.

In the illustrated embodiment, the diode 23C inserted in series between the discharge lamp 10 and the impedance element 23B when the DC voltage is higher than the lamp voltage or 100K having a very high impedance of the impedance element 23B. ) Can be omitted, so the avoidance of high frequency power supply to DC power supply can be regarded as small.

In this embodiment, the same parts as those in FIG. 3 are denoted by the same reference numerals by adding 10 to that in FIG. 3, and the other parts and their functions are substantially the same as those in FIG.

According to another feature of the present invention, there is provided a discharge lamp lighting apparatus having a variable value of the power supply of the DC power supply means. The main part of the discharge lamp lighting apparatus for operating a specific type is shown in FIG. 9, wherein the high frequency voltage that can be obtained by the preheating transformer T ₁ in the preheating circuit 31D is a saturated reactor ICH _1. ) the bar to be supplied to the rectifier diode (D ₃₎ as a medium, a saturated reactor (ICH ₁₎ is controlled by the dimming control means (12) for setting a selected inductance supplied to the smoothing capacitor (C ₉₎ from the high-frequency power supply section The power source is controlled and the voltage of the DC power supply unit 33 is optionally set to a predetermined level. In this case, the voltage level may be set according to the light output of the discharge lamp 10 and the dimming level setting signal. In FIG. 9, the same elements as in FIG. 3 are shown with the same reference numerals by adding 20 to FIG. 3, and the other parts and their functions are substantially the same as in FIG.

According to another feature of the present invention, when the flicker-off of the discharge lamp 10 is generated, the discharge lamp lighting apparatus is provided so that the DC power is applied to the discharge lamp 10 by overlapping the high frequency power only as the dimming level By overlying the discharge lamp 10, it is possible to eliminate the risk of cataphoresis and shortening of lamp life that occur when DC power is always supplied.

The discharge lamp lighting device having the shape shown in FIG. 10 will be described in more detail. The device is provided with a lamp current detection circuit 43 which is a means for detecting the relative illumination rate.

In this case, a current transformer is inserted in series into the lamp current path, and a lamp current detection circuit 43D for detecting the lamp current is connected to this current transformer.

When the detected lamp current is large, the switching control circuit 43E connected to this circuit 43D is driven, and the switching connected in series between the discharge lamp 10 and the series circuit composed of the impedance element 43B and the diode 43C. Since the circuit 43F is turned on, the overlapping supply of the DC power supply to the discharge lamp 10 is such that the level of the lamp current supplied to the discharge lamp 10 does not flicker off the predetermined level, that is, the discharge lamp 10 during dimming. If it exceeds, it is stopped.

In this structure of the present invention, for the safety of the device, it is possible to prevent the PC voltage from being applied to the lamp socket in a no-load state (without a discharge lamp).

As a means for detecting the relative illumination rate, a detection circuit other than the lamp current detection circuit described above can detect the resonance current ICH ₂ flowing through the inductor CH ₂ in FIG.

Further, the drive signal for the switching control circuit 43 may be obtained by the dimming level setting signal as shown in FIG.

In the embodiment of Fig. 10, the same components as in Fig. 3 are denoted by the same reference numerals by adding 30 to Fig. 3, and the other structures and functions thereof are substantially the same as in Fig. 3.

11 shows another operating characteristic of the apparatus of FIG. 10, wherein the impedance element 43B, the diode 43C and the switching circuit 43F of FIG. 10 are formed of the first and second impedance elements 53B ₁ . 53B ₂ , first and second diodes 53C ₁ , 53C ₂ , and first and second switching circuits 53F ₁ and 53F ₂ , respectively.

In the present embodiment, three or more switching circuits 53F ₁ , 53F ₂ , .. 53F _n may be provided for the overlapping currents, so that the dimming level at which each switching circuit is turned on or off depends on the lamp current. It may be individually set to allow the DC power supply of an optimum value according to the dimming level to be superimposed and the dimming suitably realized.

In Fig. 11, the lamp current is detected by the lamp current detection circuit 53D, the switching circuits 53F ₁ and 53F ₂ are controlled through the switching circuit 54E, and a suitable DC current in response to the dimming level is Since it is configured to overlap the lamp current, the control signal is provided from the dimming control means 52 to the switching circuits 53F ₁ , 53F ₂ , or by the optimum dimming level setting signal as described with reference to the embodiment of FIG. 10. It is possible to change the device for controlling the switching circuits 53F ₁ , 53F ₂ .

On the other hand, in Figs. 10 and 11, since the hysteresis characteristics relating to the dimming level are preferably provided for the on or off operation of the respective switching circuits 53F ₁ and 53F ₂ , the discharge lamps 10 Although the switching operation due to the optical output difference of the discharge lamp 10 at the turn-on or turn-off time of the switching circuits 53F ₁ and 53F ₂ may generate flicker upon repetition, the flicker can be avoided by the hysteresis characteristic. .

In FIG. 11, the same components shown in FIG. 3 are denoted by the same reference numerals by adding 40 to those in FIG. 3, and other configurations and their functions are substantially the same as those in FIG.

According to still another feature of the present invention, there is provided a discharge lamp lighting apparatus for efficiently reducing a predetermined stress applied to a switching element included in a switching circuit.

For example, the apparatus of FIGS. 10 and 11 has a problem that the switching element requires a high voltage as the starting voltage in the switching circuit, and this problem can be solved by the apparatus embodying the shape of the present invention. Referring to the present apparatus with reference to FIG. 12, in comparison with the circuit of FIG. 1, the DC power supply control switching means SW ₁ for controlling the DC power supply to the discharge lamp 10 and at the time of startup of the discharge lamp 10 is shown. A parallel circuit of the overcurrent prevention switching means SW ₂ to be conducted is connected between the second impedance element Z ₂ and the DC power supply 64, and this switching means is replaced with a common switching element provided to achieve the same function. May be

Passive overvoltage protection devices, such as zener diodes, avalanche diodes, and surge hops, may be used as the switching means (SW ₂ ) for preventing the overcurrent, which is lower than the starting voltage of the lamp and lower than the lamp lighting voltage. It operates at high breakdown voltages and does not need to provide a separate control circuit for this device.

In FIG. 12, the same components as those in FIG. 1 are denoted by the same reference numerals by adding 50 to those in FIG. 1, and other structures and functions thereof are substantially the same as those in FIG.

The apparatus according to the embodiment of FIG. 12 is described in detail with reference to FIG. 13, which shows the main circuit of FIG. 12, the same components as shown in FIG. 4, which is the main circuit of the FIG. Reference numerals are used.

In this case, the commercial AC power supply V _S is connected to the AC input terminal of the diode bridge DB ₁ , and the capacitor C ₂₁ is connected to the DC output terminal of the diode bridge.

A series circuit of MOS transistors Q ₂ and Q ₃ is connected to both ends of the capacitor C ₂₁ connected in parallel. The primary winding of the capacitor C ₂₂ and the high frequency transformer T ₄ is directly connected to the drain terminal of the MOS transistor Q ₃ via the DC component removing capacitor C ₂₃ , and the discharge terminal discharges the capacitor. The source side terminal of the filament in the lamp 10 is connected via the primary winding of the inductor T ₅ .

Resonant and preheating current passing capacitors C ₂₄ are connected in parallel to the non-source side terminals of both filaments of the discharge lamp 10.

The secondary winding output of the high frequency transformer T ₁₄ is rectified by the diode D ₃ and smoothed by the capacitor C ₉ , whereby a DC voltage is obtained.

A capacitor (C _9), one end has a ratio of the filament of the discharge lamp 10 to the choke coil (CH ₃₎ mediators of - and any one of the source-side end is connected to the other end of the capacitor (C _9), the diodes (D ₂ ) And the other source side end of the other filament of the discharge lamp 10 via the MOS transistors Q ₇ , Q ₈ . Since the choke coil CH ₃ blocks the high frequency, the high frequency voltage applied to the discharge lamp 10 prevents leakage to the capacitor C ₉ .

The inductor T ₅ is formed in combination with the capacitor C ₂₄ and the LC series resonant circuit, which emits light by operating the discharge lamp 10 by the resonance voltage generated through the capacitor C ₂₄ .

The capacitors C _{22 and} C ₂₃ are for blocking the DC component and have a capacity larger than that of the capacitor C ₂₄ sufficient to not contribute to resonance.

The secondary winding of the inductor (T ₅ ) is connected to the AC input terminal of the diode bridge (DB ₃ ), the DC output terminal of the diode bridge is connected to a parallel circuit consisting of a capacitor (C ₂₅ ) and a resistor (R ₃₄ ), A voltage Vch corresponding to the resonance current is connected to the DC output terminal thereof, and this voltage Vch is supplied to the control circuit through the terminal "g".

In addition, the commercial AC power supply (V _S ) is connected to the AC input terminal of the other diode bridge (DB ₂ ) via the voltage drop transformer (T ₂ ), the DC output terminal of the capacitor (C ₁₀ ) and zener diode (ZD) The parallel circuit of ₁ ) is connected.

The DC voltage obtained at the capacitor C ₁₀ is supplied to the control circuit via the terminal “f”.

Terminals “h” and “i” are connected to the gate and the source of the MOS transistor Q ₂ so that a first control signal is supplied, and the second control signal is connected to the gate and ground of the MOS transistor Q ₃ . Supplied through. The first and second control signals are the same as those in the embodiment of Figs. 1-4, and the MOS transistors Q ₂ and Q ₃ perform the same inverter operation as in the embodiment.

In the embodiment illustrated in claim 13 also, the third control signal is supplied via the terminal "k" is connected to the gate and ground of the MOS transistor (Q ₇₎ MOS transistor (Q ₇₎ is on the discharge lamp (10) It will be challenged by the third control signal at a low luminous flux time to superimpose the DC power supply on the high frequency power supply.

Thus, the lamp will emit light stably without flickering off.

Also, the fourth control signal is challenged by a fourth control signal during the initial operation of the MOS transistor (Q ₈₎ is supplied via a terminal "l" is connected to the gate and grounding MOS transistor (Q ₈₎ of the discharge lamp (10) In this case, the initial driving high voltage is not applied to the MOS transistor Q ₇ during the initial driving of the lamp.

A control circuit for providing the first to fourth control signals to the main circuit shown in FIG. 13 will be described in detail with reference to FIG. 14 (a).

The control circuit is supplied with the low DC voltage Vcc obtained from the capacitor C ₁₀ as the control power supply via the terminal “f” as the control power supply voltage.

The timer circuits (IC ₅ , IC ₆ ) and oscillation circuits (IC ₇ ) are operated by this control voltage (Vcc). The timer circuit (IC ₅ ) consists of a general-purpose direct circuit (“NE555” from SIGNETIX of the United States). This triggers when the trigger terminal (pin 2) is low (1/3) Vcc, the output terminal (pin 3) is at the “H” level, and the discharge terminal (pin 7) is high impedance. The threshold level terminal (No. 6 pin) is at (2/3) Vcc, the output terminal is at the “L” level, and the discharge terminal (No. 7 pin) is also at the “L” level.

The control voltage Vcc is applied to the power supply terminal (pin 8) and the ground terminal (pin 1).

The reset terminal (pin 4) is connected to the power supply terminal (pin 8), and the frequency control terminal (pin 5) is connected to the ground terminal (pin 1) via the decoupling capacitor (C ₂₈ ).

In addition, the control voltage Vcc is applied to a series circuit composed of a resistor R ₃₇ and a capacitor C ₂₇ for the time constant of the timer circuit IC ₅ .

The threshold value terminal (No. 6 pin) of the timer circuit (IC ₅ ) is connected to the connection point of the resistor (R ₃₇ ) and the capacitor (C ₂₇ ), and the discharge terminal (No. 7 pin) is connected via the resistor (R ₃₈ ). .

Thus, the timer circuit IC ₅ operates as a monostable multivibrator.

In the circuit of FIG. 13, as the commercial AC power supply V _S is connected to raise the control voltage Vcc applied to the terminal “f”, the capacitor C ₂₆ is charged through the resistor R ₃₅ , the base of the transistor (Q ₁₀₎ - is the emitter current flows for a short period, the transistor (Q ₁₀₎ the potential of the connection point between the turns on at the moment, the resistance (R ₃₆₎ and a transistor (Q ₁₀₎ is a momentary drop in Thus, the trigger terminal (terminal 2) of the timer circuit IC ₅ is at the “L” level and the monostable multivibrator IC ₅ is triggered.

Therefore, the output terminal (pin 3) of the monostable multivibrator (IC ₅ ) has a threshold voltage value (Vth =) where the threshold terminal (pin 6) is set according to the time constant of the capacitor (C ₂₇ ) and the resistor (R ₃₇ ). Hold the “H” level until (2/3) Vcc) is reached.

In addition, as the voltage of the capacitor C ₂₇ reaches the threshold voltage value Vth, the output terminal (pin 3) becomes the "L" level, and the discharge terminal (pin 7) changes to the "L" level so that the capacitor The voltage that was charged in C ₂₇ is discharged through resistor R ₃₈ .

In this case, the output terminal (pin 3) goes to the “H” level for about 1 second depending on the time constant of the capacitor C ₂₇ and the resistor R ₃₇ .

When the output terminal (pin 3) of the timer circuit IC ₅ is at the “H” level, the base current is applied to the transistor Q ₁₁ through the resistors R ₃₉ and R ₄₀ to turn on the transistor.

In addition, the base current is applied to the base of the transistor Q ₁₄ through the resistors R ₃₉ and R ₄₅ to turn on the transistor. When the output terminal (pin 3) of the timer circuit IC ₅ is at the "L" level, the transistors Q ₁₁ and Q ₁₄ are both turned off.

In addition, the timer IC ₆ is composed of an integrated circuit such as SIGNTIX “NE555”. The control voltage Vcc is applied through the power supply terminal (pin 8) and the ground terminal (pin 1), and the reset terminal (pin 4). Is connected to the power supply terminal (pin 8), the frequency control terminal (pin 5) is connected to the ground terminal (pin 1) through the decoupling capacitor (C ₃₃ ).

The control voltage Vcc is applied to the series circuit composed of the resistor R ₄₈ and the capacitor C ₃₂ forming the time constant circuit of the timer circuit IC ₆ .

Since the threshold value terminal (No. 6 pin) and the discharge terminal (No. 7 pin) are connected to the connection point of the resistor (R ₄₈ ) and the capacitor (C ₃₂ ), the timer circuit (IC ₆ ) will operate as a monostable multivibrator.

As the timer operation of the timer circuit IC ₅ terminates the above operation and the output terminal (pin 3) changes from the "H" level to the "L" level, the transistor Q ₁₄ is turned from the on state to the off state. therefore, the collector potential of the transistor is increased, a capacitor (C ₃₄₎ is charged via a resistor (R _46), the base of the transistor (Q ₁₅₎ - is the emitter current flows for a short period of the transistor (Q ₁₅₎ is momentarily Comes on.

For this reason, the potential at the connection point of the resistor R ₄₇ and the transistor Q ₁₅ drops instantaneously, and the trigger terminal (pin 2) of the timer circuit IC ₆ is at the "L" level. Triggered as a multivibrator.

After that, the output terminal (pin 3) reaches the predetermined threshold voltage (Vth = (2/3) Vcc) according to the time constant of the capacitor terminal (pin 6) of the capacitor C ₃₂ and the resistor R ₄₈ . Keep the "H" level until When the voltage of the capacitor C ₃₂ reaches the threshold holder voltage Vth, the output terminal (pin 3) becomes the "L" level, and the charged voltage of the capacitor C ₃₂ is discharged.

In this case, the output terminal (pin 3) of the timer circuit IC ₆ becomes the “H” level for several hundred μsec depending on the time constant of the capacitor C ₃₂ and the resistor R ₄₈ .

If the output terminal (pin 3) of the timer circuit IC ₆ is at the “H” level, current is applied to the base and emitter of the transistor Q ₁₆ via the resistors R ₄₉ and R ₅₁ to turn on the transistor. The connection point potential of the resistors R ₅₀ and R ₅₃ drops to turn off the transistor Q ₁₇ .

When the output terminal of the timer circuit IC ₆ is at the "L" level, the transistor Q ₁₆ is turned off, and the connection point potential between the resistors R ₅₀ and R ₅₃ is increased to turn on the transistor Q ₁₇ .

For the oscillation circuit IC ₇ a control IC (for example "μPC494" of NEC Corporation) for use as the same switching regulator as the embodiment shown in FIGS. 1 to 4 may be used.

In this case, the dead-off time divides the level of the reference voltage Vref by the resistor R ₅₆ and the variable resistor VR ₁₀ , and divides the divided voltage into the dead-off time control terminal of the oscillation circuit IC ₇ . It can be set by inputting to (pin 4).

The non-inverting input terminals (pins 1 and 6) and the inverting input terminals (pins 2 and 15) of the oscillation circuit (IC ₇ ) are input terminals for the pulse width control comparator, and when the pulse width control is not performed, the oscillating circuit The non-inverting input terminal is connected to ground and the inverting input terminal is operated to connect the reference voltage (Vref) level.

The feedback terminal (pin 3) is open when not used as the feedback terminal for pulse width control.

Here, the output control terminal (pin 13) receives a push-pull operation with respect to the level of the reference voltage (Vref) at the reference voltage output terminal (pin 14), the control signal of the MOS transistors (Q ₂ , Q ₃ ) Grounds the open emitter terminals (pins 9 and 10) and pulls the oscillation outputs obtained from the respective open collector terminals (pins 8 and 11) and the pull-up resistors (R ₄₂ , R ₄₃ ) and NOT circuits (G6, G9). It is obtained by inverting and waveform shaping, respectively.

The output of the NOT circuit G6 is provided to the gate of the MOS transistor Q ₃ as the second control signal of the main circuit through the terminal “j”, and the output of the NOT circuit G9 is a resistor R ₄₄ and a transistor. (Q ₁₂ , Q ₁₃ ), MOS transistors via terminals “h” and “i” as the first control signals of the main circuit, insulated by a drive circuit consisting of a coupling capacitor (C ₃₁ ) and a pulse transformer (T ₁₀ ). Provided to the gate-source of (Q ₂ ).

As shown in FIG. 14, the resonant input terminal of the reference voltage comparator IC ₈ divided by the resistors R ₅₄ and R ₅₅ from the control voltage Vcc is applied to the resonant current detected in the main circuit. The corresponding voltage Vch is applied to the non-inverting input terminal.

The output of the comparator IC ₈ is inverted in the NOT circuit G10 and supplied to the gate of the MOS transistor Q ₇ as the third control signal of the main circuit through the terminal “k”. As the discharge lamp 10 is dimmed at a low luminous flux, the voltage Vch is lowered and the output of the comparator IC ₈ is maintained at the "L" level, so that the NOT circuit G10 outputs the "H" level. Is generated to turn on the MOS transistor Q ₇ .

On the other hand, when the discharge lamp 10 is not in a low luminous flux state, the MOS transistor Q ₇ is turned off.

The voltage of the output terminal (No. 3 pin) of the timer circuit IC ₆ is waveform-formed through the buffer circuit composed of the NOT circuits G7 and G8, and the MOS transistor Q through the terminal “l” as the fourth control signal of the main circuit. ₈ ) is supplied to the gate.

Claim 14 (a) and 14 (b) degrees when the operation described with reference to the 15 degrees, a timer circuit (IC ₅₎ is a transistor (Q ₁₁₎ to be activated by the commercial AC power supply voltage (V _S) about a second During this start, the current IRT is limited only by the resistor R ₄₁ and the oscillation frequency f ₁₁ of the oscillating circuit IC ₇ is increased. The oscillation frequency f ₁₁ at this time is set to be much higher than the resonance frequency in the no-load state of the load circuit, and since the voltage applied through the discharge lamp is low, the discharge lamp 10 is not started and preheated. The current is supplied to the filament for about 1 second.

When the timer operation of the timer circuit IC ₅ ends, the transistor Q ₁₁ is turned off, and then the transistor C ₁₇ remains off for several hundred μs, which causes the current IRT to become a resistor ( R ₄₁ ) and the variable resistor VR ₁₁ , and the oscillation circuit IC ₇ oscillates at a low oscillation frequency f ₁₂ .

The capacitor C ₂₉ is connected in parallel with the variable resistor VR ₁₁ to smooth the oscillation frequency.

At this time, since the oscillation frequency f ₁₂ is set to be close to the resonant frequency in the no-load state of the load circuit, the discharge lamp proceeds to discharge with a very high voltage applied to the discharge lamp 10.

As the timer operation of the timer circuit IC ₆ is terminated, the transistor Q ₁₇ is turned on and the ground of the slider of the variable resistor VR ₁₁ is connected, so that the current IRT is a resistor R ₄₁ . And limited by a part of the variable resistor VR ₁₁ , and the oscillation circuit IC ₇ is oscillated at an oscillation frequency f _{13 in} which f1 < f13 < f12.

By operating the slider of the variable resistor VR ₁₁ , the oscillation frequency f ₁₃ can be made high or low.

When the oscillation frequency f ₁₃ is increased, the resonance operation is weakened to reduce the resonance current, and the luminous flux generated by the discharge lamp 10 is lowered.

In this way, dimming of the discharge lamp 10 can be realized.

In the main circuit, the resonant current IT ₅ flowing in the inductor IT ₅ is detected as the voltage Vch, and when the detected voltage value is below the predetermined level, the comparator IC ₈ generates an “L” level output. , NOT circuit G10 generates an “H” level output to turn on MOS transistor Q ₇ .

Therefore, the DC power is superimposed so as to be supplied to the discharge lamp 10 so that flicker-off does not occur in a low luminous flux state, so that the lamp can be stably emitted.

On the other hand, when the discharge lamp 10 is not in a low luminous flux state, the flow of DC power is blocked, so that problems such as cataphoresis of the lamp and shortening of the life of the lamp can be prevented.

In addition, the MOS transistor Q ₈ connected in parallel to the MOS transistor Q ₇ for DC power control is turned on for several hundred microseconds at the start of the discharge lamp 10, that is, the output terminal of the timer circuit IC ₆ (pin 3). ) Is maintained at the “H” level.

Therefore, the voltage passing through the MOS transistor Q ₇ becomes zero during that time, so that the high voltage for starting the discharge lamp 10 is applied to the lamp, so that a predetermined stress or the like can be prevented from being applied due to the overvoltage application. There is a number.

In the apparatus of FIG. 14, the apparatus is designed to detect the resonant current as a means for detecting the discharge lamp 10, so that an apparatus for detecting the lamp current or the optical output may be arranged. The dimming level setting signal may be used to control the MOS transistors Q ₇ and Q ₈ .

FIG. 16 shows another form of the device of FIG. 13, in which the DC current control MOS transistor Q ₇ , the overcurrent protection MOS transistor Q ₇ and the overcurrent protection MOS transistor Q _{8 of} FIG. Is commonly achieved by the transistor Q ₇ .

17 shows a detail of the control circuit.

More specifically, the outputs of the NOT circuits G8 and G11 are input to the OR circuit G11, and the outputs of the OR circuit G11 are supplied to the gate of the MOS transistor Q ₇ through the terminal " l " The 14-degree MOS transistor Q ₈ may be omitted.

That is, the DC power supply control MOS transistor Q ₇ remains on not only at low light flux but also at the start of the discharge lamp 10, and the other MOS transistor Q ₈ does not need to be separately provided for overvoltage prevention. In this case, the other structures and functions are substantially the same as those in FIG. 16 and 17, MOS transistors are used for DC power supply control or for overvoltage prevention, but switching elements such as bipolar transistors or relays may be used if necessary.

18 illustrates another form of the FIG. 13 device.

In this case, the zener diode ZD ₁₀ is connected in parallel to the MOS transistor Q ₇ for DC power supply and is used as a switching device for preventing high voltage. The zener diode ZD ₁₀ is a drain-source of the MOS transistor Q ₇ . It has a zener voltage that is set lower than the breakdown voltage passing through and higher than the voltage applied during illumination.

Therefore, the zener diode ZD ₁₀ becomes a conductor only during the initial driving of the discharge lamp 10 so that a predetermined voltage is not applied past the MOS transistor Q ₇ . In addition, since a passive high voltage prevention element is used, the control circuit is simpler and more economical than an active element such as a MOS transistor.

Instead of the zener diode ZD ₁₀ , a surge absorber such as ZNR or a passive element such as an avalanche diode may be used.

Other structures and functions of this form are substantially the same as in FIG.

According to another feature of the present invention, there is provided a discharge lamp lighting apparatus for immediately stopping the superimposed supply of DC power when the discharge lamp 10 is turned off.

Referring to FIG. 19, which is another form of the FIG. 1 apparatus according to the present invention, the control voltage Vcc of the condenser C ₁₀ , which is the operating power source of the control means 72, is determined in the light flux region where the discharge lamp 10 is low. When the power switch SW _AC is opened in the controlled light control state, the control unit 72 outputs a control signal until the voltage reaches a level below the minimum voltage V _MIN . The circuitry of the control means 72 will continue to operate as shown in FIG. 20A.

Although the voltage of the capacitor C ₂₁ , which is the main power supply of the inverter, is also lowered, the discharge lamp 10 which maintains its illumination in the low luminous flux region consumes very little power, and thus the capacitor C ₂₁ as shown in FIG. ), The voltage Vc ₂₁ gradually decreases.

Since the DC power for maintaining the illumination is supplied to the lamp from the capacitor C ₂₁ through the resistor R ₅₇ , the illumination of the discharge lamp 10 is maintained even when the power switch SW _AC is opened. If the discharge lamp 10 maintains the illumination state until the voltage Vc ₂₁ of the condenser C ₂₁ becomes equal to or less than the predetermined voltage V ₀ , the control means 72 stops at time t ₁ . The operation of causes the discharge lamp 10 to be illuminated until time t ₂ as shown in FIG. 20B.

On the other hand, when the power switch SWAC is opened in the fully lit state of the discharge lamp 10, the power consumption in the inverter is sufficiently large to rapidly lower the voltage Vc ₂₁ of the capacitor C ₂₁ as shown in FIG. 20C. In some cases, as shown in FIG. 20d, the control means 72 stops its operation, and the voltage Vc ₂₁ of the capacitor C ₂₁ is kept higher than the predetermined voltage V ₀ at the time t ₁ . The oscillation of the inverter is stopped, the voltage Vc ₂₁ is then gradually lowered, and the discharge lamp 10 will be illuminated until a time t ₃ at which the voltage Vc ₂₁ is below the predetermined level V0. .

Therefore, as shown in FIG. 21, the discharge lamp extinction signal S11 is provided to the DC power supply means 78 to cut off the DC power supply immediately after the discharge lamp 10 is extinguished.

In other more detail, as shown in claim 22 also, the MOS transistor (Q ₁₇₎ is a resistance (R ₅₇₎ and since the series connection of the MOS transistor (Q ₁₇₎ is turned on by providing a signal (P) to the gate of the transistor Will be turned off and the DC power supply path will be destroyed.

In the embodiment of FIGS. 21 and 22, the other components and functions are substantially the same as those of FIGS.

FIG. 23 shows a typical example of the control means for providing the control signal to the circuit of FIG. 22. In this example, a drive circuit for the MOS transistors Q ₂ and Q ₃ of the main circuit and a drive signal are supplied. An oscillation circuit IC ₉ and a voltage detection circuit 77 for controlling the turn-off of the MOS transistor Q ₇ when the discharge lamp is turned off are provided.

As the operating power source for these circuits, the control power supply voltage Vcc obtained from the condenser C _{10 of the} control power supply unit is supplied to the circuit.

The drive circuit for the MOS transistor Q ₂ includes a pulse transformer T ₁₁ , resistors R ₆₃ , R ₆₄ and diodes D2 ₁ , D2 ₃ .

A control voltage Vcc is provided to the center tap of the primary winding of the pulse transformer T ₁₁ , one side of the primary winding is then grounded via the above-described driving MOS transistor Q ₁₈ , and the other of the primary winding is provided. The side is grounded via a diode D2 ₁ .

One side of the secondary winding of the pulse transformer T ₁₁ is connected to the source terminal of the MOS transistor Q ₂ of the main circuit via the terminal “n”, and the other side thereof is the normal bias resistor R ₆₃ , the reverse bias. It is connected to the gate of the MOS transistor Q ₂ via the diode D ₂₃ and the terminal “m”.

Transistor R ₆₄ is connected in parallel to the gate-source of MOS transistor Q ₂ .

As the driving MOS transistor Q ₁₈ is turned on and one side of the pulse transformer T ₁₁ is grounded, the primary winding is controlled by the control voltage Vcc applied to the center tap of the primary winding of the transformer T ₁₁ . Current flows in the secondary winding, and the current induced in the secondary winding flows through a series circuit composed of resistors R ₆₃ and R ₆₄ connected to the secondary winding, and voltage is generated across the resistor R ₆₄ . The voltage turns on the transistor past the gate-source of the MOS transistor Q ₂ .

As the driving MOS transistor Q ₁₈ is turned off and the current flowing through the primary winding of the pulse transformer T ₁₁ is cut off, a regenerative current flows to the primary winding through the diode D ₂₁ . .

At this time, the counter electromotive force is generated in the secondary winding of the pulse transformer T ₁₁ , and the reverse voltage bias between the gate and the source of the MOS transistor Q ₂ flows to the resistor R ₆₄ through the diode D ₂₃ . The charge charged in the capacitor between the gate and the source is quickly discharged to turn off the MOS transistor Q ₂ quickly.

The driving circuit for the MOS transistor Q ₃ has the same structure, and the same operation is performed.

The driving circuit for the MOS transistor is composed of a pulse transformer (T ₁₂ ), a resistor (R ₆₅ , R ₆₆ ) and a diode (D ₂₂ , D ₂₄ ), which is a pulse transformer (T ₁₁ ), a resistor (R ₆₃ , R _64). ) And diodes D ₂₁ and D ₂₃ , respectively, and the same operation is performed.

For the oscillation circuit IC ₉ , a control IC (“μPC474C”) for use with the switching regulator may be used, and the same function as in the above-described embodiment is obtained.

In this embodiment, the push-pull operation is performed by polling the output control terminal (pin 13) of the oscillating circuit IC ₉ to the reference voltage Vref, and the open emitter terminals (pins 9 and 10) are grounded. The oscillation output obtained at the open collector terminals (pins 8 and 11) produces an input signal for the driving MOS transistors Q ₁₈ and Q ₁₉ .

That is, if a short circuit is formed between the first open collector terminal (pin 8) and the open emitter terminal (pin 9), the gate of the MOS transistor Q ₁₉ is at the "L" level, but is open between these terminals. Is obtained, the gate of the MOS transistor Q ₁₉ will be at the "H" level by the pull-up resistor R ₆₂ .

Similarly, the gate of the MOS transistor Q ₁₈ is at the “L” level when the second open collector terminal (pin 11) and the open emitter terminal (pin 10) are shorted, and “ H ”level.

MOS transistors (Q _18, Q ₁₉₎ is a MOS transistor (Q _2, Q ₃₎ MOS transistor (Q _2, Q ₃₎ the pulse transformer of the driver circuit for forming a drive circuit to drive the (T _11, T ₁₂₎ Are connected to one end of each.

The oscillation frequency of the oscillation circuit IC ₉ is determined by the time constants of the capacitor C ₃₆ , the fixed resistor R ₅₈ , and the variable resistor VR ₁₂ .

As the value of the variable resistor VR ₁₂ is appropriately adjusted, the oscillation frequency of the oscillation circuit IC ₉ can be controlled. The dead-off time of the oscillation output is determined by the divided voltage level of the reference voltage Vref by the resistors R ₅₉ and R ₆₀ .

In the other hand, the voltage detecting circuit 77, a capacitor (C ₁₀₎ a control voltage (Vcc) obtained is divided by a resistor (R _67, R _68), the connection point between the resistors (R _67, R ₆₈₎ ( The voltage obtained in q) is applied to the resistor R ₇₀ through the zener diode ZD ₂ .

The voltage generated across the resistor R ₇₀ is applied to the base-emitter of the transistor Q ₂₀ , the collector of which is connected to the control power supply Vcc through the resistor R ₆₉ , and the resistor R ₇₂ . Is connected to the base of the PNP transistor Q ₂₁ .

The control voltage Vcc is provided to the emitter of the PNP transistor Q ₂₁ and its collector is grounded through the resistor R ₇₁ .

The series circuit of the resistors R ₇₃ and R ₇₄ is connected in parallel to the resistor R ₇₁ , and the voltage obtained at the connection point P between these resistors R ₇₃ and R ₇₄ is the MOS transistor Q ₁₇ of FIG. 22. Is used as the gate drive low pressure.

24A to 24C show an operation waveform of the voltage detection circuit 77 of FIG. 23, in which the power switch SWAC is closed before the timing t0 and determined by the zener voltage of the zener diode ZD ₁ . The predetermined DC voltage is generated at the capacitor C ₁₀ .

The voltage held at the connection point q is obtained by dividing the DC constant voltage by the resistors R ₆₇ and R ₆₈ , which is set higher than the zener voltage of the zener diode ZD ₂ .

Therefore, the zener diode ZD ₂ conducts before timing t0 to generate a voltage through resistor R ₇₀ , so transistor Q ₂₀ is turned on and the collector at point r of transistor Q ₂₀ . The voltage Vr will be at the "L" level as shown in FIG. 24B compared to the control voltage Vcc shown in FIG. 24A.

Further, the connection point between, so the PNP transistor, the current flow through the resistance (R ₇₂₎ and a transistor (Q ₂₀₎ to the base of (Q ₂₁₎ a PNP transistor (Q ₂₁₎ is turned on, a resistor _{(R 73, R 74) (} P The potential at () is the voltage determined according to the control voltage (Vcc) as shown in FIG. 24C, and since the direct current flows to the discharge lamp 10 through the resistor R ₅₇ , the MOS transistor Q ₁₇ . Is turned on.

When the power switch SWAC is opened at the timing t0, the control voltage Vcc is lowered as shown in FIG. 24A, and the voltage at the connection point q is at the timing t4, and the Zener diode ZD ₂ Since the zener diode ZD ₂ is in a non-conductive state, the transistor Q ₂₀ is turned off, and its collector voltage Vr is controlled as shown in FIG. 24B. Will match (Vcc).

Therefore, the PNP transistor Q ₂₁ is turned off, and the potential of the connection point P between the resistors Q ₇₃ and Q ₇₄ becomes the "L" level as shown in FIG. 24C, and the MOS transistor Q ₁₈ . Is turned off. Accordingly, the DC current flowing to the discharge lamp 10 through the resistor R ₅₇ is cut off. As the operation of the oscillation circuit IC ₉ is stopped, inverter oscillation is stopped, and the discharge of the discharge lamp 10 is stopped. At this time, the DC current for maintaining its illumination does not flow to the discharge lamp 10 and the glow afterwards is cut off.

In this embodiment, the voltage drop of the control voltage Vcc is detected to obtain an extinguishing signal for the discharge lamp, which is effective for detecting the voltage drop in the capacitor C ₂₁ forming the inverter input power source. The extinguishing signal may also be obtained by another switch interlocked with the power switch SWAC.

25 shows another embodiment, in which the dimming control means 82 can control the light output of the discharge lamp 10 from 100% illumination to 0% illumination, i.e., off, according to the dimming signal VDM. To be dimmed. In this case, fade-out is obtained by cutting off the DC power supply for maintaining the illumination of the discharge lamp.

As shown in FIG. 26, the dimming rate is decreased when the dimming signal VDM is reduced, so that the light output is reduced, and when the dimming signal VDM reaches a predetermined time, it is necessary to maintain illumination of the discharge lamp. DC power is cut off, lighting rate is zero and the light output is lost.

FIG. 27 shows a fade-out control circuit for use in connection with FIGS. 22 and 23. In FIG. 27, the terminals "p" and "s" are terminals "p" and "s" of FIG. Respectively.

Here, the dimming signal VDM is input to the inverting input terminal of the operational amplifier IC ₁₀ through the input resistor R ₇₅ and the resistors R ₇₆ and R _{77 to} the non-inverting input terminal of the operational amplifier IC ₁₀ . The reference voltage obtained by dividing the control voltage (Vcc) is applied to the output terminal thereof. The output terminal thereof is connected to the inverting input terminal of the amplifier IC ₁₀ through the feedback resistor R ₇₈ and simultaneously through the input resistor R ₈₁ . The reference voltage obtained by dividing the control voltage Vcc by the resistors R ₇₉ and R ₈₀ is applied to the non-inverting input terminal of the other operational amplifier IC ₁₁ , and the output terminal of the amplifier IC _{11 is} connected to the feedback resistor R. ₈₂ ) is connected to its inverting input terminal via the terminal “S” to the resistance terminal (No. 6 pin) of the oscillating circuit IC ₉ of FIG.

Therefore, the dimming signal VDM is provided to the resistor terminal (No. 6 pin) of the oscillation circuit IC9 via the operational amplifiers IC ₁₀ and IC ₁₁ to execute dimming control. In this case, as the dimming signal VDM increases, the light output of the discharge lamp 10 increases.

Further, a control voltage (Vcc) by a light control signal (VDM) is supplied to the inverting input terminal of the comparator (IC12) to the resistance (R ₈₃₎ parameters, in its non-inverting input terminal resistance (R _84, R ₈₅₎ The divided reference voltage is applied.

To the An output terminal of the comparator (IC12) resistance (R ₈₆₎ bar which is connected to the base of the parameters of transistors (Q _22), a transistor (Q ₂₂₎ is 23 degrees, the resistance through the terminal "p" (R ₇₄₎ Are connected in parallel.

As shown in FIG. 26, when the dimming signal VDM is larger than the predetermined level (R ₈₄ / (R ₈₄ + R ₈₅ )) Vcc, the output terminal of the comparator IC12 is at the "L" level and the transistor Turn off (Q ₂₂ ).

When the dimming signal VDM is smaller than the predetermined level, the output terminal of the comparator IC12 is at the “H” level to turn on the transistor Q ₂₂ .

Accordingly, since the MOS transistor Q _{17 of} FIG. 22 is strongly turned off and the DC voltage applied to the discharge lamp 10 through the resistor R ₅₇ is blocked for discharge, the discharge lamp 10 is discharged. As shown in FIG. 26, the discharge cannot be maintained in the low luminous flux dimming area, and the discharge lamp is completely turned off.

Therefore, in this embodiment, the extinguishing of the discharge lamp can be carried out by means of applying excessive stress to circuit elements such as the interruption of input power, or without stopping the inverter oscillation, and also reducing the inverter oscillation output and maintaining the discharge This can be done by cutting off the DC power supply.

On the other hand, inverter oscillation is continued to minimize the stress applied to the circuit element.

According to still another feature of the present invention, there is provided a dimming discharge lamp lighting apparatus in which an abnormal discharge state such as low electron radiation generated in a filament can be stably detected so that excessive stress is not applied to the circuit element.

That is, when the filament f ₂ of the discharge lamp 10 of FIG. ₁ is in a low electron emission state, this state can be detected by detecting excessive current flowing through the MOS transistors Q ₂ and Q ₃ .

However, when the other filament f ₁ is in a low radiating state, even if the inverter itself is in an abnormal discharge state, the inverter does not detect an abnormal state, and normal operation is performed to generate excessive stress that is added to the circuit element. Lose.

Referring to FIG. 28, the DC current detecting means 99 is disposed between the discharge lamp 10 and the DC power supply means 13 of FIG. 1, and the DC power supply means is indicated by the reference numeral 93. As shown in FIG. .

Therefore, more than normal lighting, the detected DC current by the current detecting means 99 will be provided to the dimming control means as an abnormal discharge signal.

In this case, the high frequency power supply supplied from the high frequency power supply unit 91 to the discharge lamp 10 in response to the detection of the abnormal discharge may be stopped, or the manufacturing name control may be performed for the discharge lamp in response to the detection of the lamp being extinguished.

The dimming control means 92 has the same structure as that of FIG. 1 capable of dimming the discharge lamp from the arc discharge area to the glow discharge area.

Other structures and their functions are the same as in the above-described embodiment.

29A and 29B, the high frequency power is supplied from the high frequency power supply 101 to the discharge lamp 10, and the DC power is discharged from the DC power supply means 103 when superimposed on the high frequency power. 10), and when the filament f ₂ at the cathode of the DC power supply is in a low radiation state, the lamp current flowing through the discharge lamp 10 flows only from the filament f ₂ to the filament f ₁ . do.

This is because there is no radiation from the filament (f ₂₎ electrons are hardly emitted from the filament (f ₂₎ to electrons are emitted only from the filament (f _2).

Referring to the equivalent circuit of FIG. 29A shown in FIG. 29B, a high frequency power source is applied to the discharge lamp 10 through the discharge lamp 10 through the filaments f ₁ and f ₂ having the resistors RB and RA. The discharge lamp 10 itself includes a diode D ₀ and a lamp impedance having a half-wave rectification function assuming that a unidirectional lamp current flows in the occurrence of a low radiation state in the filament f ₂ .

When a low radiation condition occurs in the filament f ₂ , current flows from the filament f ₂ to the filament as indicated in the direction of the virtual diode D ₀ , so that an overcurrent is applied to the switching element of the high frequency power supply 101. By flowing, the preheating value can be increased or a phenomenon in which a large stress is applied to the circuit element can be easily detected.

If a low radiation condition occurs at the filament f ₁ , the direction of the virtual diode D ₀ is reversed from the 29th degree, so the lamp current flows only from the filament f ₁ to the filament f ₂ , and the DC power supply Current may be supplied from the means 103.

The stress added to the circuit elements of the high frequency power supply 101 is so small that the conventional low radiation detector cannot detect such a situation.

In this embodiment, the lamp current is detected from the DC power supply 103 at the time of low radiation occurring in the filament f ₁ , and the steam of the amount of DC power supplied from the means 103 is achieved to achieve the purpose. .

Referring to the embodiment of FIG. 28 referred to as an embodiment of the circuit, the current detecting resistors R ₈₇ and R ₈₈ are connected in series to an inductor CH ₃ which forms a DC current supply path towards the discharge lamp 10. The magnitude of the DC current supplied to the discharge lamp 10 is the point between these resistors ( Is detected as a potential in.

FIG. 31 is an example of a control circuit for supplying a control signal to FIG. 30, in which all the structures for DC current detection and their functions are substantially the same as in the above embodiment.

In the DC current detecting means 99, the point " Voltage at V ) Is averaged by the capacitor (C ₄₀ ) and applied to the non-inverting input terminal of the comparator (IC ₁₃ ) via the input resistor (R ₈₉ ), and the control voltage (Vcc) is applied by the resistors (R ₉₀ , R ₉₁ ). The divided reference voltage Vk is applied to the other inverting input terminal of the comparator IC ₁₃ .

As long as the discharge lamp 10 emits light normally, Voltage at V ) Is lower than the reference voltage (Vk) to maintain the output of the comparator (IC ₁₃ ) to the "L" level.

Whenever a low radiation condition occurs in the filament f _{1 of the} discharge lamp 10, the current flowing in the discharge lamp 10 is increased and the point “ Voltage at V ) Increases above the reference voltage (Vk) and the output of the comparator changes to the “H” level.

The output of the DC current detecting means 99 is provided to the oscillation limiting means 100 composed of the transistor Q ₂₃ and the resistors R ₉₂ and R _93. The collector of the transistor Q ₂₃ has an oscillating circuit ( Is connected to the connection point between the resistor R ₅₈ and the variable resistor VR ₁₂ for setting the time constant of the IC ₉ ), its emitter is grounded, and its base is connected to the DC current detecting means (R ₉₂ ) by the resistor R ₉₂ . It is connected to the output terminal of 99) and grounded via a resistor (R ₉₃ ).

As the output of the DC current detecting means 99 goes to the "H" level, the base current flows through the transistor Q ₂₃ , conducts through the collector and the emitter, and the variable resistor VR ₁₂ is shorted between both ends thereof. Therefore, the frequency of the oscillation circuit IC ₉ is increased, the oscillation output of the inverter is limited, and the stress applied to the circuit elements of the inverter is reduced.

FIG. 32 shows another operating characteristic of the device of FIG. 28, wherein the filament f ₁ as well as the low radiation state at the filament f ₂ can be detected by providing the resonance voltage detecting means 105. In this means, the series circuit of the voltage dividing resistors R ₉₄ and R ₉₅ is connected in parallel to the capacitor C ₇ .

Resistance resonance voltage of the high-frequency divided by (R _94, R ₉₅₎ is a half wave current in a diode (D _25), condenser bar, this voltage is smoothed in a (C ₄₁₎ is converted to a DC voltage input resistance (R ₉₆ Is applied to the non-inverting input terminal of the comparator IC14, and the reference voltage obtained by dividing the control voltage Vcc by the resistors R ₉₇ and R ₉₈ is applied to the other inverting input terminal of the comparator IC ₁₄ . .

During normal lighting of the discharge lamp 10, the DC voltage of the capacitor C ₄₁ is lower than the reference voltage of the resistor R ₉₈ , and the output of the comparator IC ₁₄ is at the "L" level.

When a low radiation state is generated in the filament f ₂ , only one direction current flows through the resonant circuit and the discharge lamp 10 including the inductor LCH ₁ and the capacitor C ₇ , and the capacitor C ₇ is generated. The resonance voltage is raised to a very high voltage.

For this reason, the voltage obtained at the capacitor C ₇ is higher than the reference voltage at the resistor R ₉₈ , and the output of the comparator is at the “H” level.

The output of this comparator is input to the base of transistor Q ₂₃ via resistor R ₉₉ and diode D ₂₆ .

As above, the output of the comparator IC ₁₃ is input to the base of the transistor Q ₂₃ through the resistor R ₉₂ and the diode D ₂₇ .

The diodes D ₂₆ and D ₂₇ form an OR circuit, so that when the output of the resonant voltage detecting means 105 becomes the "H" level, or the output of the DC current detecting means 99 becomes the "H" level, oscillation is performed. Transistor Q _{23 in} limiting means 100 is turned on.

Therefore, a low radiation state generated in the filament f ₁ or filament f ₂ can be detected, and the oscillation output of the inverter means is limited at the time of occurrence of the low radiation state.

33 and 34 show another operating characteristic diagram of the device of FIG. 28, in which the DC current supplied to the discharge lamp 10 is not detected, and the start signal is applied to the DC current detection means for restart control. From 119 to dimming control means 112.

More specifically, as shown in FIG. 34, the point “ Voltage at V ) Is applied to the non-inverting input terminal of the comparator IC ₁₅ via the input resistor R ₁₀₀ , and the reference voltage of the control voltage Vcc by the resistors R ₁₀₁ and R ₁₀₂ is equal to that of the comparator IC ₁₅ . These voltages are applied to the inverting input terminals and compared.

The output of the comparator IC ₁₅ is input to the restart control circuit 112 via the resistor R _103. The reference voltage applied to the inverting input terminal of the comparator IC ₁₅ is set for normal illumination of the discharge lamp. “ Voltage at V Since the lamp is set to a lower value, the normal lighting of the lamp will bring the output of the comparator (IC ₁₅ ) to the "H" level, but the lamp off will make the output of the comparator to the "L" level.

Therefore, when the output of the comparator IC ₁₅ is at the "L" level, the restart control circuit 112 provides a predetermined voltage to the oscillation circuit IC to bring the switching frequency of the inverter means closer to the resonance frequency of the load circuit, and the discharge lamp. Sufficient voltage is generated through the idle capacitor C to start the discharge lamp 10, so that the discharge lamp is restarted.

In the above embodiment, although the low intensity mercury arc discharge lamp has been described assuming that it is dimmed, the present invention need not be limited to dimming the discharge lamp.

It is important that the lighting of the low intensity mercury arc discharge lamp of the discharge lamp can be realized efficiently and stably when the lighting is normally difficult.

Claims (15)

1 ~ 36 (Deleted) (Newly established) low intensity mercury arc discharge lamp, high frequency power supply unit for providing high frequency power to the discharge lamp, means for controlling the high frequency power source provided to the discharge lamp, and the discharge lamp at a level capable of maintaining the discharge during low light illumination A DC power supply means for supplying a DC power supply and including overlapping stop means for stopping the superposition of the DC power when the relative illumination rate of the lamp with respect to illumination at rated current is equal to or greater than a predetermined level, wherein the DC power supply Discharge lamp lighting apparatus, characterized in that superimposed on the high frequency power provided to the lamp from the high frequency power supply unit (Newly formed) The method according to claim 37, wherein the overlapping stop means is composed of a plurality of switching circuits connected in parallel with each other with respect to the discharge lamp, and the relative illumination rate above the predetermined level is set differently for each of the switching circuits. Device characterized in that (Newly formed) The apparatus according to claim 37, wherein the superposition stop means includes switching means at a DC power supply that stops superimposition of the DC power supplies when the relative illumination rate exceeds a predetermined level. (New) The apparatus according to claim 39, further comprising an overcurrent preventing switching means connected in parallel with the DC power control switching means operating at startup of the discharge lamp. (New) The apparatus according to claim 40, wherein the DC power supply control switching means and the overcurrent prevention switching means are formed by a common switching means. (New) The apparatus according to claim 37, further comprising means for stopping superimposition of the DC power supply in response to a signal for turning off the discharge lamp. (New) The apparatus according to claim 37, further comprising abnormal state detecting means for detecting an abnormal state of said discharge lamp by detecting a DC power supplied from said DC power supply means to said discharge lamp. (New) The apparatus according to claim 43, further comprising means for stopping the high frequency power supply of the discharge lamp from the high frequency power supply unit when the abnormal state detecting means detects an abnormal state. (New) The apparatus according to claim 37, further comprising means for detecting a non-illumination state of the discharge lamp by detecting a DC power level supplied from the DC power supply unit to the discharge lamp. (New) The apparatus according to claim 45, wherein the non-illumination state detection means is composed of re-illumination means for executing re-illumination control when detecting the non-illumination state. (Newly formed) The control unit according to claim 37, wherein the control unit is comprised of dimming control means for dimming the discharge lamp from an arc discharge area to a glow discharge area, wherein the level of the supplied DC power supplies the discharge during low light dimming. The relative illumination rate of the discharge lamp with respect to illumination at rated current is 20% or less in low luminous illumination, And said DC power supply means comprising means for adjusting the supply of said DC power in accordance with a dimming level. (Newly constructed) 47. The relative illumination rate of the discharge lamp to illumination at rated current is 5% at low luminous flux dimming, and the DC power supply means means for adjusting the DC power supply in accordance with the dimming level. Apparatus comprising a (New) The apparatus according to claim 48, wherein the DC power supply means includes means for adjusting the supply of the DC power according to the dimming level. (New) The method according to item 37, wherein the high frequency power source is controlled such that the lamp current is reduced so as to illuminate a discharge lamp and obtain a low luminous flux, and at a low luminous flux level, the DC power component of the lamp current is a value sufficient to obtain a glow discharge. Device which is maintained in