JPWO2020049637A1 - Learning device - Google Patents

Abstract

The learning device 100 is a learning device including a calculation unit 110 for inputting a matrix of M rows and N columns (M and N are integers of 1 or more each), and the calculation unit 110 includes a plurality of calculation units and a plurality of calculation units. When a matrix is input to the arithmetic unit 110, the arithmetic unit of the above reads each component of the matrix and inputs the read component to the corresponding arithmetic unit.

Description

The present invention relates to a learning device.

With the spread of machine learning, further ingenuity is required to cope with the ever-changing situation. In order to respond to the ever-changing situation, it is necessary to incorporate various raw data acquired in the environment in which it is used into learning as learning data. The training data is data used for training the discrimination model.

In learning using learning data (machine learning), for example, parameters of arithmetic expressions and discrimination expressions used in a predetermined learning device are adjusted based on the relationship between input and output indicated by the learning data. .. The learner is, for example, a discriminant model that discriminates about one or more labels when data is input.

As a relationship between arithmetic resources and arithmetic accuracy in machine learning, for example, Non-Patent Document 1 provides an example of a learning arithmetic circuit and a learning method for efficiently executing deep learning of a neural network with particularly low power consumption. Are listed.

Further, in Non-Patent Document 2, in deep learning in CNN (Convolutional Neural Network), a plurality of convolutional layers are divided into a layer in which weights are fixed and a layer in which weights are updated (extended function layer). An example of a learning method for shortening the learning time by limiting the above is described.

Further, as an example of a circuit configuration for learning calculation in machine learning, Non-Patent Document 3 describes an optimization example of accelerator design based on FPGA (Field-Programmable Gate Array).

The outline of the learning method will be described below. FIG. 10 is an explanatory diagram showing an example of a general learning method and a circuit configuration for learning in a neural network including one or more intermediate layers between an input layer and an output layer.

In the example shown in FIG. 10, the large-scale learning circuit 70 learns the entire neural network, which is a predetermined discrimination model, in order to correspond to the learning algorithm for general-purpose use.

The balloon attached to the large-scale learning circuit 70 shown in FIG. 10 schematically describes the direction of processing and the range of processing in the learning process of the neural network. In the balloon, the unit 71 corresponding to the neuron in the neural network is represented by an ellipse.

Further, the line segment 72 (the line connecting the units 71 shown in FIG. 10) represents the connection between the units 71. The arrow 73 (thick arrow pointing to the right in FIG. 10) represents the range of inference processing and inference processing. The arrow 74 (thick left-pointing arrow shown in FIG. 10) indicates the range of the parameter update process and the parameter update process. The parameter update process is an example of the learning process.

Note that FIG. 10 shows an example of a feedforward type neural network in which the input to each unit 71 is the output of the unit 71 in the previous layer. For example, when time series information is retained, the input to each unit 71 may include the output of the unit 71 of the previous layer at the previous time, as in a recurrent type neural network.

Even if the input to each unit 71 includes the output of the unit 71 of the previous layer at the previous time, the direction of the inference processing is considered to be the direction from the input layer to the output layer (forward direction). Is done. Further, the input to each unit 71 is not limited to the above example.

The inference processing performed from the input layer in a predetermined order is also called "forward propagation". On the other hand, the direction of parameter update processing is not particularly limited. For example, as in the parameter update process shown in FIG. 10, the direction of the parameter update process may be the direction from the output layer to the input layer (reverse direction).

The parameter update process shown in FIG. 10 is an example of a process executed by the error back propagation method. However, the parameter update process is not limited to the process executed by the error back propagation method. For example, the parameter update process may be executed by STDP (Spike Timing Dependent Plasticity).

The following learning methods can be mentioned as examples of model learning methods in deep learning, not limited to neural networks. First, after inputting training data into the input layer, inference processing is performed in each layer up to the output layer to calculate the output of each unit 71 in the forward direction (forward propagation: see arrow 73 shown in FIG. 10).

Next, the parameters used to calculate the output of each unit 71 in the layer are set based on the error calculated from the output from the output layer (final output) and the relationship between the input and output indicated by the training data. Performs parameter update processing to be updated (backpropagation: see arrow 74 shown in FIG. 10). As shown in FIG. 10, the parameter update process is performed by tracing each layer from the output layer to the first layer in the opposite direction. Further, the parameter update process is performed so that the calculated error is minimized.

As shown in FIG. 10, when the entire model is the learning target, the output of each unit 71 in all the layers (first layer to nth layer) after the input layer is calculated by the parameter update process. The parameters used for this are updated. The parameter to be updated is, for example, the weight of the bond between the units 71 that joins each unit 71 in the layer and the unit 71 in the other layer.

A trained model having a high recognition rate is generated by repeatedly executing the above parameter update process a plurality of times while changing the learning data, for example. FIG. 10 shows a large-scale learning circuit 70 that performs the above inference processing and parameter update processing with high calculation accuracy as an example of realizing a calculation circuit that performs learning.

FIG. 11 is an explanatory diagram showing an example of input / output of the unit 71 and connection with another unit 71 when focusing on one unit 71. FIG. 11A shows an example of input / output of one unit 71. Further, FIG. 11B shows an example of bonding between the units 71 arranged in two layers.

As shown in FIG. 11A, when four inputs (x _{1 to x 4} ) and one output (z) are given to one unit 71, the operation of the unit 71 is expressed by, for example, the equation (1A). ).

z = f (u) ・ ・ ・ Equation (1A)
However, u = a + w ₁ x ₁ + w ₂ x ₂ + w ₃ x ₃ + w ₄ x ₄ ... Equation (1B)

In addition, f () in the formula (1A) represents an activation function. Further, a in the formula (1B) represents an intercept. _{Further, w 1 to w 4} in the equation (1B) represent parameters such as weights corresponding to each input (x _{1 to x 4).}

On the other hand, as shown in FIG. 11B, when each unit 71 is connected between the layers arranged in two layers, when focusing on the subsequent layer, the input to each unit 71 in the layer (each x _{1). The output (z 1 to z 4} ) of each unit 71 with respect to ~ x ₄ ) is expressed, for example, as follows.

_{z i = f (u i)} ··· formula (2A)
_{However, u i = a + w i} , 1 x 1 + w i, 2 x 2 + w i, 3 x 3 + w i, 4 x 4 ··· formula (2B)

Note that i in the formula (2A) is an identifier of the unit 71 in the same layer (i = 1 to 3 in this example). It is also possible to regard the intercept a in the equation (2B) as a coefficient (that is, one of the parameters) of the constant term of the value 1.

In the following, equation (2B) is simplified.
u _i = Σ (wi _{, k} * x _k ) ・ ・ ・ Equation (2C)
May be written as. In the formula (2C), the intercept a is omitted. Further, k in the equation (2C) represents an input to each unit 71 in the layer, more specifically, an identifier of another unit 71 that performs the input.

If the input to each unit 71 in the layer is only the output of each unit 71 in the previous layer, the above simplified formula may be used.
u _i ^(L) = Σ (wi _{, k} ^(L) * x _k ^(L-1) ) ・ ・ ・ Equation (2D)
It is also possible to write.

In addition, L in the formula (2D) represents the identifier of the layer. _{Further, wi and k} in the equation (2D) represent the parameters of each unit i in the L layer. More specifically, wi _{and k} correspond to the weight of the connection between each unit i and the other unit k (connection between units 71).

Hereinafter, the unit 71 is not particularly distinguished, and the function (activation function) that determines the output value of the unit 71 may be simplified and described as z = Σ (w * x).

The above set of weights is described in vector form as follows.

w _i = [wi _{, 1} , wi _{, 2} , ..., wi _{, k} ] ^T ... Equation (3)

Equation (3) is called a weight vector. _{Further, if the input vector x = [x 1} , x ₂ , ..., X _k ] ^T , which is a set of inputs of a certain layer, and the weight matrix obtained by horizontally connecting the weight vectors is W, the output vector z is f ( represented by W ^T x). The following relationship holds between the output vector z and the activation function.

_{z = f (u) = [} f (u 1), f (u 2), ···, f (u n)] ··· Equation (4)

In the above example, the calculation in which a certain unit 71 obtains the output z from the input x corresponds to the inference processing in the unit 71. Parameters (for example, weight w) are fixed in the inference process. The inference process is, for example, a process executed in an operating monitoring system or the like to determine whether or not an object in an image is a specific object. On the other hand, the calculation for obtaining the parameters of the unit 71 corresponds to the parameter update process in the unit 71.

FIG. 12 shows an example of an inference device that performs inference processing. FIG. 12 is a block diagram showing a configuration example of a general inference device. The inference device 80 shown in FIG. 12 includes a weight memory 81, a weight loading unit 82, and a calculation unit 83.

The weight memory 81 has a function of storing the weight matrix W. The weight loading unit 82 has a function of loading the weight matrix W stored in the weight memory 81 from the weight memory 81.

The weight loading unit 82 inputs the loaded weight matrix W to the calculation unit 83. The calculation unit 83 has a function of performing the above inference processing using the input weight matrix W.

Next, FIG. 13 shows an example of a learning device that performs parameter update processing. FIG. 13 is a block diagram showing a configuration example of a general learning device. The learning device 90 shown in FIG. 13 includes a weight memory 91, a weight loading unit 92, a calculation unit 93, and a weight store unit 94.

The weight memory 91 has a function of storing the weight matrix W. The weight loading unit 92 has a function of loading the weight matrix W stored in the weight memory 91 from the weight memory 91.

The weight loading unit 92 inputs the loaded weight matrix W to the calculation unit 93. The calculation unit 93 has a function of performing the above parameter update process using the input weight matrix W.

The calculation unit 93 inputs the weight matrix W updated in the parameter update process to the weight store unit 94. The weight store unit 94 has a function of writing the weight matrix W updated by the calculation unit 93 to the weight memory 91.

Specifically, the weight store unit 94 updates the weight matrix W stored in the weight memory 91 to the input weight matrix W. When writing the weight matrix W, the weight store unit 94 may have a function of temporarily storing the weight matrix W.

Further, as another example of an apparatus that executes inference processing and learning processing, Patent Document 1 describes a neuroprocessor that performs inference and learning calculations of a neural network at high speed without increasing hardware.

Japanese Unexamined Patent Publication No. 5-346914

YHChen, et.al., "Eyeriss: an Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks", in IEEE Jornal of Slid-State Circuits, vol.52, no.1, Jan. 2017, pp.127-138 .. Wei. Liu, et.al., "SSD: Single shot MultiBox Detector", arXiv: 1512.02325v5, Dec. 2016. Chen Zhang, et.al., "Optimizing FPGA-based Accelerator Design for Deep convolutional Neural Networks", In ACM FPGA 2015, pp.160-170.

In the above learning process, each component of the weight matrix W is rearranged and used. For example, such transposed matrix W ^T of the weight matrix W, disposed was replaced matrix of each component are used.

Weight loading unit 92 shown in FIG. 13, arranged to generate a transposed matrix W ^T, for example, reads out the components of the weight matrix W stored in the weight memory 91 for each row, each read component Repeat the work of changing.

However, the method of repeatedly executing the loading of the weight matrix W from the weight memory 91 and the rearrangement of each component consumes a large amount of power. In addition, the time required for rearranging each component becomes longer.

Further, even if each component of the weight matrix W is rearranged on the weight memory 91 side, power is consumed when the weight loading unit 92 transfers the matrix to the calculation unit 93. Patent Document 1 and Non-Patent Documents 1 to 3 do not describe a method for rearranging each component of a matrix having low power consumption.

[Purpose of Invention]
Therefore, an object of the present invention is to provide a learning device capable of rearranging each component of a matrix with low power consumption, which solves the above-mentioned problems.

The learning device according to the present invention is a learning device including a calculation unit for inputting a matrix of M rows and N columns (M and N are integers of 1 or more each), and the calculation unit includes a plurality of calculation units and a plurality of calculation units. When a matrix is input to the arithmetic unit, each component of the matrix is read, and the read component is input to the corresponding arithmetic unit.

According to the present invention, each component of the matrix can be rearranged with low power consumption.

It is a block diagram which shows the structural example of the 1st Embodiment of the learning apparatus by this invention. It is a block diagram which shows the structural example of the arithmetic unit 1300 of 1st Embodiment. It is a block diagram which shows the other structural example of the arithmetic unit 1300 of 1st Embodiment. It is a block diagram which shows the other structural example of the arithmetic unit 1300 of 1st Embodiment. It is a flowchart which shows the operation of the transposed matrix generation processing by the arithmetic unit 1300 of 1st Embodiment. It is a block diagram which shows the structural example of the arithmetic unit 1300 of 2nd Embodiment. It is a flowchart which shows the operation of the 180 degree rotation matrix generation processing by the arithmetic unit 1300 of 2nd Embodiment. It is explanatory drawing which shows the hardware configuration example of the learning apparatus 1000 by this invention. It is a block diagram which shows the outline of the learning apparatus by this invention. It is explanatory drawing which shows the example of the general learning method in the neural network which includes one or more intermediate layers between an input layer and an output layer, and the circuit structure for learning. It is explanatory drawing which shows the example of the input / output of a unit 71 and the coupling with another unit 71 when paying attention to one unit 71. It is a block diagram which shows the structural example of a general inference device. It is a block diagram which shows the structural example of a general learning apparatus.

Embodiment 1.
[Description of configuration]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a first embodiment of the learning device according to the present invention.

As shown in FIG. 1, the learning device 1000 includes a weight memory 1100, a weight loading unit 1200, a calculation unit 1300, and a weight store unit 1400.

The unidirectional arrow shown in each block diagram indicates the direction in which the data flows. However, the possibility that data flows in both directions at the points where each arrow is described is not excluded.

In order to rearrange each component of the weight matrix W with low power consumption, it is conceivable that the calculation unit 1300 includes a group of calculation units having wiring capable of internally transferring the components.

Compared to the work in which the weight loading unit 1200 reads out each component of the weight matrix W line by row and rearranges each component, the work in which each arithmetic unit that reads the component rearranges each component by exchanging the components is better. Low power consumption. Hereinafter, the functions of each component of the learning device 1000 that rearranges each component of the weight matrix W with low power consumption will be described.

The weight memory 1100 has a function of storing a weight matrix W (parameter group) used for inference processing and learning processing. The weight of each unit 71 is a parameter of each unit 71 in the present embodiment. The discrimination model is, for example, a neural network.

The weight loading unit 1200 has a function of loading the weight matrix W from the weight memory 1100. Regardless of whether the inference process or the learning process is performed, the weight loading unit 1200 loads the weight matrix W as it is from the weight memory 1100. The weight loading unit 1200 inputs the loaded weight matrix W to the calculation unit 1300.

The arithmetic unit 1300 has a function of performing the above inference processing or the above learning processing using the weight matrix W loaded from the weight memory 1100.

Specifically, the calculation unit 1300 is an inference that calculates the output for the discrimination data of each unit 71 of the discrimination model in which a plurality of layers each composed of one or more units 71 are connected in a layered manner in a predetermined order. Execute the process. Further, the arithmetic unit 1300 executes a learning process of updating at least a part of the weights of each unit 71 based on the output of the learning data of each unit 71.

The calculation unit 1300 inputs the weight matrix W updated in the learning process to the weight store unit 1400. The weight store unit 1400 has a function of writing the weight matrix W updated by the calculation unit 1300 to the weight memory 1100.

Specifically, the weight store unit 1400 updates the weight matrix W stored in the weight memory 1100 to the input weight matrix W. When writing the weight matrix W, the weight store unit 1400 may have a function of temporarily storing the weight matrix W.

That is, the weight store unit 1400 stores the weight (weight matrix W) to be updated of each unit 71 in the learning process in the weight memory 1100. By storing the weight matrix W in the weight memory 1100 by the weight store unit 1400, the updated weight matrix W is used in the next inference processing and learning processing.

FIG. 2 is a block diagram showing a configuration example of the calculation unit 1300 of the first embodiment. As shown in FIG. 2, the arithmetic unit 1300 includes arithmetic units 1301 to 1309, first weight registers 1311 to 1319, and second weight registers 1321 to 1329.

The arithmetic unit 1300 of the present embodiment includes nine arithmetic units. The number of arithmetic units included in the arithmetic unit 1300 is not limited to nine. The arithmetic unit 1300 may include a plurality of arithmetic units arranged in a matrix format. The calculation unit 1300 of the present embodiment includes a calculation unit arranged in a matrix format of 3 rows and 3 columns.

As shown in FIG. 2, the arithmetic unit 1301 is arranged in the arithmetic unit 1300 together with the first weight register 1311 and the second weight register 1321. Similarly, other arithmetic units are arranged in the arithmetic unit 1300 together with the first weight register and the second weight register.

The weights read by each arithmetic unit when the weight matrix W is input to the arithmetic unit 1300 are stored in the first weight register. Each arithmetic unit reads a component of the weight matrix W corresponding to its own arrangement.

Specifically, the arithmetic unit arranged in the m (m is an integer of 1 or more and 3 or less) th from the top and n (n is an integer of 1 or more and 3 or less) from the left in the arithmetic unit 1300 is the arithmetic unit. When the weight matrix W is input to 1300, the (m, n) component of the weight matrix W is read.

In the example shown in FIG. 2, the arithmetic unit 1301 arranged first from the top and first from the left reads the _{weight w 1, which is the (1,1) component of the weight matrix W. The weight w 1} read by the arithmetic unit 1301 is stored in the first weight register 1311. Each arithmetic unit executes inference processing and learning processing using the weights stored in the first weight register.

Further, as shown in FIG. 2, the arithmetic unit 1300 is used between the arithmetic unit 1302 and the arithmetic unit 1304, between the arithmetic unit 1303 and the arithmetic unit 1307, and between the arithmetic unit 1306 and the arithmetic unit 1308. Each data is configured to be transferable. Specifically, as shown in FIG. 2, the arithmetic units are connected to each other by wiring.

In the learning process, the transposed matrix W ^T of the weight matrix W is used. In the example shown in FIG. 2, the weight w ₂ is (1,2) component of the weight matrix W becomes the transposed matrix W ^T (2,1) component. The weight w ₄ is a (2,1) component of the weight matrix W becomes a transposed matrix W, ^T (1, 2) component.

Therefore, when the learning process is executed, the weights are exchanged between the arithmetic unit 1302 and the arithmetic unit 1304. _{Specifically, the arithmetic unit 1302 writes the weight w 2} stored in the first weight register 1312 to the second weight register 1324 of the arithmetic unit 1304.

_{Further, the arithmetic unit 1304 writes the weight w 4} stored in the first weight register 1314 to the second weight register 1322 of the arithmetic unit 1302. Similarly, weights are exchanged between the arithmetic unit 1303 and the arithmetic unit 1307, and between the arithmetic unit 1306 and the arithmetic unit 1308, respectively.

In the configuration example shown in FIG. 2, since there is only one wiring between the two arithmetic units, the weight exchange is performed according to, for example, a time division multiplexing method.

When the weights are exchanged according to the time division multiplexing method, the arithmetic unit 1302 _{writes the weight w 2} to the second weight register 1324, and then the arithmetic unit 1304 writes the weight w ₄ to the second weight register 1322. Similarly, the arithmetic unit 1303 and the arithmetic unit 1307, and the arithmetic unit 1306 and the arithmetic unit 1308 also exchange weights according to the time division multiplexing method.

After the weights are exchanged, each arithmetic unit except the arithmetic unit 1301, the arithmetic unit 1305, and the arithmetic unit 1309 replaces the weight written in the second weight register with the weight stored in the first weight register.

For example, the arithmetic unit 1302 _{writes the weight w 4} written in the second weight register 1322 to the first weight register 1312. _{Further, the arithmetic unit 1302 writes the weight w 2} stored in the first weight register 1312 to the second weight register 1322.

By executing the above processing, the arithmetic unit 1300 generates a transposed matrix W ^T of the weight matrix W virtually. In other words, each first weight registers, each weight is stored in the array as the transposed matrix W ^T shown in FIG. Therefore, calculation unit 1300 may perform a learning process using the transposed matrix W ^T.

FIG. 3 is a block diagram showing another configuration example of the calculation unit 1300 of the first embodiment. As shown in the configuration example shown in FIG. 3, there are two, respectively, between the arithmetic unit 1302 and the arithmetic unit 1304, between the arithmetic unit 1303 and the arithmetic unit 1307, and between the arithmetic unit 1306 and the arithmetic unit 1308. Wiring may be present.

The two arithmetic units connected by the two wires shown in FIG. 3 can exchange weights at the same time. For example, the operation of the arithmetic unit 1302 _{writing the weight w 2} to the second weight register 1324 and the operation of the arithmetic unit 1304 writing the weight w ₄ to the second weight register 1322 can be executed at the same time.

In the configuration examples shown in FIGS. 2 to 3, since the arithmetic units that exchange weights are directly connected to each other, each weight is transferred only once. That is, the power consumed by the rearrangement of each weight is the lowest.

FIG. 4 is a block diagram showing another configuration example of the calculation unit 1300 of the first embodiment. Unlike the configuration examples shown in FIGS. 2 to 3, in the configuration example shown in FIG. 4, the arithmetic units that exchange weights are not directly connected to each other.

Each arithmetic unit shown in FIG. 4 exchanges each weight as follows. For example, the arithmetic unit 1302 first _{writes the weight w 2} to the second weight register 1321 of the arithmetic unit 1301. Next, the arithmetic unit 1301 _{writes the written weight w 2} to the second weight register 1324 of the arithmetic unit 1304.

After the weight w ₂ is written to the second weight register 1324, the arithmetic unit 1304 _{writes the weight w 4} to the second weight register 1321 of the arithmetic unit 1301. Next, the arithmetic unit 1301 _{writes the written weight w 4} to the second weight register 1322 of the arithmetic unit 1302.

As described above, each arithmetic unit shown in FIG. 4 inputs a weight to the destination arithmetic unit via another arithmetic unit. _{As shown in FIG. 4, the weight w 2} and the weight w ₄ are exchanged via the arithmetic unit 1302 and the arithmetic unit 1304 connected by the solid arrow.

_{Similarly, the weight w 3} and the weight w ₇ are exchanged via the arithmetic unit 1302, the arithmetic unit 1304, and the arithmetic unit 1305 connected to the arithmetic unit 1303 and the arithmetic unit 1307 by a broken arrow. _{In addition, the weight w 6} and the weight w ₈ are exchanged via the arithmetic unit 1306 and the arithmetic unit 1308 connected to the arithmetic unit 1308 by a thick arrow.

The weights may be exchanged via a route other than the route shown in FIG. Further, as in the configuration example shown in FIG. 3, two wires (corresponding to the arrows shown in FIG. 4) may exist between each arithmetic unit.

After the weights are exchanged, each arithmetic unit except the arithmetic unit 1301, the arithmetic unit 1305, and the arithmetic unit 1309 replaces the weight written in the second weight register with the weight stored in the first weight register.

As shown in FIG. 4, if each arithmetic unit can freely set the transfer destination of the weight, that is, if each arithmetic unit has a routing ability, the exchange of weights between the arithmetic units is executed more flexibly. ..

The operation of each arithmetic unit included in the arithmetic unit 1300 in which the matrix of M rows and N columns (M and N are integers of 1 or more) of the present embodiment is generalized and described as follows. When m is an integer of 1 or more and M or less and n is an integer of 1 or more and N or less, each of the m-th and n-th arithmetic units from the top among the plurality of arithmetic units included in the arithmetic unit 1300 of the present embodiment. Reads the (m, n) components of the matrix when the matrix of M rows and N columns is input to the arithmetic unit 1300.

In the present embodiment, the m-th and n-th (m ≠ n) arithmetic units from the top correspond to the n-th and m-th arithmetic units from the left. That is, the arithmetic unit that reads the (m, n) component (m ≠ n) of the matrix corresponds to the arithmetic unit that reads the (n, m) component of the matrix. Each arithmetic unit inputs the read component to the corresponding arithmetic unit.

The reason for setting "m ≠ n" is to exclude the arithmetic units (for example, arithmetic unit 1301, arithmetic unit 1305, and arithmetic unit 1309) corresponding to the diagonal components of the square matrix. By the above operation, the calculation unit 1300 can generate a transposed matrix W ^T based on weight matrix W with low power consumption.

[Explanation of operation]
Hereinafter, the operation unit 1300 of the present embodiment will be described with reference to FIG. 5 the operation of generating the transposed matrix W ^T. FIG. 5 is a flowchart showing the operation of the transposed matrix generation process by the calculation unit 1300 of the first embodiment.

First, when the weight matrix W is input to the arithmetic unit 1300, each arithmetic unit reads the corresponding weight of the weight matrix W (step S101). Each arithmetic unit stores the read weight in the first weight register.

Then, each arithmetic unit except the arithmetic unit 1301, the arithmetic unit 1305, and the arithmetic unit 1309 exchanges weights with the corresponding arithmetic units (step S102). That is, each arithmetic unit writes the stored weight to the second weight register of the corresponding arithmetic unit. In addition, weights are written from the corresponding arithmetic units to the second weight register of each arithmetic unit.

Next, each arithmetic unit except the arithmetic unit 1301, the arithmetic unit 1305, and the arithmetic unit 1309 replaces the weight written in the second weight register with the weight stored in the first weight register (step S103).

That is, each arithmetic unit writes the weight written in the second weight register to the first weight register. Further, each arithmetic unit writes the weight stored in the first weight register to the second weight register. After exchanging each weight, the arithmetic unit 1300 ends the transposed matrix generation process.

[Explanation of effect]
The learning device 1000 of the present embodiment includes a calculation unit 1300 including a plurality of calculation units directly connected by wiring. Arithmetic units connected by wiring can exchange read weights. That is, the calculation unit 1300 can easily generate a transposed matrix W ^T from the input weight matrix W.

Since the arithmetic unit 1300 generates a transposed matrix W ^T, as compared with the learning apparatus for executing repeatedly sorting load and the components of the weight matrix W, the learning device 1000 of this embodiment, in the generation of the transposed matrix W ^T The power consumed can be reduced.

Embodiment 2.
[Description of configuration]
Next, a second embodiment of the arithmetic unit 1300 according to the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing a configuration example of the calculation unit 1300 of the second embodiment. The configuration of the learning device 1000 of this embodiment is the same as the configuration of the learning device 1000 shown in FIG.

As shown in FIG. 6, the arithmetic unit 1300 of the present embodiment also includes arithmetic units 1301 to 1309, first weight registers 1311 to 1319, and second weight registers 1321 to 1329, similarly to the first embodiment. .. That is, the calculation unit 1300 of the present embodiment also includes a calculation unit arranged in a matrix format of 3 rows and 3 columns.

Each arithmetic unit is arranged in the arithmetic unit 1300 together with the first weight register and the second weight register. Each function of the arithmetic unit, the first weight register, and the second weight register is the same as each function in the first embodiment.

As shown in FIG. 6, the arithmetic unit 1300 is configured so that data can be transferred between each arithmetic unit other than the arithmetic unit 1305.

In the learning process, in addition to the transposed matrix W ^T of the weight matrix W, the matrix of the weights of the weight matrix W is placed at a position opposite to 180 degrees (hereinafter, referred to as 180-degree rotation matrix.) Are also used. In the example shown in FIG. 6, the weight w _2, which is the (1,2) component of the weight matrix W, becomes the (3,2) component in the 180-degree rotation matrix.

That is, the (1,2) component of the weight matrix W is treated as the (3,2) component = ((3 + 1-1), (3 + 1-2)) component in the 180-degree rotation matrix. "3" in (3 + 1-1) is the number of rows in the weight matrix W. The second "1" in (3 + 1-1) corresponds to the "1" in the (1,2) component of the weight matrix W.

Further, "3" in (3 + 1-2) is the number of columns of the weight matrix W. Further, "2" in (3 + 1-2) corresponds to "2" in the (1,2) component of the weight matrix W. The components of the other weight matrix W are also rearranged according to the same formula.

Therefore, when the learning process is executed, the weight w ₂ and the weight w ₈ are exchanged between the arithmetic unit 1302 and the arithmetic unit 1308. Specifically, the arithmetic unit 1302 first _{writes the weight w 2} to the second weight register 1323 of the arithmetic unit 1303. Next, the arithmetic unit 1303 _{writes the written weight w 2} to the second weight register 1326 of the arithmetic unit 1306.

Next, the arithmetic unit 1306 _{writes the written weight w 2} to the second weight register 1329 of the arithmetic unit 1309. Next, the arithmetic unit 1309 _{writes the written weight w 2} to the second weight register 1328 of the arithmetic unit 1308. Similarly, the arithmetic unit 1308 also _{writes the weight w 8} to the second weight register 1322 of the arithmetic unit 1302 via another arithmetic unit.

As described above, each arithmetic unit shown in FIG. 6 inputs a weight to the destination arithmetic unit via another arithmetic unit. _{Similarly, the weight w 1} and the weight w ₉ are exchanged between the arithmetic unit 1301 and the arithmetic unit 1309. _{Further, the weight w 3} and the weight w ₇ are exchanged between the arithmetic unit 1303 and the arithmetic unit 1307. _{Further, the weight w 4} and the weight w ₆ are exchanged between the arithmetic unit 1304 and the arithmetic unit 1306.

The weights may be exchanged via a route other than the route shown in FIG. Further, as in the configuration example shown in FIG. 3, two wires (corresponding to the arrows shown in FIG. 6) may exist between each arithmetic unit.

After the weights are exchanged, each arithmetic unit except the arithmetic unit 1305 replaces the weight written in the second weight register with the weight stored in the first weight register.

As shown in FIG. 6, if each arithmetic unit can freely set the transfer destination of the weight, that is, if each arithmetic unit has a routing ability, the exchange of weights between the arithmetic units is executed more flexibly. ..

Further, as in the configuration example shown in FIG. 2, the arithmetic units whose weights are exchanged may be connected by wiring. Further, as in the configuration example shown in FIG. 3, the arithmetic units whose weights are exchanged may be connected by two wirings.

The operation of each arithmetic unit included in the arithmetic unit 1300 in which the matrix of M rows and N columns (M and N are integers of 1 or more) of the present embodiment is generalized and described as follows. When m is an integer of 1 or more and M or less and n is an integer of 1 or more and N or less, each of the m-th and n-th arithmetic units from the top among the plurality of arithmetic units included in the arithmetic unit 1300 of the present embodiment. Reads the (m, n) components of the matrix when the matrix of M rows and N columns is input to the arithmetic unit 1300.

In this embodiment, the m-th from the top and the n-th from the left (2 × m-1 ≠ M and 2 × n-1 ≠ N), the (M + 1-m) th from the top, and the (N + 1) from the left. −n) Corresponds to the th-th arithmetic unit. That is, the arithmetic unit that read the (m, n) component of the matrix (2 × m-1 ≠ M and 2 × n-1 ≠ N) and the (M + 1-m, N + 1-n) component of the matrix were read. Corresponds to the arithmetic unit. Each arithmetic unit inputs the read component to the corresponding arithmetic unit.

The reason for setting "2 x m-1 ≠ M and 2 x n-1 ≠ N" is that the arithmetic unit corresponding to the component located at the center of the square matrix having an odd number of rows and columns (for example, This is to exclude the arithmetic unit 1305). By the above operation, the arithmetic unit 1300 can generate a 180-degree rotation matrix based on the weight matrix W with low power consumption.

[Explanation of operation]
Hereinafter, the operation of the arithmetic unit 1300 of the present embodiment to generate a 180-degree rotation matrix will be described with reference to FIG. 7. FIG. 7 is a flowchart showing the operation of the 180-degree rotation matrix generation process by the calculation unit 1300 of the second embodiment.

First, when the weight matrix W is input to the arithmetic unit 1300, each arithmetic unit reads the corresponding weight of the weight matrix W (step S201). Each arithmetic unit stores the read weight in the first weight register.

Next, each arithmetic unit except the arithmetic unit 1305 exchanges weights with the corresponding arithmetic unit (step S202). That is, each arithmetic unit writes the stored weight to the second weight register of the corresponding arithmetic unit. In addition, weights are written from the corresponding arithmetic units to the second weight register of each arithmetic unit.

Next, each arithmetic unit except the arithmetic unit 1305 replaces the weight written in the second weight register with the weight stored in the first weight register (step S203).

That is, each arithmetic unit writes the weight written in the second weight register to the first weight register. Further, each arithmetic unit writes the weight stored in the first weight register to the second weight register. After exchanging each weight, the arithmetic unit 1300 ends the 180-degree rotation matrix generation process.

[Explanation of effect]
The learning device 1000 of the present embodiment includes a calculation unit 1300 including a plurality of calculation units directly connected by wiring. Arithmetic units connected by wiring can exchange read weights. That is, the arithmetic unit 1300 can easily generate a 180-degree rotation matrix from the input weight matrix W.

Since the arithmetic unit 1300 generates a 180-degree rotation matrix, the learning device 1000 of the present embodiment can generate a 180-degree rotation matrix, as compared with a learning device that repeatedly loads the weight matrix W and rearranges each component. The power consumed can be reduced.

Hereinafter, a specific example of the hardware configuration of the learning device 1000 of each embodiment will be described. FIG. 8 is an explanatory diagram showing a hardware configuration example of the learning device 1000 according to the present invention.

The learning device 1000 shown in FIG. 8 includes a processor 1001, a main storage device 1002, an auxiliary storage device 1003, an interface 1004, an output device 1005, and an input device 1006. Further, the processor 1001 may include various arithmetic / processing devices such as a CPU 1008 and a GPU 1007.

When implemented as shown in FIG. 8, the operation of the learning device 1000 may be stored in the auxiliary storage device 1003 in the form of a program. When the program is stored in the auxiliary storage device 1003, the CPU 1008 reads the program from the auxiliary storage device 1003, expands it in the main storage device 1002, and executes a predetermined process in the learning device 1000 according to the expanded program.

The CPU 1008 is an example of an information processing device that operates according to a program. The learning device 1000 may include, for example, an MPU (Micro Processing Unit), an MCU (Memory Control Unit), or a GPU (Graphics Processing Unit) in addition to the CPU (Central Processing Unit). FIG. 8 shows an example in which the learning device 1000 further includes the GPU 1007 in addition to the CPU 1008.

Auxiliary storage 1003 is an example of a non-temporary tangible medium. Other examples of non-temporary tangible media include magnetic disks, magneto-optical disks, CD-ROMs (Compact Disk Read Only Memory), DVD-ROMs (Digital Versatile Disk Read Only Memory), which are connected via interface 1004. Examples include semiconductor memory.

Further, when the target program stored in the auxiliary storage device 1003 is distributed to the learning device 1000 by a communication line instead of being stored in the auxiliary storage device 1003, the distributed learning device 1000 delivers the distributed program. It may be expanded to the main storage device 1002 and a predetermined process may be executed.

Further, the program may be used to realize a part of a predetermined process in the learning device 1000. Further, the program may be a difference program for realizing a predetermined process in the learning device 1000, which is used in combination with another program already stored in the auxiliary storage device 1003.

Interface 1004 sends and receives information to and from other devices. The output device 1005 also presents information to the user. Further, the input device 1006 accepts the input of information from the user.

Further, some elements shown in FIG. 8 can be omitted depending on the processing content of the learning device 1000. For example, if the learning device 1000 does not present information to the user, the output device 1005 can be omitted. Further, for example, if the learning device 1000 does not accept information input from the user, the input device 1006 can be omitted.

In addition, some or all of the above components are realized by a general-purpose or dedicated circuit (Circuitry), a processor, or a combination thereof. These may be composed of a single chip or may be composed of a plurality of chips connected via a bus. Further, a part or all of the above-mentioned components may be realized by a combination of the above-mentioned circuit or the like and a program.

When a part or all of each of the above components is realized by a plurality of information processing devices and circuits, the plurality of information processing devices and circuits may be centrally arranged or distributed. Good. For example, the information processing device, the circuit, and the like may be realized as a form in which each is connected via a communication network, such as a client-and-server system and a cloud computing system.

Next, the outline of the present invention will be described. FIG. 9 is a block diagram showing an outline of the learning device according to the present invention. The learning device 100 according to the present invention is a learning device including a calculation unit 110 (for example, a calculation unit 1300) in which a matrix of M rows and N columns (M and N are each an integer of 1 or more) is input, and is a calculation unit 110. Includes a plurality of arithmetic units (for example, arithmetic units 1301 to 1309), and the plurality of arithmetic units read each component of the matrix when a matrix is input to the arithmetic unit 110, and perform the corresponding operation on the read component. Enter each in the vessel.

With such a configuration, the learning device can sort each component of the matrix with low power consumption.

Further, when m is an integer of 1 or more and M or less and n is an integer of 1 or more and N or less, the arithmetic unit that reads the (m, n) component (m ≠ n) of the matrix and the (n, m) of the matrix. It may correspond to the arithmetic unit that has read the components.

With such a configuration, the learning device can generate a transposed matrix.

Further, the m-th and n-th (m ≠ n) arithmetic units from the top among the plurality of arithmetic units arranged in the matrix format are the n-th from the top and m from the left among the plurality of arithmetic units. Corresponding to the second arithmetic unit, when the matrix is input to the arithmetic unit 110, the (m, n) component of the matrix may be read.

With such a configuration, the learning device can generate a transposed matrix by utilizing the arrangement of a plurality of arithmetic units.

Further, when m is an integer of 1 or more and M or less and n is an integer of 1 or more and N or less, the (m, n) component (2 × m-1 ≠ M and 2 × n-1 ≠ N) of the matrix is set. The read arithmetic unit may correspond to the arithmetic unit that has read the (M + 1-m, N + 1-n) component of the matrix.

With such a configuration, the learning device can generate a 180 degree rotation matrix.

Further, among the plurality of arithmetic units arranged in the matrix format, the m-th and n-th (2 × m-1 ≠ M and 2 × n-1 ≠ N) arithmetic units from the top are a plurality of arithmetic units. Corresponds to the (M + 1-m) th arithmetic unit from the top and the (N + 1-n) th arithmetic unit from the left, and when a matrix is input to the arithmetic unit 110, even if the (m, n) component of the matrix is read. Good.

With such a configuration, the learning device can generate a 180 degree rotation matrix by utilizing the arrangement of a plurality of arithmetic units.

Further, each arithmetic unit may be connected to the corresponding arithmetic unit by wiring.

With such a configuration, the learning device can further reduce the power consumption related to the rearrangement of each component of the matrix.

Further, each arithmetic unit may be connected to the corresponding arithmetic unit by two wirings.

With such a configuration, the learning device can exchange each component of the matrix more quickly.

Further, each arithmetic unit may input a component read into the corresponding arithmetic unit via another arithmetic unit.

With such a configuration, the learning device is applied for purposes other than the generation of transposed matrices or 180 degree rotation matrices.

Further, each arithmetic unit may be connected to another arithmetic unit by two wirings.

With such a configuration, the learning device can exchange each component of the matrix more quickly.

Further, the matrix component may be a parameter of each unit of the discrimination model in which a plurality of layers each composed of one or more units are connected in a layered manner.

With such a configuration, the learning device can handle the weight matrix.

Further, the discrimination model may be a neural network.

With such a configuration, the learning device can perform deep learning.

Although the present invention has been described above with reference to the embodiments and examples, the present invention is not limited to the above embodiments and examples. Various changes that can be understood by those skilled in the art can be made within the scope of the present invention in terms of the structure and details of the present invention.

70 Large-scale learning circuit
71 units
80 Inference device
81, 91, 1100 Weight memory
82, 92, 1200 Weight load section
83, 93, 110, 1300 Arithmetic unit
90, 100, 1000 learning device
94, 1400 Weight store
1001 processor
1002 main memory
1003 Auxiliary storage
1004 interface
1005 output device
1006 input device
1007 GPU
1008 CPU
1301-1309 Arithmetic
1311-1319 1st weight register
1321 to 1329 2nd weight register

Claims (10)

It is a learning device provided with a calculation unit for inputting a matrix of M rows and N columns (M and N are integers of 1 or more each).
The calculation unit
Including multiple arithmetic units
The plurality of arithmetic units are
When the matrix is input to the calculation unit, each component of the matrix is read and read.
A learning device characterized in that the read components are input to the corresponding arithmetic units. When m is an integer of 1 or more and M or less, and n is an integer of 1 or more and N or less, an arithmetic unit that reads the (m, n) component (m ≠ n) of the matrix and the (n, m) component of the matrix. The learning device according to claim 1, wherein the arithmetic unit that has read the above corresponds to the arithmetic unit. Of the multiple arithmetic units arranged in a matrix format, the m-th and n-th (m ≠ n) arithmetic units from the top are
Corresponds to the nth arithmetic unit from the top and the mth arithmetic unit from the left among the plurality of arithmetic units.
The learning device according to claim 2, wherein when a matrix is input to the arithmetic unit, the (m, n) component of the matrix is read. When m is an integer of 1 or more and M or less and n is an integer of 1 or more and N or less, the (m, n) component (2 × m-1 ≠ M and 2 × n-1 ≠ N) of the matrix is read. The learning device according to claim 1, wherein the arithmetic unit and the arithmetic unit that has read the (M + 1-m, N + 1-n) components of the matrix correspond to each other. Of the plurality of arithmetic units arranged in a matrix format, the m-th and n-th from the left (2 × m-1 ≠ M and 2 × n-1 ≠ N) arithmetic units are
Corresponds to the (M + 1-m) th arithmetic unit from the top and the (N + 1-n) th arithmetic unit from the left among the plurality of arithmetic units.
The learning device according to claim 4, wherein when a matrix is input to the arithmetic unit, the (m, n) component of the matrix is read. The learning device according to any one of claims 1 to 5, wherein each arithmetic unit is connected to a corresponding arithmetic unit by wiring. The learning device according to claim 6, wherein each arithmetic unit is connected to a corresponding arithmetic unit by two wires. The learning device according to any one of claims 1 to 5, wherein each arithmetic unit inputs a component read into a corresponding arithmetic unit via another arithmetic unit. The learning device according to claim 8, wherein each arithmetic unit is connected to another arithmetic unit by two wires. The component of the matrix is described in any one of claims 1 to 9, which is a parameter of each unit of the discrimination model in which a plurality of layers each composed of one or more units are connected in a layered manner. Learning device.

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