JPWO2019164710A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2019164710A5 JPWO2019164710A5 JP2020544520A JP2020544520A JPWO2019164710A5 JP WO2019164710 A5 JPWO2019164710 A5 JP WO2019164710A5 JP 2020544520 A JP2020544520 A JP 2020544520A JP 2020544520 A JP2020544520 A JP 2020544520A JP WO2019164710 A5 JPWO2019164710 A5 JP WO2019164710A5
- Authority
- JP
- Japan
- Prior art keywords
- memory location
- data
- cache
- level cache
- processing unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000875 corresponding Effects 0.000 claims 18
- 238000001514 detection method Methods 0.000 claims 7
- 230000003111 delayed Effects 0.000 claims 2
- 238000004590 computer program Methods 0.000 claims 1
Claims (20)
複数の処理ユニットと、
複数のNレベルキャッシュと、
前記複数のNレベルキャッシュのうちの2つ以上に関連付けられ、前記複数のNレベルキャッシュのバッキングストアとして構成された(N+i)レベルキャッシュと、
制御論理であって、少なくとも、
複数のNレベルキャッシュのうちの第1のNレベルキャッシュへの、メモリ位置に格納されたデータを含む流入を検出することと、
前記第1のNレベルキャッシュへの前記流入を検出したことに基づいて、前記(N+i)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に第2の処理ユニットのためにログされているかどうかを判定し、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているときに、以前に前記第2の処理ユニットのためにログされたログデータを参照して、前記メモリ位置の前記データを第1の処理ユニットのためにログさせることと、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされていないときに、前記メモリ位置の前記データを前記第1の処理ユニットのために値によってログさせることと
のうちの一方を実行することと
を実行するように前記コンピューティングデバイスを構成する制御論理と
を備えたコンピューティングデバイス。 It ’s a computing device,
With multiple processing units
Multiple N-level caches and
A (N + i) level cache associated with two or more of the plurality of N-level caches and configured as a backing store for the plurality of N-level caches.
Control logic, at least
To detect an inflow containing data stored in a memory location into the first N-level cache of a plurality of N-level caches.
Based on the detection of the inflow into the first N-level cache, the (N + i) level cache is checked and the data at the memory location is previously logged for the second processing unit. Determine if there is,
When the data in the memory location was previously logged for the second processing unit, reference to the log data previously logged for the second processing unit in the memory location. Logging the data for the first processing unit
Of having the data at the memory location logged by value for the first processing unit when the data at the memory location was not previously logged for the second processing unit. A computing device with a control logic that configures the computing device to perform one and the other.
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインに、1つまたは複数のアカウンティングビットが設定されているかどうかを判定することと、
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインが、ログされた処理ユニットに対応するウェイに格納されているかどうかを判定することと、
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインが、前記キャッシュラインがログされていると判定するために利用可能な関連するキャッシュコヒーレンスプロトコル(CCP)状態データを有するかどうかを判定することと
のうちの1つまたは複数を含む、コンピューティングデバイス。 The computing device of claim 1 checks the (N + i) level cache to determine if the data at the memory location has previously been logged for the second processing unit. That is
Determining whether one or more accounting bits are set in the cache line in the (N + i) level cache corresponding to the memory location.
Determining whether the cache line in the (N + i) level cache corresponding to the memory location is stored in the way corresponding to the logged processing unit.
Determining if a cache line in the (N + i) level cache corresponding to the memory location has relevant cache coherence protocol (CCP) state data available to determine that the cache line is logged. A computing device that includes one or more of the things to do.
前記(N+i)レベルキャッシュが(N+1)レベルキャッシュを含むように、iは1であり、
前記コンピューティングデバイスは、前記(N+1)レベルキャッシュのバッキングストアとして構成される(N+2)レベルキャッシュも含み、
前記(N+i)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているかどうかを判定することは、
前記(N+1)レベルキャッシュ内のどのキャッシュラインも前記メモリ位置に対応していないと判定することと、
前記(N+2)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているかどうかを判定することと
を含む、コンピューティングデバイス。 The computing device according to claim 1.
I is 1 so that the (N + i) level cache includes the (N + 1) level cache.
The computing device also includes a (N + 2) level cache configured as a backing store for the (N + 1) level cache.
Checking the (N + i) level cache to determine if the data at the memory location was previously logged for the second processing unit
It is determined that none of the cache lines in the (N + 1) level cache corresponds to the memory position.
A computing device comprising checking the (N + 2) level cache to determine if the data at the memory location was previously logged for the second processing unit.
前記メモリ位置のアドレスをログすることと、
前記メモリ位置のアドレスおよび順序付けデータをログすることと、
キャッシュウェイへの参照をログすることと、
キャッシュウェイへの参照および順序付けデータをログすることと、
前記第2の処理ユニットを前記メモリ位置に対応するキャッシュラインの前の所有者としてログすることと、
前記第2の処理ユニットを参照するキャッシュコヒーレンスプロトコル(CCP)データをログすることと
のうちの1つまたは複数を含む、コンピューティングデバイス。 The computing device of claim 1, with reference to log data previously logged for the second processing unit, the data at the memory location for the first processing unit. To log
To log the address of the memory location and
Logging the address and ordering data of the memory location
Logging references to cashways and
Logging reference and ordering data to the cache way,
Logging the second processing unit as the previous owner of the cache line corresponding to the memory location
A computing device comprising logging cache coherence protocol (CCP) data with reference to the second processing unit.
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内の第2のキャッシュラインを保持しながら、前記メモリ位置に対応する前記第1のNレベルキャッシュ内の第1のキャッシュラインを追い出すことと、
前記第1のNレベルキャッシュへの、前記メモリ位置に格納された前記データも含む後続の流入を検出したことに基づいて、前記後続の流入を、前記第2のキャッシュラインの存在に基づいて参照によってログさせることと
を実行するように前記コンピューティングデバイスをさらに構成する、コンピューティングデバイス。 The computing device according to claim 1, wherein the control logic is at least.
Ejecting the first cache line in the first N-level cache corresponding to the memory location while retaining the second cache line in the (N + i) level cache corresponding to the memory location.
Referencing the subsequent inflow to the first N-level cache based on the presence of the second cache line, based on the detection of subsequent inflows to the first N-level cache, including the data stored in the memory location. A computing device that further configures the computing device to perform and to be logged by.
前記メモリ位置にも対応する前記(N+i)レベルキャッシュ内の第2のキャッシュラインを保持しながら、前記メモリ位置に対応する前記第1のNレベルキャッシュ内の第1のキャッシュラインを追い出すことと、
前記第1の処理ユニットでの追加のコード実行に基づいて、前記第1のNレベルキャッシュへの、前記メモリ位置に格納された前記データも含む後続の流入を検出することと、
前記第1のNレベルキャッシュへの前記後続の流入を検出したことに少なくとも基づいて、かつ、前記第2のキャッシュラインの存在に少なくとも基づいて、前記後続の流入をログする必要がないと判定することと
を実行するように前記コンピューティングデバイスをさらに構成する、コンピューティングデバイス。 The computing device according to claim 1, wherein the control logic is at least.
While holding the second cache line in the (N + i) level cache corresponding to the memory position, the first cache line in the first N level cache corresponding to the memory position is expelled.
Detecting subsequent inflows into the first N-level cache, including the data stored in the memory location, based on additional code execution in the first processing unit.
It is determined that there is no need to log the subsequent inflow, at least based on the detection of the subsequent inflow into the first N-level cache, and at least based on the presence of the second cache line. A computing device that further configures the computing device to do so.
複数のNレベルキャッシュのうちの第1のNレベルキャッシュへの、メモリ位置に格納されたデータを含む流入を検出するステップと、
前記第1のNレベルキャッシュへの前記流入を検出したことに基づいて、前記(N+i)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に第2の処理ユニットのためにログされているかどうかを判定し、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているときに、以前に前記第2の処理ユニットのためにログされたログデータを参照して、前記メモリ位置の前記データを第1の処理ユニットのためにログさせることと、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされていないときに、前記メモリ位置の前記データを前記第1の処理ユニットのために値によってログさせることと
のうちの一方を実行するステップと
を含む、方法。 A method for trace recording based on recording an inflow into a lower level cache with reference to previous log data based on the knowledge of one or more upper level caches, wherein the method is (i). (Ii) Associated with a plurality of processing units, (ii) a plurality of N-level caches, and (iii) two or more of the plurality of N-level caches, and configured as a backing store for the plurality of N-level caches (iii). Implemented in computing devices including N + i) level cache, said method
A step of detecting an inflow containing data stored in a memory location into the first N-level cache among a plurality of N-level caches, and
Based on the detection of the inflow into the first N-level cache, the (N + i) level cache is checked and the data at the memory location is previously logged for the second processing unit. Determine if there is,
When the data in the memory location was previously logged for the second processing unit, reference to the log data previously logged for the second processing unit in the memory location. Logging the data for the first processing unit
Of having the data at the memory location logged by value for the first processing unit when the data at the memory location was not previously logged for the second processing unit. A method that includes steps to perform one.
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインに、1つまたは複数のアカウンティングビットが設定されているかどうかを判定することと、
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインが、ログされた処理ユニットに対応するウェイに格納されているかどうかを判定することと、
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内のキャッシュラインが、前記キャッシュラインがログされていると判定するために利用可能な関連するキャッシュコヒーレンスプロトコル(CCP)状態データを有するかどうかを判定することと
のうちの1つまたは複数を含む、方法。 The method of claim 11 is to check the (N + i) level cache to determine if the data at the memory location has previously been logged for the second processing unit. ,
Determining whether one or more accounting bits are set in the cache line in the (N + i) level cache corresponding to the memory location.
Determining whether the cache line in the (N + i) level cache corresponding to the memory location is stored in the way corresponding to the logged processing unit.
Determining if a cache line in the (N + i) level cache corresponding to the memory location has associated cache coherence protocol (CCP) state data available to determine that the cache line is logged. A method comprising one or more of what to do.
前記(N+i)レベルキャッシュが(N+1)レベルキャッシュを含むように、iは1であり、
前記コンピューティングデバイスは、前記(N+1)レベルキャッシュのバッキングストアとして構成される(N+2)レベルキャッシュも含み、
前記(N+i)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているかどうかを判定することは、
前記(N+1)レベルキャッシュ内のどのキャッシュラインも前記メモリ位置に対応していないと判定することと、
前記(N+2)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているかどうかを判定することと
を含む、方法。 The method according to claim 11.
I is 1 so that the (N + i) level cache includes the (N + 1) level cache.
The computing device also includes a (N + 2) level cache configured as a backing store for the (N + 1) level cache.
Checking the (N + i) level cache to determine if the data at the memory location was previously logged for the second processing unit
It is determined that none of the cache lines in the (N + 1) level cache corresponds to the memory position.
A method comprising checking the (N + 2) level cache to determine if the data at the memory location was previously logged for the second processing unit.
前記メモリ位置のアドレスをログすることと、
前記メモリ位置のアドレスおよび順序付けデータをログすることと、
キャッシュウェイへの参照をログすることと、
キャッシュウェイへの参照および順序付けデータをログすることと、
前記第2の処理ユニットを前記メモリ位置に対応するキャッシュラインの前の所有者としてログすることと、
前記第2の処理ユニットを参照するキャッシュコヒーレンスプロトコル(CCP)データをログすることと
のうちの1つまたは複数を含む、方法。 11. The method of claim 11, wherein the data at the memory location is logged for the first processing unit with reference to the log data previously logged for the second processing unit. That is
To log the address of the memory location and
Logging the address and ordering data of the memory location
Logging references to cashways and
Logging reference and ordering data to the cache way,
Logging the second processing unit as the previous owner of the cache line corresponding to the memory location
A method comprising logging cache coherence protocol (CCP) data with reference to the second processing unit.
前記メモリ位置に対応する前記(N+i)レベルキャッシュ内の第2のキャッシュラインを保持しながら、前記メモリ位置に対応する前記第1のNレベルキャッシュ内の第1のキャッシュラインを追い出すステップと、
前記第1のNレベルキャッシュへの、前記メモリ位置に格納された前記データも含む後続の流入を検出したことに基づいて、前記後続の流入を、前記第2のキャッシュラインの存在に基づいて参照によってログさせるステップと
をさらに含む方法。 The method according to claim 11.
A step of expelling a first cache line in the first N-level cache corresponding to the memory location while holding a second cache line in the (N + i) level cache corresponding to the memory location.
Referencing the subsequent inflow to the first N-level cache based on the presence of the second cache line, based on the detection of subsequent inflows to the first N-level cache, including the data stored in the memory location. How to include more steps to be logged by.
前記メモリ位置にも対応する前記(N+i)レベルキャッシュ内の第2のキャッシュラインを保持しながら、前記メモリ位置に対応する前記第1のNレベルキャッシュ内の第1のキャッシュラインを追い出すステップと、
前記第1の処理ユニットでの追加のコード実行に基づいて、前記第1のNレベルキャッシュへの、前記メモリ位置に格納された前記データも含む後続の流入を検出するステップと、
前記第1のNレベルキャッシュへの前記後続の流入を検出したことに少なくとも基づいて、かつ、前記第2のキャッシュラインの存在に少なくとも基づいて、前記後続の流入をログする必要がないと判定するステップと
をさらに含む方法。 The method according to claim 11.
A step of expelling a first cache line in the first N-level cache corresponding to the memory location while holding a second cache line in the (N + i) level cache corresponding to the memory location.
A step of detecting a subsequent inflow of the first N-level cache, including the data stored in the memory location, based on additional code execution in the first processing unit.
It is determined that there is no need to log the subsequent inflow, at least based on the detection of the subsequent inflow into the first N-level cache, and at least based on the presence of the second cache line. How to include more steps.
複数のNレベルキャッシュのうちの第1のNレベルキャッシュへの、メモリ位置に格納されたデータを含む流入を検出することと、
前記第1のNレベルキャッシュへの前記流入を検出したことに基づいて、前記(N+i)レベルキャッシュをチェックして、前記メモリ位置の前記データが以前に第2の処理ユニットのためにログされているかどうかを判定し、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされているときに、以前に前記第2の処理ユニットのためにログされたログデータを参照して、前記メモリ位置の前記データを第1の処理ユニットのためにログさせることと、
前記メモリ位置の前記データが以前に前記第2の処理ユニットのためにログされていないときに、前記メモリ位置の前記データを前記第1の処理ユニットのために値によってログさせることと
のうちの一方を実行することと
を実行させるコンピュータプログラム。 It is associated with (i) a plurality of processing units, (ii) a plurality of N-level caches, and (iii) two or more of the plurality of N-level caches, and is configured as a backing store for the plurality of N-level caches. For computing devices, including (N + i) level caches, at least,
To detect an inflow containing data stored in a memory location into the first N-level cache of a plurality of N-level caches.
Based on the detection of the inflow into the first N-level cache, the (N + i) level cache is checked and the data at the memory location is previously logged for the second processing unit. Determine if there is,
When the data in the memory location was previously logged for the second processing unit, reference to the log data previously logged for the second processing unit in the memory location. Logging the data for the first processing unit
Of having the data at the memory location logged by value for the first processing unit when the data at the memory location was not previously logged for the second processing unit. A computer program that runs one and the other.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/904,072 | 2018-02-23 | ||
US15/904,072 US10496537B2 (en) | 2018-02-23 | 2018-02-23 | Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache |
PCT/US2019/017737 WO2019164710A1 (en) | 2018-02-23 | 2019-02-13 | Trace recording by logging influxes to a lower-layer cache based on entries in an upper-layer cache |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2021515312A JP2021515312A (en) | 2021-06-17 |
JPWO2019164710A5 true JPWO2019164710A5 (en) | 2022-02-18 |
JP7221979B2 JP7221979B2 (en) | 2023-02-14 |
Family
ID=65520481
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020544520A Active JP7221979B2 (en) | 2018-02-23 | 2019-02-13 | Trace recording by logging entries into the lower tier cache based on entries in the upper tier cache |
Country Status (15)
Country | Link |
---|---|
US (1) | US10496537B2 (en) |
EP (1) | EP3740871B1 (en) |
JP (1) | JP7221979B2 (en) |
KR (1) | KR102645481B1 (en) |
CN (1) | CN111742302A (en) |
AU (1) | AU2019223883B2 (en) |
BR (1) | BR112020013505A2 (en) |
CA (1) | CA3088563A1 (en) |
ES (1) | ES2927911T3 (en) |
IL (1) | IL276652B2 (en) |
MX (1) | MX2020008664A (en) |
PH (1) | PH12020551325A1 (en) |
SG (1) | SG11202007582RA (en) |
WO (1) | WO2019164710A1 (en) |
ZA (1) | ZA202004083B (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10031834B2 (en) | 2016-08-31 | 2018-07-24 | Microsoft Technology Licensing, Llc | Cache-based tracing for time travel debugging and analysis |
US11042469B2 (en) | 2017-08-28 | 2021-06-22 | Microsoft Technology Licensing, Llc | Logging trace data for program code execution at an instruction level |
US10642737B2 (en) | 2018-02-23 | 2020-05-05 | Microsoft Technology Licensing, Llc | Logging cache influxes by request to a higher-level cache |
WO2021061220A1 (en) * | 2019-09-24 | 2021-04-01 | Microsoft Technology Licensing, Llc | Logging trace data for program code execution at an instruction level |
KR20210079637A (en) * | 2019-12-20 | 2021-06-30 | 에스케이하이닉스 주식회사 | Data Storage Apparatus and Operation Method Thereof |
LU101770B1 (en) * | 2020-05-05 | 2021-11-05 | Microsoft Technology Licensing Llc | Memory page markings as logging cues for processor-based execution tracing |
US20220269615A1 (en) * | 2021-02-22 | 2022-08-25 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in system memory |
WO2022177697A1 (en) * | 2021-02-22 | 2022-08-25 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in an upper-level cache |
US11561896B2 (en) | 2021-02-22 | 2023-01-24 | Microsoft Technology Licensing, Llc | Cache-based trace logging using tags in an upper-level cache |
Family Cites Families (82)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4598364A (en) | 1983-06-29 | 1986-07-01 | International Business Machines Corporation | Efficient trace method adaptable to multiprocessors |
WO1993017385A1 (en) | 1992-02-27 | 1993-09-02 | Intel Corporation | Dynamic flow instruction cache memory |
US5905855A (en) | 1997-02-28 | 1999-05-18 | Transmeta Corporation | Method and apparatus for correcting errors in computer systems |
US6009270A (en) | 1997-04-08 | 1999-12-28 | Advanced Micro Devices, Inc. | Trace synchronization in a processor |
US6167536A (en) | 1997-04-08 | 2000-12-26 | Advanced Micro Devices, Inc. | Trace cache for a microprocessor-based device |
US6094729A (en) | 1997-04-08 | 2000-07-25 | Advanced Micro Devices, Inc. | Debug interface including a compact trace record storage |
US5944841A (en) | 1997-04-15 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor with built-in instruction tracing capability |
US6101524A (en) | 1997-10-23 | 2000-08-08 | International Business Machines Corporation | Deterministic replay of multithreaded applications |
US6553564B1 (en) | 1997-12-12 | 2003-04-22 | International Business Machines Corporation | Process and system for merging trace data for primarily interpreted methods |
US6351844B1 (en) | 1998-11-05 | 2002-02-26 | Hewlett-Packard Company | Method for selecting active code traces for translation in a caching dynamic translator |
US6854108B1 (en) | 2000-05-11 | 2005-02-08 | International Business Machines Corporation | Method and apparatus for deterministic replay of java multithreaded programs on multiprocessors |
US7448025B2 (en) | 2000-12-29 | 2008-11-04 | Intel Corporation | Qualification of event detection by thread ID and thread privilege level |
JP2002207613A (en) | 2001-01-12 | 2002-07-26 | Fujitsu Ltd | Device and method for gathering history |
US6634011B1 (en) | 2001-02-15 | 2003-10-14 | Silicon Graphics, Inc. | Method and apparatus for recording program execution in a microprocessor based integrated circuit |
US20020144101A1 (en) | 2001-03-30 | 2002-10-03 | Hong Wang | Caching DAG traces |
US7181728B1 (en) | 2001-04-30 | 2007-02-20 | Mips Technologies, Inc. | User controlled trace records |
US7185234B1 (en) | 2001-04-30 | 2007-02-27 | Mips Technologies, Inc. | Trace control from hardware and software |
US7178133B1 (en) | 2001-04-30 | 2007-02-13 | Mips Technologies, Inc. | Trace control based on a characteristic of a processor's operating state |
US20030079205A1 (en) | 2001-10-22 | 2003-04-24 | Takeshi Miyao | System and method for managing operating systems |
US7051239B2 (en) | 2001-12-28 | 2006-05-23 | Hewlett-Packard Development Company, L.P. | Method and apparatus for efficiently implementing trace and/or logic analysis mechanisms on a processor chip |
US7089400B1 (en) | 2002-08-29 | 2006-08-08 | Advanced Micro Devices, Inc. | Data speculation based on stack-relative addressing patterns |
US20040117690A1 (en) | 2002-12-13 | 2004-06-17 | Andersson Anders J. | Method and apparatus for using a hardware disk controller for storing processor execution trace information on a storage device |
US7284153B2 (en) * | 2003-11-17 | 2007-10-16 | International Business Machines Corporation | Apparatus, method, and system for logging diagnostic information |
US7526757B2 (en) | 2004-01-14 | 2009-04-28 | International Business Machines Corporation | Method and apparatus for maintaining performance monitoring structures in a page table for use in monitoring performance of a computer program |
US20050223364A1 (en) | 2004-03-30 | 2005-10-06 | Peri Ramesh V | Method and apparatus to compact trace in a trace buffer |
US8010337B2 (en) | 2004-09-22 | 2011-08-30 | Microsoft Corporation | Predicting database system performance |
US7447946B2 (en) | 2004-11-05 | 2008-11-04 | Arm Limited | Storage of trace data within a data processing apparatus |
JP4114879B2 (en) | 2005-01-21 | 2008-07-09 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Trace information collection system, trace information collection method, and trace information collection program |
US7640539B2 (en) | 2005-04-12 | 2009-12-29 | International Business Machines Corporation | Instruction profiling using multiple metrics |
US8301868B2 (en) | 2005-09-23 | 2012-10-30 | Intel Corporation | System to profile and optimize user software in a managed run-time environment |
US7877630B1 (en) | 2005-09-28 | 2011-01-25 | Oracle America, Inc. | Trace based rollback of a speculatively updated cache |
US7984281B2 (en) | 2005-10-18 | 2011-07-19 | Qualcomm Incorporated | Shared interrupt controller for a multi-threaded processor |
US9268666B2 (en) | 2005-10-21 | 2016-02-23 | Undo Ltd. | System and method for debugging of computer programs |
US7620938B2 (en) | 2005-10-31 | 2009-11-17 | Microsoft Corporation | Compressed program recording |
US20070106827A1 (en) | 2005-11-08 | 2007-05-10 | Boatright Bryan D | Centralized interrupt controller |
US7461209B2 (en) | 2005-12-06 | 2008-12-02 | International Business Machines Corporation | Transient cache storage with discard function for disposable data |
US20070150881A1 (en) | 2005-12-22 | 2007-06-28 | Motorola, Inc. | Method and system for run-time cache logging |
US20070220361A1 (en) | 2006-02-03 | 2007-09-20 | International Business Machines Corporation | Method and apparatus for guaranteeing memory bandwidth for trace data |
US7958497B1 (en) | 2006-06-07 | 2011-06-07 | Replay Solutions, Inc. | State synchronization in recording and replaying computer programs |
US7676632B2 (en) | 2006-07-18 | 2010-03-09 | Via Technologies, Inc. | Partial cache way locking |
US7472218B2 (en) | 2006-09-08 | 2008-12-30 | International Business Machines Corporation | Assisted trace facility to improve CPU cache performance |
US20080250207A1 (en) | 2006-11-14 | 2008-10-09 | Davis Gordon T | Design structure for cache maintenance |
US20080114964A1 (en) | 2006-11-14 | 2008-05-15 | Davis Gordon T | Apparatus and Method for Cache Maintenance |
US8370806B2 (en) | 2006-11-15 | 2013-02-05 | Qualcomm Incorporated | Non-intrusive, thread-selective, debugging method and system for a multi-thread digital signal processor |
US8261130B2 (en) | 2007-03-02 | 2012-09-04 | Infineon Technologies Ag | Program code trace signature |
US8484516B2 (en) | 2007-04-11 | 2013-07-09 | Qualcomm Incorporated | Inter-thread trace alignment method and system for a multi-threaded processor |
JP5104340B2 (en) | 2007-04-24 | 2012-12-19 | 富士通株式会社 | Computer apparatus and cache recovery method thereof |
US20090037886A1 (en) | 2007-07-30 | 2009-02-05 | Mips Technologies, Inc. | Apparatus and method for evaluating a free-running trace stream |
CN101446909B (en) | 2007-11-30 | 2011-12-28 | 国际商业机器公司 | Method and system for managing task events |
US8078807B2 (en) | 2007-12-27 | 2011-12-13 | Intel Corporation | Accelerating software lookups by using buffered or ephemeral stores |
CN101765093B (en) * | 2008-12-23 | 2013-06-12 | 中兴通讯股份有限公司 | Automatic buffer tracking method of RNC abnormal calling signaling |
US8413122B2 (en) | 2009-02-12 | 2013-04-02 | International Business Machines Corporation | System and method for demonstrating the correctness of an execution trace in concurrent processing environments |
US8402318B2 (en) | 2009-03-24 | 2013-03-19 | The Trustees Of Columbia University In The City Of New York | Systems and methods for recording and replaying application execution |
US8589629B2 (en) | 2009-03-27 | 2013-11-19 | Advanced Micro Devices, Inc. | Method for way allocation and way locking in a cache |
US8140903B2 (en) | 2009-04-16 | 2012-03-20 | International Business Machines Corporation | Hardware process trace facility |
US8423965B2 (en) | 2009-06-23 | 2013-04-16 | Microsoft Corporation | Tracing of data flow |
JP2011013867A (en) | 2009-06-30 | 2011-01-20 | Panasonic Corp | Data processor and performance evaluation analysis system |
US8719796B2 (en) | 2010-01-26 | 2014-05-06 | The Board Of Trustees Of The University Of Illinois | Parametric trace slicing |
US8468501B2 (en) | 2010-04-21 | 2013-06-18 | International Business Machines Corporation | Partial recording of a computer program execution for replay |
US9015441B2 (en) | 2010-04-30 | 2015-04-21 | Microsoft Technology Licensing, Llc | Memory usage scanning |
US8499200B2 (en) | 2010-05-24 | 2013-07-30 | Ncr Corporation | Managing code-tracing data |
US20120042212A1 (en) | 2010-08-10 | 2012-02-16 | Gilbert Laurenti | Mixed Mode Processor Tracing |
US9645913B2 (en) | 2011-08-03 | 2017-05-09 | Daniel Geist | Method and apparatus for debugging programs |
US20130055033A1 (en) | 2011-08-22 | 2013-02-28 | International Business Machines Corporation | Hardware-assisted program trace collection with selectable call-signature capture |
US8584110B2 (en) | 2011-09-30 | 2013-11-12 | International Business Machines Corporation | Execution trace truncation |
US8612650B1 (en) | 2012-03-13 | 2013-12-17 | Western Digital Technologies, Inc. | Virtual extension of buffer to reduce buffer overflow during tracing |
US9304863B2 (en) | 2013-03-15 | 2016-04-05 | International Business Machines Corporation | Transactions for checkpointing and reverse execution |
US9058415B1 (en) | 2013-03-15 | 2015-06-16 | Google Inc. | Counting events using hardware performance counters and annotated instructions |
US9189360B2 (en) | 2013-06-15 | 2015-11-17 | Intel Corporation | Processor that records tracing data in non contiguous system memory slices |
US9086974B2 (en) | 2013-09-26 | 2015-07-21 | International Business Machines Corporation | Centralized management of high-contention cache lines in multi-processor computing environments |
US9535815B2 (en) | 2014-06-04 | 2017-01-03 | Nvidia Corporation | System, method, and computer program product for collecting execution statistics for graphics processing unit workloads |
US9300320B2 (en) | 2014-06-27 | 2016-03-29 | Qualcomm Incorporated | System and method for dictionary-based cache-line level code compression for on-chip memories using gradual bit removal |
US9875173B2 (en) | 2014-06-30 | 2018-01-23 | Microsoft Technology Licensing, Llc | Time travel debugging in managed runtime |
US9361228B2 (en) | 2014-08-05 | 2016-06-07 | Qualcomm Incorporated | Cache line compaction of compressed data segments |
US9588870B2 (en) | 2015-04-06 | 2017-03-07 | Microsoft Technology Licensing, Llc | Time travel debugging for browser components |
CN104881371B (en) * | 2015-05-29 | 2018-02-09 | 清华大学 | Persistence memory transaction handles buffer memory management method and device |
WO2017028908A1 (en) | 2015-08-18 | 2017-02-23 | Telefonaktiebolaget Lm Ericsson (Publ) | Method for observing software execution, debug host and debug target |
US9767237B2 (en) | 2015-11-13 | 2017-09-19 | Mentor Graphics Corporation | Target capture and replay in emulation |
US9569338B1 (en) | 2015-12-02 | 2017-02-14 | International Business Machines Corporation | Fingerprint-initiated trace extraction |
US10031833B2 (en) | 2016-08-31 | 2018-07-24 | Microsoft Technology Licensing, Llc | Cache-based tracing for time travel debugging and analysis |
US10031834B2 (en) | 2016-08-31 | 2018-07-24 | Microsoft Technology Licensing, Llc | Cache-based tracing for time travel debugging and analysis |
US10642737B2 (en) | 2018-02-23 | 2020-05-05 | Microsoft Technology Licensing, Llc | Logging cache influxes by request to a higher-level cache |
-
2018
- 2018-02-23 US US15/904,072 patent/US10496537B2/en active Active
-
2019
- 2019-02-13 JP JP2020544520A patent/JP7221979B2/en active Active
- 2019-02-13 CA CA3088563A patent/CA3088563A1/en active Pending
- 2019-02-13 CN CN201980014858.4A patent/CN111742302A/en active Pending
- 2019-02-13 ES ES19707256T patent/ES2927911T3/en active Active
- 2019-02-13 SG SG11202007582RA patent/SG11202007582RA/en unknown
- 2019-02-13 BR BR112020013505-4A patent/BR112020013505A2/en unknown
- 2019-02-13 MX MX2020008664A patent/MX2020008664A/en unknown
- 2019-02-13 EP EP19707256.4A patent/EP3740871B1/en active Active
- 2019-02-13 KR KR1020207026919A patent/KR102645481B1/en active IP Right Grant
- 2019-02-13 AU AU2019223883A patent/AU2019223883B2/en active Active
- 2019-02-13 WO PCT/US2019/017737 patent/WO2019164710A1/en active Application Filing
-
2020
- 2020-07-03 ZA ZA2020/04083A patent/ZA202004083B/en unknown
- 2020-08-11 IL IL276652A patent/IL276652B2/en unknown
- 2020-08-20 PH PH12020551325A patent/PH12020551325A1/en unknown
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20210351911A1 (en) | Techniques for preventing memory timing attacks | |
JP5430756B2 (en) | Providing state memory in the processor for system management mode | |
JP2007188315A5 (en) | ||
JP2005339561A5 (en) | ||
JP2020534589A5 (en) | ||
JP2020500365A5 (en) | ||
US20090125788A1 (en) | Hardware based memory scrubbing | |
US9880896B2 (en) | Error feedback and logging with memory on-chip error checking and correcting (ECC) | |
US10558569B2 (en) | Cache controller for non-volatile memory | |
US10282250B1 (en) | Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory | |
US8862942B2 (en) | Method of system for detecting abnormal interleavings in concurrent programs | |
JPH0895856A (en) | Computer apparatus with cache memory | |
US9405646B2 (en) | Method and apparatus for injecting errors into memory | |
JP2005182749A (en) | Cache memory and its error correction method | |
JP2013504127A5 (en) | ||
JPWO2019164710A5 (en) | ||
RU2015151131A (en) | LOADING A PARTIAL WIDTH, DEPENDING ON THE MODE, IN PROCESSORS WITH REGISTERS WITH A LARGE NUMBER OF DISCHARGES, METHODS AND SYSTEM | |
US9009548B2 (en) | Memory testing of three dimensional (3D) stacked memory | |
US10216562B2 (en) | Generating diagnostic data | |
US7275202B2 (en) | Method, system and program product for autonomous error recovery for memory devices | |
US7577890B2 (en) | Systems and methods for mitigating latency associated with error detection and correction | |
US11803433B2 (en) | Localization of potential issues to objects | |
CN115576872A (en) | Access detection method and device for multi-level cache | |
US9542318B2 (en) | Temporary cache memory eviction | |
US11593209B2 (en) | Targeted repair of hardware components in a computing device |