JPWO2017038448A1 - Nitride semiconductor device - Google Patents

Abstract

  The nitride semiconductor device according to an embodiment of the present technology includes a first semiconductor layer, an active layer provided on the first semiconductor layer, and light emitted from the active layer provided on the active layer. And a second semiconductor layer having an emission window. At least one recess or first dielectric multilayer film is formed on a side surface of the first semiconductor layer or the second semiconductor layer.

Description

  The present technology relates to, for example, a nitride semiconductor device that emits light in the stacking direction.

  A semiconductor element constituting a surface emitting laser or the like is mounted on a submount or the like in order to discharge heat generated from the element. In mounting, solder is generally used, but it is known that the solder rises due to the wettability of the element. When this rise is large, there is a problem that the solder contacts other than the desired region and current leakage occurs.

  On the other hand, for example, a light emitting device such as a surface emitting laser using a nitride semiconductor as a semiconductor material generally has a lower DBR layer (second reflective layer), a lower spacer layer (second compound semiconductor layer), The active layer, the upper spacer layer (first compound semiconductor layer), the upper DBR layer (first reflective layer), and the contact layer (first electrode) are stacked in this order (for example, see Patent Documents 1 and 2). . In such a light emitting element, since various characteristics thereof are strongly influenced by heat, an attempt has been made to improve heat exhaustion by covering most of the light emitting element with solder having high thermal conductivity. For this reason, there is a problem that leakage failure is likely to occur in conjunction with the solder rising due to the wettability of the element.

JP2015-35541A Japanese Patent Laid-Open No. 2015-35542

  On the other hand, for example, a method of suppressing solder rise by providing a digging or the like in a member (mounted member) in contact with a nitride semiconductor element such as a submount is considered. As described above, when the mounted member is processed, it is difficult to control the solder coating region on the surface of the element, although a certain effect can be obtained with respect to the suppression of the solder rise. Therefore, this method has a problem that a sufficient effect cannot be obtained for improving the exhaust heat efficiency.

  Therefore, it is desirable to provide a nitride semiconductor device that can reduce the occurrence of leakage defects while improving exhaust heat efficiency.

  A nitride semiconductor device according to an embodiment of the present technology includes a first semiconductor layer, an active layer provided on the first semiconductor layer, and a second semiconductor layer provided on the active layer. At least one indentation or dielectric multilayer film is formed on one side surface of the first semiconductor layer and the second semiconductor layer.

  In the nitride semiconductor device according to the embodiment of the present technology, at least one of the first semiconductor layer and the second semiconductor layer having the active layer interposed therebetween has at least one recess or dielectric multilayer film on the side surface. One is formed. By forming a large number of interfaces and dents on the side surface of the element by the dielectric multilayer film, it is possible to control the solder coating region used during mounting.

  According to the nitride semiconductor device of one embodiment of the present technology, a recess or a dielectric multilayer film is formed on one side surface of the first semiconductor layer and the second semiconductor layer with the active layer interposed therebetween. Since at least one of them is formed, it is possible to control the solder covering region used during mounting. Therefore, it is possible to suppress the rise of the solder while increasing the heat exhaust efficiency by the coating of the solder, and to reduce the occurrence of leakage failure. Note that the effect of the present technology is not necessarily limited to the effect described herein, and may be any effect described in the present disclosure.

1 is a cross-sectional view of a surface emitting semiconductor laser according to an embodiment of the present technology. It is a schematic diagram showing the planar shape of the dielectric multilayer film of the semiconductor laser shown in FIG. FIG. 3 is a schematic diagram illustrating an example of a formation position of the dielectric multilayer film illustrated in FIG. 2. It is sectional drawing for demonstrating the manufacturing method of the semiconductor laser shown in FIG. It is sectional drawing for demonstrating the process following FIG. 4A. It is sectional drawing for demonstrating the process following FIG. 4B. It is sectional drawing for demonstrating the process following FIG. 5A. It is sectional drawing of LED which concerns on 2nd Embodiment of this technique. FIG. 10 is an example of a cross-sectional view of a semiconductor laser soldered to a heat sink as Application Example 1; FIG. 10 is an example of a cross-sectional view of a semiconductor laser soldered to a heat sink as Application Example 1; It is an example of sectional drawing of LED soldered to the heat sink as the application example 2. FIG. It is an example of sectional drawing of LED soldered to the heat sink as the application example 2. FIG.

Hereinafter, an embodiment of the present technology will be described in detail with reference to the drawings. The description will be given in the following order.
1. First embodiment (semiconductor laser having a dielectric multilayer film and a recess on a side surface of a semiconductor layer on a substrate side)
1-1. Overall configuration 1-2. Manufacturing method 1-3. Action / Effect Second Embodiment (LED having a dielectric multilayer film and a depression on the side surface of the semiconductor layer on the substrate side)
3. Application examples

<1. First Embodiment>
FIG. 1 illustrates an example of a cross-sectional configuration of a surface-emitting type semiconductor element (semiconductor laser 1) according to the first embodiment of the present technology. The semiconductor laser 1 includes a substrate 11 and a plurality of dielectric multilayer films 41 in contact with the surface S1 of the substrate 11. The plurality of dielectric multilayer films 41 are provided on the substrate 11 at intervals. The semiconductor laser 1 further has a configuration in which the semiconductor layer 20, the insulating film 24, the transparent electrode 32, and the second reflective layer 42 are laminated in this order. Of the plurality of dielectric multilayer films 41, when the dielectric multilayer film 41 facing the second reflective layer 42 is the first reflective layer 41A, the pair of first reflective layer 41A and second reflective layer 42 is a resonator. Function as. The semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are stacked in this order from the substrate 11 side. Each dielectric multilayer film 41 is embedded with the first semiconductor layer 21, and the side surfaces of the one or more dielectric multilayer films 41 are exposed on the side surfaces of the first semiconductor layer 21. That is, at least one dielectric multilayer film 41 is formed on the side surface of the first semiconductor layer 21. Furthermore, at least one recess 21 </ b> A is formed on the side surface of the first semiconductor layer 21. The semiconductor laser 1 has a first electrode 31 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 1 is schematically shown and is different from actual dimensions.

(1-1. Overall configuration)
The substrate 11 is an element forming substrate used for manufacturing the semiconductor layer 20. The substrate 11 is provided in contact with the semiconductor layer 20 (first semiconductor layer 21). As the substrate 11, for example, various substrates such as a GaN substrate, a sapphire substrate, a GaAs substrate, a SiC substrate, an alumina substrate, a ZnS substrate, a ZnO substrate, a LiMgO substrate, a LiGaO ₂ substrate, a MgAl ₂ O ₄ substrate, and an InP substrate are used. it can. In addition, an insulating substrate made of AlN or the like, a semiconductor substrate made of Si, SiC, Ge, or the like, a metal substrate, or an alloy substrate may be used. The thickness of the substrate 11 in the stacking direction (hereinafter simply referred to as thickness), for example, 0.05 mm to 0.5 mm is preferable.

The semiconductor layer 20 has a configuration in which a first semiconductor layer 21, an active layer 22, and a second semiconductor layer 23 are sequentially stacked from the substrate 11 side. The first semiconductor layer 21 and the second semiconductor layer 23 have different conductivity types. For example, the first semiconductor layer 21 is formed of an n-type compound semiconductor, and the second semiconductor layer 23 is formed of a p-type compound semiconductor. Is formed. The first semiconductor layer 21, the active layer 22, and the second semiconductor layer 23 are each composed of a nitride-based compound semiconductor. Specific nitride compound semiconductors include GaN compound semiconductors such as GaN, AlGaN, InGaN, and AlInGaN. In addition, AlN, AlInN, and InN are mentioned. Furthermore, these compound semiconductors may contain boron (B) atoms, thallium (Tl) atoms, arsenic (As) atoms, phosphorus (P) atoms, and antimony (Sb) atoms as desired. . The active layer 22 preferably has a quantum well structure. Specifically, it may have a single quantum well structure (QW structure) or a multiple quantum well structure (MQW structure). The active layer 22 having a quantum well structure has a structure in which at least one well layer and a barrier layer are stacked. As a combination of (a compound semiconductor constituting a well layer and a compound semiconductor constituting a barrier layer), (In _y Ga _(1-y) N, GaN), (In _y Ga _(1-y) N, In _z Ga _(1-z) N) [where y> z], (In _y Ga _{(1- y)} N, AlGaN), (AlGaN / GaN), (AlzGa1 _- zN / AlyGa1 _-yN ) [where y> z].

  The first semiconductor layer 21 and the second semiconductor layer 23 may each be a single structure layer or a multilayer structure layer. Further, it may be a layer having a superlattice structure. Furthermore, it can also be set as the layer provided with the composition gradient layer and the concentration gradient layer.

  The first electrode 31 is provided on the surface opposite to the one surface of the substrate 11 on which the semiconductor layer 20 is formed. The first electrode 31 includes, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium ( It is a single layer film or a laminated film containing at least one kind of metal (including an alloy) of Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and indium (In). It is preferable. Specifically, for example, Ti / Au, Ti / Al, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd, etc. A laminated film is mentioned. Note that the layer before the “/” in the multilayer structure is located closer to the active layer 22 side.

The transparent electrode 32 is provided on the semiconductor layer 20. The transparent electrode 32 is provided in contact with the emission window 24 </ b> W that emits light emitted from the active layer 22 in the second semiconductor layer 23. The transparent electrode 32 is formed of a so-called transparent conductive material having optical transparency. Specific examples of the transparent conductive material include indium-tin oxide (including ITO, Indium TinOxide, Sn-doped In ₂ O ₃ , crystalline ITO, and amorphous ITO), and indium-zinc oxide (IZO, Indium). Zinc Oxide), IFO (F-doped In ₂ O ₃ ), tin oxide (SnO ₂ ), ATO (Sb-doped SnO ₂ ), FTO (F-doped SnO ₂ ), zinc oxide (ZnO, Al-doped ZnO, B-doped ZnO). In addition, a transparent conductive film whose base layer is gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like may be used. However, although the material which comprises the transparent electrode 32 depends on the arrangement state of the 2nd reflective layer 42 and the transparent electrode 32 mentioned later, it is not limited to a transparent conductive material, Palladium (Pd), platinum (Pt ), Nickel (Ni), gold (Au), cobalt (Co), rhodium (Rh), and other metals can also be used. The transparent electrode 32 may be composed of at least one of these materials.

  On the transparent electrode 32, the 2nd electrode 33 for electrically connecting with an external electrode or a circuit is provided. The second electrode 33 is, for example, a single layer film containing at least one metal selected from Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is a laminated film. Specifically, for example, a laminated film of Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, etc. It is done. Although not provided here, a pad electrode may be provided on the first electrode 31 as appropriate. When the first electrode 31 is composed of an Ag layer or an Ag / Pd layer, a cover metal layer (not shown) made of, for example, Ni / TiW / Pd / TiW / Ni is formed on the surface of the first electrode 31. Then, it is preferable to form a pad electrode made of a multilayer film such as Ti / Ni / Au or Ti / Ni / Au / Cr / Au on the cover metal layer.

A current confinement structure is preferably formed between the semiconductor layer 20 (specifically, the second semiconductor layer 23) and the transparent electrode 32. The current confinement structure is configured by an insulating film 24 provided on the second semiconductor layer 23, for example. The insulating film 24 has an opening 24A, which serves as a current injection region in the semiconductor layer 20 (second semiconductor layer 23). At this time, the current injection region in the semiconductor layer 20 (second semiconductor layer 23) corresponds to the emission window 24H. Insulating film 24, for example, it is formed by SiO _X, SiN _X or AlO _X.

  Note that the current confinement structure is not necessarily formed by the insulating film 24. For example, the mesa structure may be formed by etching the second semiconductor layer 23 by a reactive ion etching (RIE) method, or a part of the stacked second semiconductor layers 23. May be partially oxidized from the lateral direction to form a current confinement region. Furthermore, impurities may be ion-implanted into the second semiconductor layer 23 to form a region with reduced conductivity, and these may be combined as appropriate. However, the transparent electrode 32 needs to be electrically connected to a part of the second semiconductor layer 23 through which current flows due to current constriction.

For example, a plurality of dielectric multilayer films 41 are provided in the plane of the substrate 11 and are embedded by the first semiconductor layer 21. A part of the plurality of dielectric multilayer films 41 provided on the substrate 11 has an end face in the same plane as the end face of the semiconductor layer 20 and is exposed on the side face of the semiconductor laser 1. The dielectric multilayer film 41 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN _x , AlN _x , AlGaN, GaN _x , BN _x, etc.) or fluoride. _{Specifically, SiO x, TiO x, NbO} x, ZrO x, TaO x, ZnO x, AlO x, HfO x, SiN x, AlN x , and the like.

The first reflective layer 41A functions as a DBR (Distributed Bragg Reflector) layer. The first reflective layer 41A preferably has a configuration in which two or more types of dielectric films made of dielectric materials having different refractive indexes among the dielectric materials are alternately stacked. Thereby, the light reflection effect is obtained. Examples of the combination of the two kinds of dielectric films include SiO _x / SiN _x , SiO _x / NbO _x , SiO _x / ZrO _x , SiO _x / AlN _{x and the} like. In order to obtain a desired light reflectance, the material, the film thickness, the number of stacked layers, and the like constituting each dielectric film may be appropriately selected. The thickness of each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength λ0 and the refractive index n of the material used at the light emission wavelength λ0. Specifically, an odd multiple of λ0 / (4n) is preferable. For example, in a light emitting device having an emission wavelength λ0 of 410 nm, when the dielectric multilayer film 41 is made of SiO _x / NbO _y , the thickness of each dielectric film is preferably about 40 nm to 70 nm. The number of stacked layers is preferably 5 or more, and more preferably 15 or more. The entire thickness of the dielectric multilayer film 41 is preferably 0.6 μm to 3.0 μm, for example. For example, the dielectric multilayer film 41 is preferably arranged or arranged so as to grow laterally in the [1120] direction.

  As shown in FIG. 2, the planar shape of the dielectric multilayer film 41 is, for example, a lattice (rectangular) shape (A), a polygonal shape including a regular hexagon (B), a circular shape including an ellipse (C), a stripe shape ( D) or an island shape. The cross-sectional shape of the dielectric multilayer film 41 may be rectangular as shown in FIG. 1 or may be formed in a trapezoidal shape. Further, as shown in FIG. 3, a part of the dielectric multilayer film 41 may be missing from the substrate 11. The lack of the dielectric multilayer film 41 is caused by cracking or chipping of the dielectric multilayer film 41 at the time of cutting by cleavage. Further, for example, it is caused by the difference between the linear thermal expansion coefficient of the substrate 11 and the linear thermal expansion coefficient of the dielectric multilayer film 41. The loss of the dielectric multilayer film 41 occurs on the end surface of the substrate 11, thereby forming a recess 21 </ b> A on the side surface of the semiconductor layer 20. Note that the lack of the dielectric multilayer film 41 may be intentionally formed.

The second reflective layer 42 is provided at a position facing the first reflective layer 41 </ b> A with the semiconductor layer 20 in between, specifically, provided on the transparent electrode 32. Similar to the dielectric multilayer film 41, the second reflective layer 42 is made of an oxide or nitride such as Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti (for example, _{, SiN X, AlN X, AlGaN} , and is formed by a GaN _X, BN _X, etc.) or fluorides and the like. The second reflective layer 42, the of the dielectric material, to obtain a high refractive index material such as SiN _x or TaO _x, that is high optical reflectance alternately laminating a low refractive index material such as SiO _x Can do. In order to obtain a desired light reflectance, in addition to the material constituting each dielectric film, the film thickness, the number of stacked layers, and the like may be appropriately selected. The thickness of each dielectric film can be adjusted as appropriate depending on the material used, and is determined by the light emission wavelength λ0 and the refractive index n of the material used at the light emission wavelength λ0. Specifically, an odd multiple of λ0 / (4n) is preferable. For example, in a light emitting device having an emission wavelength λ0 of 410 nm, when the dielectric multilayer film 41 is made of SiO _x / NbO _y , the thickness of each dielectric film is preferably about 40 nm to 70 nm. The number of stacked layers is 2 or more, preferably 2-15. The entire thickness of the dielectric multilayer film 41 is preferably 0.6 μm to 3.0 μm, for example.

(1-2. Manufacturing method)
The semiconductor laser 1 of the present embodiment can be manufactured as follows, for example.

4A to 5B show a method of manufacturing the semiconductor laser 1 in the order of steps. First, as shown in FIG. 4A, a dielectric multilayer film 41X is formed. Specifically, it is formed by laminating, for example, five layers of SiO _x films and SiN _x films alternately on the substrate 11 by using any film forming method such as sputtering, CVD, and vapor deposition. Subsequently, as shown in FIG. 4B, the dielectric multilayer film 41X is selectively etched to form a plurality of dielectric multilayer films 41 whose side surfaces are surrounded by the grooves 41H. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.

Next, as shown in FIG. 5A, the semiconductor layer 20 and the insulating film 24 are formed on the substrate 11 and the dielectric multilayer film 41. Specifically, the dielectric multilayer film 41 is used as a selective growth mask, and the substrate 11 is placed in a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus and heated to a desired temperature. For example, the semiconductor layer 20 including the first semiconductor layer 21 made of n-type GaN and the active layer (light emitting layer) 22, for example, the second semiconductor layer 23 made of p-type GaN, is grown. For growth, trimethylgallium (TMGa) as a Ga source, trimethylaluminum (TMAl) as an Al source, trimethylindium (TMIn) as an In source, silane (SiH ₄ ) as an n-type impurity Si source, and p-type impurity Mg Cyclopentadienylmagnesium (Cp ₂ Mg) is used as a raw material for the above, and ammonia gas (NH ₃ ) is used as the N raw material. Here, for example, the first semiconductor layer 21 is grown to 5 μm, the active layer 22 is grown to 80 nm, and the second semiconductor layer 23 is grown to 100 nm. Subsequently, for example, a SiO ₂ film is formed to a thickness of, for example, 200 nm by using any film formation method such as sputtering, CVD, and vapor deposition, and then selectively etched to form a second current injection region. An insulating film 24 having an opening 24A from which the semiconductor layer 23 is exposed is formed. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used. Here, the area of the current injection region is less than or equal to half of the area of the opposing dielectric multilayer film 41 (first reflective layer 41A), and is, for example, about 25πm ² .

Subsequently, as shown in FIG. 5B, the transparent electrode 32, the second electrode 33, and the second reflective layer 42 are formed. Specifically, for example, an ITO film is formed using any film forming method such as sputtering, CVD, and vapor deposition, and then selectively etched to form a transparent electrode 32 having a desired shape. . For the etching process, wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used. Next, for example, Au, Pt, and Ti are formed in this order by using any film forming method such as sputtering, CVD, and vapor deposition, and then selectively etched to form Ti / Pt only at a desired portion. The second electrode 33 is formed leaving the / Au film. For the etching process, wet etching using acid or the like, dry etching using a reactive ion etching apparatus or the like, lift-off using the PR method, or the like can be used. Subsequently, for example, a dielectric multilayer film in which, for example, five layers of SiO _x films and SiN _x films are alternately formed by using any film formation method such as sputtering, CVD, and vapor deposition is formed, and, for example, selective The second reflective layer 42 having a desired shape is formed by etching. For the etching step, wet etching using hydrofluoric acid or the like, dry etching using an RIE apparatus, or the like can be used.

  Next, after the substrate 11 is ground and polished from the back side, the first electrode 31 is formed. Finally, the element is cut out from the substrate 11 by cleavage or the like. At this time, the dielectric multilayer film 41 is cut out. Thereby, the semiconductor laser 1 shown in FIG. 1 is completed.

  As described above, the semiconductor laser 1 includes a plurality of dielectric multilayer films 41, the first semiconductor layer 21, the active layer 22, the second semiconductor layer 23, the transparent electrode 32, and the second reflective layer 42 on one surface of the substrate 11. The first electrode 31 is formed on the other surface which is laminated in this order and faces one surface of the substrate 11. Either one of the first reflective layer 41A and the second reflective layer 42 (herein, the second reflective layer 42 side) has a current injection region in order to increase the efficiency of current injection into the active layer 22 and reduce the threshold ground current. A current confinement structure (opening 24A of insulating film 24) is provided. In the semiconductor laser 1, the current injected from the first electrode 31 and the transparent electrode 32 is narrowed by the current confinement structure and then injected into the active layer 22. Thereby, light emission by recombination of electrons and holes occurs. This light is reflected by the first reflective layer 41A and the second reflective layer 42, causes laser oscillation at a predetermined wavelength, and is emitted as laser light to the outside via the first reflective layer 41A or the second reflective layer 42. .

(1-3. Action and effect)
As described above, since semiconductor lasers using nitride semiconductors are strongly affected by heat, the semiconductor lasers are generally mounted on a submount or the like using solder to discharge heat. . In addition, since solder has a high thermal conductivity, the heat exhaust efficiency tends to be improved by covering the surface of the semiconductor laser with solder as much as possible. However, in a general semiconductor laser, solder rises due to the wettability of the side surfaces, and this solder rise causes a leak failure.

  As a method for solving this problem, there has been considered a method of providing a digging or the like in a submount or the like for mounting a semiconductor laser to suppress the rise of solder. However, although this method can reduce the solder rise, it is difficult to control the solder coating area on the surface of the semiconductor laser, and it is possible to achieve both suppression of solder rise and high heat exhaust efficiency. It was difficult.

  On the other hand, in the semiconductor laser 1 of the present embodiment, the exposed surface or the recess 21 </ b> A of the dielectric multilayer film 41 is provided on the side surface of the first semiconductor layer 21 on the substrate 11. The exposed surface of the dielectric multilayer film 41 provided on the side surface of the first semiconductor layer 21 has a lower density of dangling bonds than the first semiconductor layer 21, and the side surfaces of the semiconductor laser 1 are formed by laminating these layers. A plurality of interfaces are formed. As a result, it is possible to control the coverage region of the side surface of the semiconductor laser 1 by the solder used during mounting. The recess 21 </ b> A is formed by cracking or chipping at the time of cutting by cleavage, or by missing the dielectric multilayer film 41 due to a difference in linear expansion coefficient between the substrate 11 and the dielectric multilayer film 41. This recess 21A also controls the covering region of the side surface of the semiconductor laser 1 by the solder used at the time of mounting, specifically, the rising of the solder is reduced.

  Therefore, in the semiconductor laser 1 of the present embodiment, it is possible to suppress the rise of the solder while reducing the heat generation efficiency due to the coating of the solder, and to reduce the occurrence of leakage defects.

  Other embodiments will be described below. In addition, about the structure similar to the said 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

<2. Second Embodiment>
FIG. 6 illustrates an example of a cross-sectional configuration of a surface-emitting type semiconductor element (LED2) according to the second embodiment of the present disclosure. The LED 2 includes a substrate 11 and a plurality of dielectric multilayer films 61 in contact with the surface S1 of the substrate 11. The plurality of dielectric multilayer films 61 are provided on the substrate 11 at intervals. The LED 2 further has a configuration in which the semiconductor layer 20, the transparent electrode 52, and the n-type electrode 53 are stacked in this order. Each dielectric multilayer film 61 is embedded with the first semiconductor layer 21 of the semiconductor layer 20, and the side surfaces of the one or more dielectric multilayer films 61 are exposed on the side surfaces of the first semiconductor layer 21. That is, at least one dielectric multilayer film 61 is formed on the side surface of the first semiconductor layer 21. Furthermore, at least one recess 21 </ b> A is formed on the side surface of the first semiconductor layer 21. The LED 2 has a p-type electrode 51 in contact with the surface S2 of the substrate 11 (the surface facing the surface S1). Note that the semiconductor laser 1 in FIG. 6 is schematically shown and is different from actual dimensions.

  The p-type electrode 51 is provided on the surface opposite to the one surface of the substrate 11 on which the semiconductor layer 20 is formed. The p-type electrode 51 includes, for example, gold (Au), silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), Ti (titanium), vanadium (V), tungsten (W), chromium ( It is a single layer film or a laminated film containing at least one kind of metal (including an alloy) of Cr), Al (aluminum), Cu (copper), Zn (zinc), tin (Sn), and indium (In). It is preferable. Examples of the laminated film include Ti / Au, Ti / Al, Ti / Al / Au, Ti / Pt / Au, Ni / Au, Ni / Au / Pt, Ni / Pt, Pd / Pt, Ag / Pd, and the like. Can be mentioned.

The transparent electrode 52 is provided, for example, on the upper surface of the semiconductor layer 20 (the surface of the second semiconductor layer 23), and is formed of a so-called transparent conductive material having optical transparency. Specific examples of the transparent conductive material include indium-tin oxide (including ITO, Indium Tin Oxide, Sn-doped In ₂ O ₃ , crystalline ITO, and amorphous ITO), indium-zinc oxide (IZO, Indium Zinc Oxide), IFO (F-doped In ₂ O ₃ ), tin oxide (SnO ₂ ), ATO (Sb-doped SnO ₂ ), FTO (F-doped SnO ₂ ), zinc oxide (ZnO, Al-doped ZnO) And B-doped ZnO). In addition, a transparent conductive film whose base layer is gallium oxide, titanium oxide, niobium oxide, nickel oxide, or the like may be used.

  The n-type electrode 53 is provided on a part of the transparent electrode 52. The n-type electrode 53 is, for example, a single layer film containing at least one metal selected from Ti (titanium), aluminum (Al), Pt (platinum), Au (gold), Ni (nickel), and Pd (palladium). Or it is preferable that it is a laminated film. Examples of the laminated film include Ti / Pt / Au, Ti / Au, Ti / Pd / Au, Ti / Pd / Au, Ti / Ni / Au, Ti / Ni / Au / Cr / Au, and the like.

Similar to the dielectric multilayer film 41 in the above-described embodiment, a plurality of dielectric multilayer films 61 are provided, for example, in the plane of the substrate 11 and are embedded with the first semiconductor layer 21. The dielectric multilayer film 61 has a function of reflecting the light emitted from the active layer 22 to the transparent electrode 52 side. A part of the plurality of dielectric multilayer films 61 provided on the substrate 11 has the same end surface as the semiconductor layer 20 and is exposed on the side surface of the LED 2. The dielectric multilayer film 61 includes, for example, Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, and other oxides and nitrides (for example, SiN _x , AlN _x , AlGaN, GaN _x , BN _x, etc.) or fluoride. _{Specifically, SiO x, TiO x, NbO} x, ZrO x, TaO x, ZnO x, AlO x, HfO x, SiN x, AlN x , and the like.

The dielectric multilayer film 61 is not necessarily required to alternately stack two or more kinds of dielectric films made of dielectric materials having different refractive indexes among the above-described dielectric materials. For example, SiN _x , TaO _x, etc. The light extraction efficiency is improved by alternately stacking a high refractive index material and a low refractive index material such as SiO _x . Specific combinations of dielectric materials include, for example, SiO _x / NbO _x , SiO _x / ZrO _x , SiO _x / AlN _x in addition to SiO _x / SiN _x . The thickness of each dielectric film is preferably about 40 nm to 70 nm. The number of stacked layers is preferably 5 or more, and more preferably 15 or more. The entire thickness of the dielectric multilayer film 61 is preferably 0.6 μm to 3.0 μm, for example. For example, the dielectric multilayer film 61 is preferably arranged or arranged so as to grow laterally in the [1120] direction.

  The planar shape of the dielectric multilayer film 61 is formed in, for example, a lattice (rectangular) shape, a polygonal shape including a regular hexagon, a circular shape including an ellipse, a stripe shape, or an island shape, as in the above embodiment. The cross-sectional shape of the dielectric multilayer film 61 may be rectangular as shown in FIG. 6, or may be formed in a trapezoidal shape.

  The LED 2 can be manufactured, for example, as follows using the same method as in the above embodiment. First, similarly to the above embodiment, after forming the dielectric multilayer film 61 and the semiconductor layer 20 on the substrate 11, the transparent electrode 52 and the n-type electrode 53 are formed. Specifically, for example, ITO is formed using any film forming method such as sputtering, CVD, and vapor deposition, and then selectively etched to form the transparent electrode 52 having a desired shape. For the etching process, wet etching using hydrochloric acid or the like, dry etching using a reactive ion etching apparatus, or the like can be used. Next, for example, Au, Pt, and Ti are formed in this order by using any film forming method such as sputtering, CVD, and vapor deposition, and then Ti / Pt / only in a desired portion by PR process and etching process. The n-type electrode 53 is formed leaving the Au film. For the etching process, wet etching using acid or the like, dry etching using a reactive ion etching apparatus or the like, lift-off using the PR method, or the like can be used.

  Subsequently, the substrate 11 is ground and polished from the back side, and then the p-type electrode 51 is formed. Finally, the element is cut out from the substrate 11 by cleavage or the like. At this time, the LED 2 shown in FIG. 6 is completed by cutting out across the dielectric multilayer film 61.

<3. Application example>
(Application example 1)
7A and 7B show the semiconductor laser 1 according to the first embodiment mounted on a heat sink. Here, the structure of the semiconductor laser 1 is shown in a simplified manner. The semiconductor laser 1 shown in FIG. 7A is mounted on a heat sink 101 via a solder 102, and a bonding wire 104 is connected to the second electrode 33 via a solder 103. The semiconductor laser 1 shown in FIG. 7B is mounted on a heat sink 101 via a solder 102 and a bonding wire 104 is connected to the first electrode 31 via a solder 103. In the case of junction down mounting, since the laser light is emitted from the substrate 11 side, the first electrode 31 is provided with an opening 31A, and this opening 31A serves as an emission window. As described above, in the semiconductor laser 1 of the first embodiment, the rise of the solder 102 when the junction is mounted and the fall of the solder 103 when the junction is down are mounted. This can be prevented by the one or more dielectric multilayer films 41 and the one or more recesses 21A exposed to the surface.

(Application example 2)
8A and 8B show the LED 2 in the second embodiment mounted on a heat sink. In addition, the structure of LED2 is simplified and shown here. The LED 2 shown in FIG. 8A is mounted on the heat sink 101 via the solder 102, and the bonding wire 104 is connected to the second electrode 33 via the solder 103. The LED 2 shown in FIG. 8B is mounted on the heat sink 101 via the solder 102 and the bonding wire 104 is connected to the p-type electrode 51 via the solder 103. In the case of junction down mounting, since the laser beam is emitted from the substrate 11 side, the p-type electrode 51 is provided with an opening 51A, and this opening 31A serves as an emission window. As described above, in the LED 2 according to the second embodiment, as described above, in the semiconductor laser 1 according to the first embodiment, the rise of the solder 102 when the junction is mounted is changed. It is possible to prevent the solder 103 from falling down by the one or more dielectric multilayer films 61 and the one or more recesses 21 </ b> A exposed on the respective side surfaces of the semiconductor layer 20.

  Although the present technology has been described with the first and second embodiments and application examples, the present technology is not limited to the above-described embodiments and the like, and various modifications can be made. For example, in the first and second embodiments, in the semiconductor laser 1 (or LED 2), both the dielectric multilayer film 41 (or the dielectric multilayer film 61) and the recess 21A are formed on the side surfaces of the semiconductor layer 20, respectively. However, for example, only the recess 21A or only the dielectric multilayer film 41 (or the dielectric multilayer film 61) may be provided.

  In addition, the effect described in this specification is an illustration to the last, and is not limited to this, There may exist another effect.

In addition, this technique can also take the following structures.
(1)
A first semiconductor layer;
An active layer provided on the first semiconductor layer;
A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
A nitride semiconductor device, wherein at least one recess or a first dielectric multilayer film is formed on a side surface of the first semiconductor layer or the second semiconductor layer.
(2)
An element formation substrate of the first semiconductor layer provided in contact with the first semiconductor layer;
The nitride semiconductor device according to (1), wherein at least one of the recess or the first dielectric multilayer film is formed on a side surface of the first semiconductor layer.
(3)
The nitride semiconductor device according to (2), wherein one or a plurality of the first dielectric multilayer films are embedded in the first semiconductor layer.
(4)
A second dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. The nitride semiconductor device according to (3), further comprising a body multilayer film.
(5)
The nitride semiconductor device according to any one of (1) to (4), wherein a plurality of the first dielectric multilayer films are exposed on each side surface of the first semiconductor layer.
(6)
The nitride semiconductor device according to any one of (1) to (5), wherein a plurality of the recesses are formed on each side surface of the first semiconductor layer.
(7)
The nitride semiconductor device according to any one of (1) to (6), wherein the first semiconductor layer, the active layer, and the second semiconductor layer are formed of a GaN-based compound semiconductor.
(8)
The element formation substrate is any one of (2) to (7), which is any one of a gallium nitride (GaN) substrate, an indium gallium nitride (InGaN) substrate, a sapphire substrate, and a silicon (Si) substrate. Nitride semiconductor device.

  This application claims priority on the basis of Japanese Patent Application No. 2015-172749 filed on September 2, 2015 at the Japan Patent Office. The entire contents of this application are hereby incorporated by reference. Incorporated into.

  Those skilled in the art will envision various modifications, combinations, subcombinations, and changes, depending on design requirements and other factors, which are within the scope of the appended claims and their equivalents. It is understood that

Claims (8)

A first semiconductor layer;
An active layer provided on the first semiconductor layer;
A second semiconductor layer provided on the active layer and having an emission window for emitting light emitted from the active layer;
A nitride semiconductor device, wherein at least one recess or a first dielectric multilayer film is formed on a side surface of the first semiconductor layer or the second semiconductor layer. An element formation substrate of the first semiconductor layer provided in contact with the first semiconductor layer;
The nitride semiconductor device according to claim 1, wherein at least one of the recess or the first dielectric multilayer film is formed on a side surface of the first semiconductor layer. The nitride semiconductor device according to claim 2, wherein one or a plurality of the first dielectric multilayer films are embedded in the first semiconductor layer.   A second dielectric provided at a position facing one of the first dielectric multilayer films embedded in the first semiconductor layer with the first semiconductor layer, the active layer, and the second semiconductor layer in between. The nitride semiconductor device according to claim 3, further comprising a body multilayer film.   The nitride semiconductor device according to claim 1, wherein a plurality of the first dielectric multilayer films are exposed on each side surface of the first semiconductor layer.   The nitride semiconductor device according to claim 1, wherein a plurality of the recesses are formed on each side surface of the first semiconductor layer.   2. The nitride semiconductor device according to claim 1, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are made of a GaN-based compound semiconductor.   The nitride semiconductor device according to claim 2, wherein the device formation substrate is any one of a gallium nitride (GaN) substrate, an indium gallium nitride (InGaN) substrate, a sapphire substrate, and a silicon (Si) substrate.

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