JPWO2014141476A1 - Programmable display, its program - Google Patents

Abstract

The shared memory (55) stores an access destination related to item display by the item processing unit (62) and the like, and an access destination related to logic processing by the logic processing unit (64) and the like. The rating judgment processing unit (70) judges the upgrade of each access destination related to the logic processing stored in the shared memory (55). The optimum command generation unit (69) generates the optimum command list (54) using not only the access destination related to the item display but also the upgraded access destination.

Description

  The present invention relates to a programmable display.

  In general, a programmable display is connected to various connected devices such as a PLC main body and a temperature control device, and items such as numerical displays and lamps for displaying the status of these connected devices, and for users to give arbitrary instructions. Displays an image of items such as switches. An item is also called a screen component or the like. Usually, images of a plurality of screen components (items) are displayed on the screen of the programmable display (referred to as an operation display screen).

  Data for displaying such an operation display screen (screen) (called screen data etc.) is created in advance by a developer or the like in a support device (not shown) and downloaded from the support device to a programmable display. Has been.

  The screen data includes, for each item, an image of the item (switch image, lamp image; or image identification ID, etc.), display position coordinates, and an address (assignment memory) of a predetermined area of an external memory to be described later. Address) and the like are included. In addition, some programs may be included.

  Each of the items is for displaying the state of the component or accepting an ON / OFF instruction for the component corresponding to an arbitrary component of an arbitrary connected device, for example. For example, in the case of an item that displays the temperature measurement value of the temperature control device as a numerical value, the current temperature is displayed as a numerical value as needed.

  Display control related to the various items in the programmable display is realized, for example, by periodically executing predetermined processing for each item. Predetermined processing refers to, for example, reading stored data in the predetermined area (area of allocated memory address) of a memory device (external memory) in the connected device, and using this read stored data ("acquired data") Based on this, the display content of the item is determined and displayed. The connected device updates the stored data in a predetermined area of the external memory as needed (for example, the temperature measurement value is updated as needed in the temperature control device).

  Further, the data read from the external memory is temporarily stored in a predetermined area of a memory device (referred to as internal memory) in the programmable display, and the display contents of the item are determined and displayed based on the stored data. There is also a configuration.

  In the case of this example, the process of reading the data stored in the external memory and storing it in the internal memory is executed, for example, periodically by a predetermined functional unit (here, a communication unit not shown) of the programmable display. The communication unit communicates with various connected devices such as the PLC main body and the temperature control device, for example, acquires data stored in a predetermined storage area of the external memory in the connected device, and stores the data in the internal device Overwrite and store in a predetermined area of memory. And the function part (it shall be called an item process part) which performs the display control which concerns on the said various items in a programmable display controls an item display content by accessing an internal memory regularly.

  In the support device, images of various items are stored in advance. For example, item images of various designs are created in advance for each item type (switch, lamp, meter, etc.) and stored in the storage unit of the support apparatus.

  For the item image, for example, a plurality of types of switch images (for example, for ON and OFF; switch ON image and switch OFF image) are created and registered in advance. Similarly, a plurality of types of lamp images (for example, for ON and OFF; lamp ON image and lamp OFF image) are created and registered in advance.

  A developer or the like selects and arranges an item by arranging the item image related to an arbitrary item at a desired position on the screen. Further, not only the arrangement of items but also the operation of setting the allocated memory address for each arranged item is performed.

21 and 22 are functional block diagrams (1/2) and (2/2) of a conventional programmable display. In the following description, “FIG. 21” and the like will be described without particular distinction.
A conventional programmable display 200 includes a CPU 211, a RAM 213, a graphic controller 215, a display 219, and the like, and further includes a non-illustrated nonvolatile storage device (flash memory or the like). The storage device stores screen data 222, predetermined application programs, and the like.

  When the CPU 211 executes the predetermined application program, for example, various processing function units shown in dotted lines in FIG. That is, the item generation unit 261, the item processing unit 262, the communication processing unit 263 (263-1, 263-2, etc.), the logic processing unit 264, the item processing schedule unit 265, the shared memory generation processing unit 266, the logic processing schedule shown in the figure. The processing functions of various processing function units such as the unit 267, the logic command generation unit 268, and the optimum command generation unit 269 are realized.

The item generation unit 261 generates an item list 251 based on the screen data 222 and the like. This is generated, for example, by copying a part of the screen data 222.
The shared memory generation processing unit 266 stores data corresponding to the item list 251 generated by the item generation unit 261 in the shared memory 255. In other words, the data stored in the shared memory 255 is updated.

  The shared memory 255 stores the “acquired data” corresponding to each item in the item list 251. The stored content of this “acquired data” is updated by the communication processing unit 263.

  Each communication processing unit 263 communicates with each connected device 4 via the communication line 6 to acquire data stored in a predetermined area (allocated memory area) of the external memory. Then, this “acquired data” is overwritten and stored in the corresponding area of the shared memory 255.

The communication processing unit 263 performs a process of acquiring the stored data in the allocated memory area based on the optimum command list 254.
The optimal command list 254 is generated by the optimal command generation unit 269 based on the shared memory 255. This is to generate an access destination so that access destinations (allocated memory areas) for each item stored in the shared memory 255 are accessed collectively.

  The item processing unit 262 is called, for example, periodically (cyclically) by the item processing scheduling unit 265, and is related to updating the display contents of each item based on the data stored in the shared memory 255 or the like. Execute the process.

The above is mainly the existing processing function units and data related to the determination / update processing (refresh processing) of the display contents of each item on the display operation screen.
Here, in the programmable display, not only the cyclic refresh process described above but also a logic process by a logic program arbitrarily created by the user (for example, some program using an if-then-else statement, etc.) is performed. There is. During this logic processing, it may be necessary to obtain stored data of an arbitrary access destination (an arbitrary storage area of an arbitrary external memory in an arbitrary connected device) irregularly (suddenly).

The processing function units related to the logic processing as described above are the logic processing unit 264, the logic processing scheduling unit 267, the logic command generation unit 268, and the like.
The logic command generation unit 268 generates a logic command list 252. The logic command list 252 stores, for example, the above-mentioned arbitrary access destination, processing execution conditions (branch conditions, etc.) according to the stored data of the access destination.

  The logic processing unit 264 performs data acquisition processing according to the logic command list 252 under the schedule management by the logic processing scheduling unit 267. For example, the access destination stored in the logic command list 252 is stored in the shared memory 255 and a command including the access destination is stored in the command list (FIFO) 253.

  Here, the logic processing unit 264 often enters a standby state until data acquisition. For example, when acquiring data related to an If statement, it is not possible to know whether to execute then or else unless data is acquired.

  When one or more commands are stored in the command list 253, for example, the communication processing unit 263 also retrieves the top command and performs processing for accessing the access destination included in the command. Then, the acquired data from the access destination is stored in the shared memory 255 and the logic processing unit 264 is notified of the completion of data acquisition.

Receiving this notification, the logic processing unit 264 acquires the stored data in the shared memory 255, and resumes the logic processing that has been in the standby state.
Further, for example, conventional techniques described in Patent Documents 1 and 2 are known.

The invention of Patent Document 1 has the following steps.
・ Memory data reading process to read data from external device memory periodically;
Read data for adjusting the memory data length read by the read command so that the memory data read process is completed with one read command within a predetermined time when the memory data is read in the memory data read step Length adjustment process;
In the invention of Patent Document 2, when reading the memory data of the externally connected device, the memory device storing the memory data, the memory address, and the size of the memory data read from the memory address are respectively read in the read command. The present invention relates to a method for optimizing communication commands in an electronic device in which only one is set to execute reading.

The invention of Patent Document 2 includes the same data group classification step, a first time calculation step, a second time calculation step, a communication time comparison step, a memory data reading step, and the like.
In the same data group classification step, memory data is classified for each externally connected device and each memory device, and classified into memory data groups of the same classification.
In the first time calculation step, the memory data group of the same classification is connected with a plurality of desired memory data of the memory data group and read by one execution of the read command. In this case, the connection data reading communication time is calculated. This is calculated from the communication speed of the externally connected device having the memory data group, the transmission time of the read command, and the reception time of the desired memory data corresponding to the read command;
The second time calculating step reads the memory data group of the same classification, by executing the read command a plurality of times without connecting a plurality of desired memory data of the memory data group. The unconnected data read communication time when performing is calculated. This is calculated from the communication speed of the externally connected device having the memory data group, the transmission time of the read command, and the reception time of the desired memory data corresponding to the read command.
The communication time comparison step compares the linked data read communication time with the unlinked data read communication time.
In the memory data reading step, in the comparison of the communication times, when the linked data read communication time is faster than the unlinked data read communication time, the desired memory data is linked and one read command is executed. Read by execution. Further, when the unconnected data read communication time is faster than the connected data read communication time, reading is performed by executing the read command a plurality of times without connecting the desired memory data.

In Patent Documents 1 and 2, for example, there are two access destination addresses, so that two communication is required, and the two addresses are connected so that one communication is sufficient. It is disclosed. For example, FIG. 6 of Patent Document 2 discloses that data of addresses “X0000 to X0010” are collectively acquired by one communication by linking addresses “X0000” and “x0010”. Yes. Further, it is disclosed that the data between these two addresses is data that is discarded after being read at once.
JP 2009-54055 A JP 2009-54056 A

  As described above, conventionally, for example, the logic processing unit 264 acquires data from an arbitrary access destination (an arbitrary storage area of an arbitrary external memory in an arbitrary connected device 4) with execution of an arbitrary logic process. When it becomes necessary to do so, it will be as follows.

After a command for data acquisition from the access destination is stored in the command list 253, the command list 253 is in a standby state until data acquisition.
Accordingly, in some cases, the standby time is lengthened, and the processing efficiency is lowered.

  In addition, the communication processing unit 263 needs to perform communication with the connection device 4 via the communication line 6 for the data acquisition process from the external memory, and normally, a process involving such communication with the outside is required. Takes more time than internal processing. The communication processing unit 263 performs not only the cyclic access process associated with the refresh process but also the access process associated with the logic process as the external memory access process associated with such communication. In particular, the access process associated with the logic process occurs irregularly (suddenly), and the access process is executed each time.

  For this reason, when the frequency of external memory access processing accompanying logic processing is high (for example, in a situation / setting in which the logic processing unit 264 frequently operates), the processing load of the communication processing unit 263 increases and processing time is required. It becomes a state. As a result, both operations (refresh processing and logic processing) may be extremely slow (bottleneck).

  As described above, there is a problem that the refresh process and / or the logic process may be slowed down particularly when the frequency of external memory access accompanying the execution of the logic process is high.

  An object of the present invention relates to a programmable display that performs external memory access related to refresh processing of item display on a display screen and external memory access associated with execution of logic processing, and the frequency of external memory access associated with execution of logic processing is high. It is to provide a programmable display, a program, and the like that can prevent the operation from slowing down even when a situation occurs.

The programmable display of this invention is a programmable display connected to arbitrary connection apparatuses, Comprising: For example, it has the following means.
Item information storage means for storing access information indicating each access destination corresponding to each item on the display screen;
First data acquisition means for periodically acquiring data from each access destination in the connected device based on the access information and storing it in an internal memory;
-Arbitrary logic processing is executed, and when an access processing to an irregular access destination that is an access destination accompanying the logic processing occurs, it is determined whether or not the irregular access destination is integrated into the access information. And logic processing execution means for acquiring data corresponding to the irregular access destination from the internal memory when the irregular access destination is integrated with the access information;
A rating means that sets the irregular access destination whose access frequency is equal to or higher than a predetermined first threshold every time a predetermined period elapses as an upper-level access destination;
Integration means for integrating the irregular access destination, which is the above-mentioned access status, into the access information;

It is a schematic block diagram of the whole system containing the programmable display 1 of this example. It is a structural example of the programmable display of this example. It is a figure which shows the software structure of this system. It is a processing function figure (1/2) of the programmable display 1 of this example. It is a processing function figure (2/2) of the programmable display 1 of this example. It is a flowchart figure (1/2) of the external memory access process of a communication process part. It is a flowchart figure (2/2) of the external memory access process of a communication process part. It is a process flowchart figure of an item process part. It is a process flowchart figure of a shared memory production | generation process part. It is a processing flowchart figure (1/2) of a logic processing part. It is a processing flowchart figure (2/2) of a logic processing part. It is a processing flowchart figure (1/2) of the external memory access process regarding a logic process. It is a processing flowchart figure (2/2) of the external memory access process regarding a logic process. It is a process flowchart figure (1/2) of a rating determination process part. It is a process flowchart figure (2/2) of a rating determination process part. (A) is a data structure example of a shared memory, (b) is a specific example of a cyclic access memory list. (A) is an example of memory information, (b) is a data block diagram of an item list. It is a specific example of a logic command list. It is an example of the data structure of a command. It is another processing function figure of the programmable display of this example. It is a functional block diagram (1/2) of the conventional programmable display. It is a functional block diagram (2/2) of the conventional programmable display.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic configuration diagram of the entire system including the programmable display 1 of this example.
The programmable controller system shown in FIG. 1 includes various connection devices 4 and a programmable display 1 that is connected to the various connection devices 4 via a communication line 6. Furthermore, the structure by which the programmable display 1 was connected to the drawing editor apparatus 5 (support apparatus) via the communication line 3 may be sufficient. The programmable display 1 is provided with a plurality of communication interfaces 2 (communication ports), and is connected to various connection devices 4 and the drawing editor device 5 by the communication line 3 / communication line 6 connected to each communication interface 2. ing.

  However, the drawing editor device 5 does not necessarily need to be connected to the programmable display device 1 (only an example is shown). For example, when the screen data is installed in the programmable display device 1, the drawing editor device 5 may be connected to the programmable display device 1. As a result, screen data or the like created by the drawing editor device 5 is downloaded from the drawing editor device 5 to the programmable display device 1 via the communication line 3. Of course, the present invention is not limited to this example.

  In addition, instead of downloading via the communication line 3, the screen data or the like may be passed to the programmable display 1 via a portable recording medium (not shown) such as a memory card. In any case, basically, screen data created / updated by the drawing editor device 5 is stored in the programmable display device 1. And in the programmable display 1, the said operation display screen is displayed based on this screen data.

  Or the programmable display 1 may perform the arbitrary logic processes (logic program) mentioned above. This technique basically improves the processing efficiency in the programmable display device 1 that also executes such logic processing, thereby solving the above-described problems (problems).

In the following description, the drawing editor device 5 may be referred to as the support device 5.
FIG. 2 is a hardware configuration example of the programmable display device 1 of this example.
The illustrated programmable display 1 includes a display operation control device 10, a touch panel 18, a display 19, the communication interface 2, and the like.

  The display operation control device 10 includes a CPU 11, a ROM 12 (flash memory or the like), a RAM 13, a communication controller 14, a graphic controller 15, a touch panel controller 16, and the like, which are connected to a bus 17.

  The CPU 11 is a central processing unit (arithmetic processor) that controls the entire display operation control device 10. The CPU 11 performs a predetermined calculation operation (processing) by executing a program (for example, a main body program 21 described later) stored in the ROM 12 in advance. The predetermined process is, for example, a process of cyclically updating the display contents for each item on the operation display screen (the refresh process). For this purpose, an access process to the external memory corresponding to each item (a process for acquiring stored data in the allocated memory area of each item) is performed. Then, screen display control based on the “acquired data” is performed. These processes are conventional techniques as described above.

  Further, here, the main body program 21 includes a program (referred to as a logic program) arbitrarily created by a user or the like. There are various types of processing (logic processing) by the logic program, but there are cases where processing for accessing the external memory is included. As described above, this logic processing itself exists even in the past. As described above, the logic process affects the refresh process, causing a problem that both the refresh process and the logic process take time.

In addition, the calculation results associated with the execution of the main body program 21 are stored in, for example, the RAM 13 or the ROM 12.
The ROM 12 stores screen data (screen data 22 to be described later) described in the background art. As described above, the screen data 22 includes, for example, data related to display such as the display position coordinates and size for each item such as the above-described switch and lamp, and memory such as the allocated memory address (allocated memory area). It has data related to access. The screen data 22 includes an image of each item (or an identification ID of the item image).

  The processing of the CPU 11 using the main body program 21 and the like includes processing for acquiring “stored data in the allocated memory area for each item” as described above. This “acquired data” is temporarily stored, for example, in the shared memory 55 described later. The shared memory 55 may be a part of the storage area of the RAM 13 or the ROM 12, or may be another memory (not shown).

  Further, display target data based on the screen data, the acquired data, and the like are developed (drawn) on, for example, the RAM 13 (or a video RAM (not shown)) by the processing of the CPU 11. Based on this drawing, the graphic controller 15 displays the above-described operation display screen on the display 19.

  Conventionally, the screen data 22 includes, for each item, for example, two types of item images for ON and OFF. On the programmable display 1 side, for example, if the acquired data is “0”, the lamp extinguished image becomes the display target data (for example, drawn on the video RAM). ).

  The display 19 is composed of, for example, a liquid crystal panel, and a touch panel 18 is provided so as to overlap the liquid crystal panel. Conventionally, on the display 19, an operation display screen is basically displayed in which item images of a plurality of items are arranged at predetermined positions.

  Further, the communication controller 14 performs communication (data transmission / reception and the like) with the connection device 4 and the drawing editor device 5 such as a PLC main body (not shown), a temperature control device, and the like via the communication interface 2.

  The detection result of the pressing operation (touch) position on the touch panel 18 by an operator or the like is taken into the CPU 11 or the like via the touch panel controller 16 and analyzed. For example, analysis is performed based on the display position coordinates and size data of each item. For example, when an operator or the like touches the display position of the image of the switch, the CPU 11 or the like analyzes that an operation on the switch has been performed.

FIG. 3 shows a software configuration diagram of the system.
In the programmable display 1, various programs / data such as a main body program 21, screen data 22, and communication program 23 are stored in, for example, the ROM 12 (flash memory or the like). The CPU 11 reads / executes / references these programs / data, etc., thereby performing display control of the operation display screen for the programmable display.

  This operation display screen is composed of the above-described numerical display, image display of various items such as lamps, switches, etc., as in the past, and the display content of each item image is updated as necessary, for example, reflecting the above “acquired data” Is done.

  Basically, the operation display screen is displayed by the CPU 11 performing processing based on the main body program 21 and the screen data 22. The display contents of each screen component on this operation display screen (numerical display such as temperature, lighting / extinguishing of lamp, etc.) are the results of communication with each connected device 4 by the communication program 23 (such as “acquired data”). Based on the above, it is updated as needed. Further, the main body program 21 includes the logic program, and the CPU 11 also executes an arbitrary process created by the user by executing the logic program.

  The screen data 22 is obtained by, for example, downloading a part or all of the screen data file 32 arbitrarily created in advance on the drawing editor device 5 side to the programmable display 1 and storing it. It should be noted that the screen data file 32 and the screen data 22 may be referred to as screen data 22 without being particularly distinguished.

  The communication program 23 is also a part of the communication program file 33 stored in advance on the drawing editor device 5 side, for example, downloaded to the programmable display device 1 and stored.

  As described above, basically, the CPU 11 performs display control of the operation display screen based on the main body program 21, screen data 22, and “acquired data” from the external memory. For example, regarding an item such as a numerical display or a lamp, data is periodically read from the allocated memory area of the item, and the display content of the item is updated based on the read data. Alternatively, for example, regarding an item such as a switch, when a user touches a desired switch on the operation display screen (when an ON / OFF operation is performed), switch ON image display / switch OFF image display is performed.

  The CPU 11 also controls the connection device 4 according to the switch operation. For example, the data stored in the allocated memory area corresponding to the switch (such as a flag indicating ON / OFF of the switch) is updated according to the switch operation. As a result, a controller (not shown) or the like on the connected device 4 side performs an operation corresponding to this flag.

  As already described in the related art, the external memory is a memory device included in the connection device 4 and is a memory device in which memory allocation of each item is performed. As described above, the display content of each item is determined and updated based on the stored data in the allocated memory area.

  As described above, there is a configuration example in which the read data from the allocated memory area is temporarily stored in the internal memory in the programmable display 1, and item display control is performed based on this.

  In this example, data is periodically read out from a predetermined storage area of a memory device (external memory) in the connection device 4 by each communication processing unit 63, which will be described later, and this read data (the above-mentioned “acquired data”) Is stored in the internal memory (shared memory 55 described later). Then, for example, the item processing unit 62 described later performs display control of the operation display screen based on data stored in the internal memory. As a result, the display content of the operation display screen reflects the content of the current stored data in the allocated memory area corresponding to each item (the display content corresponds to the current state of the control target, etc.).

  The drawing editor 31 of the support device 5 has a function of supporting a developer or the like to create a desired screen data file 32. The support device 5 also has a function of downloading any one or more communication programs from the communication program file 33 which is a group of various communication programs stored in advance to the programmable display device 1 and storing it as the communication program 23. . However, these functions of the support device 5 are existing functions and will not be described further here.

  Note that the drawing editor device 5 is, for example, a personal computer or the like, and has a general-purpose computer configuration (CPU, storage unit (hard disk, memory, etc.), communication unit, operation unit (mouse, etc.), display) although not particularly shown. Have. The CPU executes an application program stored in advance in the storage unit, thereby realizing the existing function.

4 and 5 are processing function diagrams (1/2) and (2/2) of the programmable display device 1 of this example. In the following description, “FIG. 4 etc.” and the like are not particularly distinguished.
The programmable display 1 stores screen data 22 and the like.

  When the CPU 11 executes a predetermined program (for example, the main body program 21, the communication program 23, etc.) stored in the ROM 12, for example, various processing function units indicated by dotted lines in FIG. That is, the illustrated item generation unit 61, item processing unit 62, communication processing unit 63 (63-1, 63-2, etc.), logic processing unit 64, item processing scheduling unit 65, shared memory generation processing unit 66, logic processing schedule The processing functions of various processing function units such as the unit 67, the logic command generation unit 68, the optimum command generation unit 69, and the rating determination processing unit 70 are realized.

  Of these various processing function units 61 to 70, the processing function units 61 to 63 and 65 to 69 may be regarded as performing basically the same processing as the conventional one. However, processing related to any of a cyclic access counter 85, a sudden frequency access counter 86, and an upgrade determination flag 87, which will be described later, may be executed. The cyclic access counter 85, the sudden frequency access counter 86, and the upgrade determination flag 87, which will be described later, are basically information that does not exist conventionally. Therefore, basically, the processes related to these counters and flags may be regarded as new processes according to the present method.

  Also, the logic processing unit 64 may be regarded as having substantially the same basic processing function as the conventional one. However, an unexpected memory access unit 64a described later, which is a part of the function of the logic processing unit 64, is different from the conventional one.

The rating determination processing unit 70 is a processing function unit that does not exist conventionally.
The communication processing unit 63 is realized by the main body program 21 and the communication program 23. The processing function units other than the communication processing unit 63 are basically realized by the main body program 21, but are not limited to this example.

  The item generation unit 61 generates an item list 51 based on the screen data 22 or the like. This is generated, for example, by copying a part of the screen data 22 (further, a processed flag 118 described later is added).

  The shared memory generation processing unit 66 stores data (such as an access destination) according to the item list 51 generated by the item generation unit 61 in the shared memory 55. In other words, each stored data (such as each access destination) in the shared memory 55 is updated.

  Note that the data stored in the item list 51 and the shared memory 55 correspond to, for example, each item on the operation display screen (screen) currently displayed. Therefore, it is regenerated each time the screen is switched. The shared memory 55 also stores data such as access destinations associated with logic processing. Details will be described later.

  In the shared memory 55, the “acquired data” corresponding to each item on the operation display screen (screen) currently being displayed is stored (updated cyclically) by the communication processing unit 63.

  The communication processing unit 63 is a communication processing unit 63-1 or 63-1 provided for each connection device 4 (4-1, 4-2). That is, the illustrated communication processing unit 63-1 performs communication with the connection device 4-1 via the communication line 6 using the communication port WAY1 corresponding to the connection device 4-1, and the external memory thereof. Stored data in a predetermined area (allocated memory area). Then, this “acquired data” is overwritten and stored in the corresponding area of the shared memory 55.

  Similarly, the illustrated communication processing unit 63-2 communicates with the connection device 4-2 via the communication line 6 using the communication port WAY2 corresponding to the connection device 4-2, and externally transmits the communication port WAY2. Data stored in a predetermined area (allocated memory area) of the memory is acquired. Then, this “acquired data” is overwritten and stored in the corresponding area of the shared memory 55.

  The process of acquiring data from the external memory by the communication processing units 63 and the process of updating the data stored in the shared memory 55 by the “acquired data” are periodically (cyclically) executed.

  Here, the communication processing unit 63 of this example performs a process of acquiring storage data in the allocated memory area based on the optimum command list 54 (54-1, 54-2). The optimum command list 54 is generated by the optimum command generation unit 69 according to each connected device 4 based on the shared memory 55. The optimum command list 54-1 shown in the figure corresponds to the connected device 4-1, and the optimum command list 54-2 corresponds to the connected device 4-2.

  The optimum command generation unit 69 performs, for example, existing processing (such as address concatenation described above) disclosed in Patent Documents 1 and 2, etc. (JP 2009-54056 A, JP 2009-54055 A, etc.). Since it is a function part to perform, it does not explain in particular here.

  However, in brief, the access destination is generated so that the access destinations (allocated memory areas) for each item stored in the shared memory 55 are collectively accessed. For example, if there are items A, B, and C, and addresses D101, D105, and D108 are allocated memory areas, respectively, the area from address D101 to address D108 is collectively set as one access destination to the optimum command list 54. To be stored.

  Naturally, in this process, unnecessary data is also acquired. Therefore, only necessary data (data at addresses D101, D105, and D108) is selected and stored in the corresponding area of the shared memory 55. Discard unnecessary data.

  Usually, it takes time to perform communication processing with the connection device 4 via the communication line 6, and therefore the processing time is shortened even if the amount of data to be acquired is slightly increased and the selection processing is added. .

  However, since the processing time is not necessarily shortened by reducing the number of communications by grouping addresses as described above, the generation of the optimum command list 54 is not essential. However, even if the optimum command list 54 is not generated, in this method, an external memory access related to logic processing described later may be included in a cyclic external memory access related to item display.

  As described above, the communication processing unit 63 and the optimum command list 54 (further, a command list 53 described later) are provided according to each connected device 4. Therefore, when there are a plurality of connected devices 4, a plurality of communication processing units 63, optimum command lists 54, and the like are also provided. However, in this description, the communication processing unit 63, the optimum command list 54, and the like will be described together without being described for each connected device 4 (4-1, 4-2).

  The optimum command generation unit 69 basically stores the new shared memory 55 when the item list 51 is updated, for example, when the screen is switched, and the shared memory 55 is updated accordingly. A new optimum command list 54 corresponding to the contents is generated. In other words, basically, the contents of the optimum command list 54 are not changed except at this time. However, in this method, the contents of the optimum command list 54 may be changed by the rating determination processing unit 70. For example, an access destination by a logic processing unit 64 described later may be added to the optimum command list 54. At that time, the optimum command generation unit 69 performs optimization processing including the access destination by the logic processing unit 64 and the like (concatenation of the addresses, etc .; collects addresses together) and reproduces the optimum command list 54. It is desirable to make it. Details will be described later.

  The item processing unit 62 performs processing related to updating of display contents (for example, ON image / OFF image switching) for each item based on the data stored in the shared memory 55 ("acquired data"). Run. That is, the item processing unit 62 determines and updates the display content of the display operation screen based on, for example, data acquired from the most recently allocated memory area.

  The processing of the item processing unit 62 is also performed periodically, and the schedule management is performed by the item processing scheduling unit 65. That is, the item processing schedule unit 65 performs schedule management such as display update processing of each item by the item processing unit 62. That is, the item processing schedule unit 65 periodically calls the item processing unit 62, for example, and executes, for example, the processing of FIG. 8 described later (in other words, the processing of FIG. 8 is executed cyclically).

  The processing function unit, data, and the like related to the determination / update processing (refresh processing) of the display contents of each item on the display operation screen have been described above (excluding the rating determination processing unit 70).

  On the other hand, as described above, the CPU 11 also executes the logic process. The processing function unit, data, and the like related to the logic processing execution are the logic processing unit 64, logic processing scheduling unit 67, logic command generation unit 68, logic command list 52, command list 53 (53-1, 53-2) shown in the figure. Etc.

The processing function unit, data, and the like related to the execution of the logic processing may be basically the same as those in the prior art except for the logic processing unit 64, and will be briefly described below.
The logic command generation unit 68 performs processing (for example, branch processing; if-then-else statement) based on data of an arbitrary access destination (arbitrary address of an arbitrary external memory device of the arbitrary connected device 4) regarding an arbitrary logic program. Etc.) is stored in the logic command list 52. A specific example of the logic command list 52 will be described later.

  The logic processing unit 64 performs data acquisition processing according to the logic command list 52 under the schedule management by the logic processing scheduling unit 67. For example, the access destination stored in the logic command list 52 is stored in the shared memory 55, and a command based on the access destination is generated and stored in the command list (FIFO) 53.

  In the following description, “access processing” basically means “access processing to external memory”. Similarly, “access destination” basically means “any address of any external memory device of any connected device 4”.

  Here, the communication processing unit 63 of this example executes not only the access process based on the optimum command list 54 but also the access process based on the command list 53. That is, when any command (for example, a command 130 described later) is stored in the command list 53, this command is taken out and an access process based on this command is performed. Then, the access processing result (“acquired data” from the access destination) is stored in the corresponding area of the shared memory 55.

  The logic processing unit 64 waits for the “acquired data” to be stored in the corresponding area of the shared memory 55 by the communication processing unit 63, and if stored, performs the above-described processing (for example, branch processing) based on the acquired data. Run. In particular, in the case of branch processing, it is not known until the acquired data is obtained whether to execute then or else. For this reason, the standby time may be long. In addition, if such irregular (sudden) access processing associated with logic processing is frequently performed, the access processing related to the refresh processing may be affected, and it may take time to update the display contents.

  As a result, in this method, if there is an access destination that frequently performs access processing among the access destinations of irregular (sudden) access processing that accompanies logic processing, this access destination is the optimal command list. 54. As a result, regarding this access destination, the cyclic access is performed and the acquired data is stored in the corresponding area of the shared memory 55 regardless of whether or not an irregular (sudden) access process occurs due to the logic process. Will be stored.

  Then, when an irregular (sudden) access process to the access destination occurs, the logic processing unit 64 acquires data stored in the corresponding area of the shared memory 55. As a result, the waiting time is hardly required and the access process related to the refresh process is not disturbed. Therefore, the update process of the item display content is not delayed.

  The logic processing unit 64 includes a processing function of a sudden memory access unit 64a (not shown) described later. Thus, the logic processing unit 64 performs not only the processes in FIGS. 10 and 11 described later but also the processes in FIGS. 12 and 13 described later. Details will be described later.

Hereinafter, the various processing function units and various data will be described in more detail.
First, a detailed processing example of the communication processing unit 63 will be described.
FIGS. 6 and 7 are flowchart diagrams (1/2) and (1/2) of external memory access processing executed by each communication processing unit 63 (63-1, 63-2), for example, periodically (cyclically). 2/2). In the following description, “FIG. 6” and the like are not particularly distinguished.

  In the processing example shown in FIG. 6 and the like, basically, cyclic communication processing related to the refresh processing is executed, but in the situation where irregular (sudden) communication processing related to the logic processing is necessary, Perform communication processing. Note that the situation in which irregular (sudden) communication processing is necessary is when, for example, a command (indicating an access destination; for example, a command 130 described later) is stored in the command list 53. .

  Note that the processing itself of the communication processing unit 63 illustrated in FIG. 6 and the like may be an existing technology. Also, various data related to the processing (optimal command list 54, shared memory 55, command 130 in the example shown in FIG. 19 to be described later) may have the data structure itself. However, the contents of data may differ from existing technologies. That is, the optimum command list 54 may include not only the access destination related to the cyclic communication processing but also the access destination related to the sudden communication processing. Details will be described later.

  Regarding the cyclic communication process, first, an arbitrary memory access command is acquired from the optimum command list 54 (step S11). For example, a corresponding command is extracted using an execution index (not shown) in the optimum command list 54 as a key.

  Here, FIG. 19 shows an example of the data structure of the command. The optimum command list 54 and the command list 53 are a list of commands 130 as shown in FIG. 19, for example.

19 includes a command type 131, a memory block number 132, each memory block 133 (N memory blocks 133), and the like.
The command type 131 is, for example, “block read”, “multiple block read”, or the like. Since these are also existing technologies, they will not be described in detail, but a brief description will be as follows.
• Block read: A command that specifies an arbitrary start address and number of data. Data corresponding to the number of data is acquired from the head address. The memory block number 132 is fixed to “1”.
・ Multiple block read: This is an extended block read command, and multiple access destinations can be specified. That is, the number of memory blocks 132 is “2” or more.

The memory block number 132 is the number of memory blocks 133.
Each memory block 133 includes data items of a port 141, a device 142, an address 143, and a data number 144 in the illustrated example, for example. The port 141, the device 142, and the address 143 indicate the access destination (for example, the top address of the allocated memory area). That is, the port 141 is an identification number or the like of the port corresponding to the connected device 4 to be accessed. The device 142 is identification information or the like of an access destination memory device in the access destination connected device 4. The address 143 is the head address of the storage area to be accessed in the memory device.

Then, an area corresponding to the number of data 144 from the head address means an access destination storage area, and stored data in the storage area is read out.
That is, in the process of FIG. 7 and the like, the command 130 acquired in the process of step S11 is transmitted to the connected device 4 that is the access destination (step S12). Read the stored data from the access destination storage area and send it back. When this reply is received (step S13), “acquired data” (data read from the access destination storage area) included in the reply is stored in the corresponding area of the shared memory 55 (step S14). This process itself may be the same as in the past, but in this example, the “acquired data” includes not only the data related to the cyclic communication process for displaying the item but also the sudden communication. Data related to processing may also be included.

  Finally, for example, an execution index (not shown) in the optimum command list 54 is advanced to the next command (step S15). That is, the next processing target command 130 is designated.

  Subsequently, the first command 130 is obtained from one or more command 130 groups stored in the command list 53 (step S16). However, if there is no command 130 in the command list 53 (step S17, NO), this process is terminated.

  When one arbitrary command 130 can be acquired from the command list 53 (step S17, YES), for the command 130 to be processed, the steps S12, S13, Processing substantially similar to the processing of S14 is performed (steps S18, S19, S20).

  That is, by transmitting the command 130 acquired in step S16 to the access destination connected device 4 (step S18), on the connected device 4 side, the stored data is read from the access destination storage area and returned. When this reply is received (step S19), “acquired data” included in this reply is stored in the corresponding area of the shared memory 55 (step S20).

  Finally, the request source of the command 130 to be processed (for example, the logic processing unit 64) is notified of completion (step S21). The logic processing unit 64 or the like that has received the notification of completion reads the data stored in step S20 from the shared memory 55.

Here, FIG. 16A shows a data structure example of the shared memory 55.
In the example shown in FIG. 16A, the data stored in the shared memory 55 includes data of the port 81, device name 82, address 83, data 84, cyclic access counter 85, sudden frequency access counter 86, and upgrade determination flag 87. Consists of items.

Among these, the port 81, the device name 82, the address 83, and the data 84 may be the same as those in the prior art, and will be briefly described below.
The port 71 is identification information of the communication port and the like, and is substantially information for identifying the connection device 4 of the communication partner. The device 72 is identification information of a memory device (external memory) in the connection device 4 of the communication partner. The address 73 is an address of a predetermined storage area in the external memory indicated by the device 72, and the data 74 is stored with data acquired from this storage area. Note that the port 71, the device name 72, and the address 73 may be regarded as corresponding to the “allocated memory address” of each item.

  In addition to the conventional data items, the cyclic access counter 85, the sudden frequency access counter 86, and the upgrade determination flag 87 are provided in this example. Although these will be described later, they will be schematically described here.

  First, the shared memory 55 stores the access destination related to the refresh process and the acquired data from the access destination, but the access destination related to the sudden access process and the acquired data from the access destination are also stored. Stored. For the record related to the refresh process, a predetermined value (+1 or the like) is forcibly stored in the cyclic access counter 85, and the sudden frequency access counter 86 and the upgrade determination flag 87 are not used. On the other hand, for the record related to the sudden access processing, “0” or the like is forcibly stored in the cyclic access counter 85 and the sudden frequency access counter 86 and the upgrade determination flag 87 are used.

  Here, if the usage method of the counter 86 and the flag 87 will be briefly described, each time an arbitrary sudden access process is executed, the sudden frequency access counter 86 of the corresponding record is counted up. When the value of the counter 86 exceeds a predetermined threshold, the upgrade determination flag 87 is turned on. The processing targets of the cyclic communication processing include not only records whose cyclic access counter 85 is a predetermined value (+1 or the like) but also records whose upgrade determination flag 87 is flag ON.

  The sudden frequency access counter 86 is periodically reset. Thus, even in the case of the above sudden access processing, if the value of the counter 86 exceeds the threshold value within a predetermined period, that is, access that is frequently executed, it is included in the cyclic access processing. To. As in the prior art, this method optimizes cyclic access processing. This improves the access efficiency of the entire external memory access process including the sudden access process. However, the present invention is not limited to this example. The sudden access process may be included in the cyclic access process without optimization.

Next, processing of the item processing unit 62 will be described with reference to FIG.
FIG. 8 is a processing flowchart of the item processing unit 62.
The item processing unit 62 is periodically called by the item processing scheduling unit 65 as described above, and executes the processing of FIG.

In the illustrated processing example, first, the processed flag 119 of all records in the item list 51 is initialized (flag OFF) (step S31).
Here, FIG. 17B shows a data configuration diagram of the item list 51.

  The item list 51 in the illustrated example includes data items of item type 111, coordinates 112, size 113, port 114, device name 115, address 116, data 117 for each item type, and processed flag 118. Each record in the item list 51 corresponds to each item on the operation display screen. Note that the present invention is not limited to the illustrated example, and may further include an identification number of each item.

The item type 111 stores item type identification information indicating the type of the item (switch, lamp, numerical display, etc.).
The port 114, the device name 115, and the address 116 are memory allocation information related to each item, and correspond to the allocated memory address. That is, the storage area indicated by the address 116 in the external memory indicated by the device name 115 in the connected device 4 corresponding to the port 114 is an area assigned to the item (the assigned memory area). The stored data in the allocated memory area indicates the current state of the control / monitoring object related to the item. For example, if the item type 111 is a lamp, flag data indicating lighting / extinguishing of the lamp is the stored data.

  The data 117 for each item type is, for example, an image of the item (for example, a lamp ON image and a lamp OFF image). The coordinates 62 and the size 63 indicate the display position and size of the item image.

Returning to the description of FIG.
Subsequent to the process of step S31, an arbitrary unprocessed item (item related to a record whose processed flag 119 is OFF) is set as a process target item from the item list 51 (step S32). And the data 84 etc. of the corresponding record corresponding to the said process target item are acquired as the memory information 71 in the shared memory 55 (step S33).

  For example, a record in which the port 81, the device name 82, and the address 84 are the same as the port 114, the device name 115, and the address 116 of the processing target item is the corresponding record.

An example of the memory information 71 is shown in FIG.
The memory information 71 in the illustrated example includes data 101, a cyclic access counter 102, a sudden frequency access counter 103, an upgrade determination flag 104, and the like. These are copies of the record data 84, the cyclic access counter 85, the sudden frequency access counter 86, and the upgrade determination flag 87, for example.

However, the present invention is not limited to the above example, and the memory information 71 may be only the data 101, for example.
And the display regarding the said process target item is performed using the said acquired memory information 71 grade | etc., (Step S34). Of course, in this case, the display processing is performed using the data of the processing target item in the item list 51 (coordinate 112, size 113, item image, etc.).

  Finally, the processed flag 118 of the record of the processing target item in the item list 51 is set to processed (flag ON) (step S35). And when the unprocessed item remains in the item list 51 (step S36, YES), it returns to step S32. If the process of said step S32-S35 is performed about all the records (all items) of the item list 51 (step S36, NO), this process will be complete | finished.

Next, the shared memory generation processing unit 66 will be described.
FIG. 9 is a process flowchart of the shared memory generation processing unit 66.
For example, each time the shared memory generation processing unit 66 is called from the item generation unit 61, the shared memory generation processing unit 66 executes the processing of FIG. The item generation unit 61 calls the shared memory generation processing unit 66 every time a new list (new record) is generated in the item list 51 based on the screen data 22, for example. At this time, the item generation unit 61 passes information (pointer) indicating the generated new list (new record) to the shared memory generation processing unit 66.

  Accordingly, the shared memory generation processing unit 66 refers to the generated new list (new record) in the item list 51 and acquires the port 114, the device name 115, the address 116, and the like (step S51).

  Then, based on the acquired data, it is determined whether or not the corresponding record has already been registered in the shared memory 55 (step S52). For example, in the shared memory 55, if there is a record in which the port 81, device name 82, and address 83 are the same as the acquired port 114, device name 115, and address 116, it is determined that registration has been completed (step S52, YES). In this case, the process proceeds to step S54 without performing step S53.

  On the other hand, if it has not been registered (step S52, NO), the corresponding record is additionally registered in the shared memory 55 (step S53). That is, a new record is added to the shared memory 55, and the port 114, device name 82, and address 83 store the data of the port 114, device name 115, and address 116 acquired in step S51. Then, the process proceeds to step S54.

  In step S54, the cyclic access counter 85 in the registered record in the shared memory 55 or the record added in step S53 is updated (eg, +1) (not updated, but forcibly set to a predetermined value (here, “1”)). ') You may consider it to be)). Thereby, for example, the determination in step S72 described later is NO. Then, this process ends.

Next, processing of the logic processing unit 64 will be described.
10 and 11 are process flowchart diagrams (1/2) and (2/2) of the logic processing unit 64. FIG. In the following description, “FIG. 10” and the like are not particularly distinguished.

Here, as described above, the logic processing unit 64 also performs the processing of FIGS. 12 and 13 described later.
In the processing example shown in FIG. 10 and the like, first, the processed flag 127 of all the records in the logic command list 52 is initialized (flag OFF) (step S41).

Here, the logic command list 52 will be described.
FIG. 18 is a specific example of the logic command list 52.
The logic command list 52 in the illustrated example has data items such as an execution condition 121, a port 122, a device name 123, an address 124, a command line number 125, each command 126, a processed flag 127, a command memory previous value 128, and the like.

  The port 122, device name 123, and address 124 indicate the access destination. That is, the storage area indicated by the address 124 in the external memory device indicated by the device name 123 in the connected device 4 corresponding to the port 122 is the access destination. This is an access destination related to an arbitrary logic process involving access to the external memory (hereinafter also referred to as a command memory). Then, an instruction relating to the arbitrary logic processing is stored in each instruction 126, one line at a time. The number of instructions 126 (number of lines) is stored in the number of instruction lines 125.

  The execution condition 121 stores a condition for executing each instruction 126 described above. This is basically a condition based on the stored data of the access destination. For example, when the stored data at the access destination is a 1-bit flag, for example, switching from the flag OFF state to the flag ON state becomes the execution condition 121. In this example, for example, when the logic processing unit 64 determines that the access destination flag has been switched from OFF to ON, the logic processing unit 64 executes the instructions 126.

  For the determination related to the execution condition 121, for example, the command memory previous value 128 is used. That is, as will be described later, every time the storage data of the access destination is newly acquired, the logic processing unit 64 performs the determination based on the acquired data and the command memory previous value 128. For example, when the acquired data is the flag ON and the command memory previous value 128 is the flag OFF, it is determined that the switch has been switched from OFF to ON. Regardless of the determination result, each time the storage data at the access destination is newly acquired, the acquired data is stored as a new command memory previous value 128.

  Each record in the logic command list 52 (particularly its execution condition 121, port 122, device name 123, address 124, number of command lines 125, each command 126, etc.) is generated by the logic command generation unit 68. This is generated based on, for example, an arbitrary logic program. This generation process itself is an existing process, and is not particularly illustrated or described here. Then, the logic processing unit 64 executes the processing of FIG. 10 and the like using the generated logic command list 52 and the like. Returning to FIG.

If the process of the said step S41 is performed, the process between step S42-step S46 of illustration will be repeated by making each record of the said logic instruction | command list | wrist 52 into a process target sequentially.
That is, an unprocessed record (logic instruction) is referred to from the logic instruction list 52 (step S42), for example, the access destination (command memory) is recognized, and acquired / stored from the access destination from the shared memory 55. Data 84 that is the acquired data is acquired (step S43). That is, for example, the data 84 in the record in which the port 81, device name 82, and address 83 are the same as the processing target port 122, device name 123, and address 124 in the shared memory 55 is acquired.

  Then, based on the acquired data 84 and the previous value 128 of the command memory, it is determined whether or not the data in the command memory has changed (step S44). For example, when there is a change from flag OFF to flag ON (or conversely, from flag ON to flag OFF) as in the above example, it is determined that the data in the command memory has changed (step S44, YES). ). In this case, it is further determined whether or not it is an execution trigger based on the execution condition 121 and the like (step S47).

  In the above example, if the flag is changed from OFF to ON, it is determined that the trigger is an execution trigger (step S47, YES), the process of step S48 is executed, and then the process of step S49 is executed. become. On the other hand, in the above example, if the flag is changed from ON to OFF, it is determined that the trigger is not an execution trigger (NO in step S47), and the process of step S49 is executed without executing the process of step S48. Will do.

  The process of step S48 is a process of sequentially executing each instruction 126 in the logic instruction to be processed (sequentially executing from the first line to the Nth line). Then, each time an arbitrary external memory access is generated with the sequential execution of each instruction 126, for example, the unexpected memory access unit 64a (not shown) included in the logic processing unit 64 executes the processing shown in FIG. . Since the process of step S48 is performed only when step S47 becomes YES for each logic command, the external memory access by the process of FIG. 12 or the like is an irregular (sudden) external memory access process. Note that the information indicating the access destination is included in the instruction 126, for example.

  The process in step S49 is a process for updating the command memory previous value 128 in the logic command to be processed with the data 84 acquired in step S43.

Finally, the processed flag 127 in the logic command to be processed is set to processed (flag ON) (step S45).
If there is an unprocessed record (logic instruction) in the logic instruction list 52 (YES in step S46), the process returns to step S42. When there is no unprocessed record (logic command) (step S46, NO), this process ends.

  FIGS. 12 and 13 are process flowchart diagrams (1/2) and (1/2) of the logic processing unit 64 when the external memory access process accompanying the logic process (that is, the irregular (sudden) access process) occurs. 2/2). In the following description, “FIG. 12” and the like are not particularly distinguished.

  Note that, as described above, the processing in FIG. 12 and the like may be considered to be executed by the unexpected memory access unit 64a (not shown) included in the logic processing unit 64. However, in this description, the sudden memory access unit 64a is not particularly mentioned, and is often described as being executed by the logic processing unit 64.

  In the processing shown in FIG. 12 and the like, the logic processing unit 64 recognizes the access destination of the irregular (sudden) access processing that has occurred, and the access destination data is stored in the shared memory 55 as the data 84. If stored (in other words, included in the cyclic access process), the data 84 is acquired. For example, first, it is determined whether or not the access destination is registered in the shared memory 55 (step S61). This is registered, for example, when the shared memory 55 has a record in which the port 81, device name 82, and address 83 are the same as the access destination (that port, device name, address). (Step S61, YES) is determined.

  If the access destination is not registered in the shared memory 55 (step S61, NO), the access destination is newly registered in the shared memory 55 (step S62). For example, a new record is added to the shared memory 55, and the access destination (its port, device name, address) is stored in the port 81, device name 82, and address 83 of the new record. Further, the cyclic access counter 85, the sudden frequency access counter 86, and the upgrade determination flag 87 of the new record are set to a predetermined initial state. That is, for example, the cyclic access counter 85 and the sudden frequency access counter 86 are set to the initial value “0”. The upgrade determination flag 87 is set to OFF.

  Next, from the shared memory 55, the data 84, the cyclic access counter 85, the sudden frequency access counter 86, and the upgrade determination flag 87 of the corresponding record (registered record related to the access destination or the new record) are stored as the memory information 71. get. These are acquired as the data 101, the cyclic access counter 102, the sudden frequency access counter 103, and the upgrade determination flag 104 (step S63).

  Then, based on the memory information 71, it is determined whether or not it is a cyclic access target (step S64). If the cyclic access counter 102 in the memory information 71 acquired in step S63 is “1” or more, or if the upgrade determination flag 104 is flag ON, it is determined that the target is cyclic access (step S64, YES).

If the corresponding record is the new record, the determination in step S64 is naturally NO.
Note that even if the access destination is related to logic processing, the determination in step S64 is YES for those that are "upgraded" to be described later. That is, such an access destination is included in the cyclic access target. Therefore, it should be accessing together with the cyclic access processing related to the item display. Details will be described later.

  If it is a cyclic access target (step S64, YES), the data 84 acquired in step S63 (data 101 in the memory information 71) should be data to be acquired in the current access process. That is, the latest (most recent) data acquired from the access destination storage area by the cyclic access process should be stored as the data 84. Therefore, in this case, a predetermined logic process is executed using the acquired data 84. Then, the burst frequency access counter 86 of the registered record relating to the access destination in the shared memory 55 is updated (incremented by +1) (step S68), and this process is terminated.

  On the other hand, when it is not a cyclic access target (step S64, NO), an existing access process is executed. That is, the command 130 including the access destination (port, device name, address) is generated and stored in the command list 53 (step S65). Then, the communication processing unit 63 waits for the command 130 to execute the process shown in FIG. 6 and the like to perform the access completion event notification in step S21 (step S66). When an access completion event notification is received, the latest (most recent) data of the access destination should be stored in the data 84 of the corresponding record. Therefore, the data 84 is acquired (step S67), and the predetermined logic process is executed using the acquired data 84. Then, the sudden occurrence frequency access counter 86 of the record related to the access destination in the shared memory 55 is updated (incremented by +1) (step S68), and this process is terminated.

  In the existing access processing related to the sudden access, the waiting time in step S66 may be very long. This is the case, for example, when another command 130 is already stored in the command list 53 and forced to wait in turn. On the other hand, if the determination in step S64 is YES, the logic process can be immediately executed using the data 84 acquired from the shared memory 55. That is, the processing time can be shortened. In addition, the processing load of the communication processing unit 63 related to the command 130 stored in the command list 53 can be reduced. Then, the access process related to the refresh process is less disturbed by the sudden access process.

  Further, even if the access destination is related to logic processing, the “upgraded” which will be described later is subject to optimization by the optimum command generation unit 69, so that the data of the access destination can be efficiently acquired. I can expect. Details will be described later.

The above-mentioned “upgrade” or the like is performed by the rating determination processing unit 66.
14 and 15 are process flowchart diagrams (1/2) and (2/2) of the rating determination processing unit 66. FIG. In the following description, “FIG. 14” and the like are not particularly distinguished.

The rating determination processing unit 66 periodically executes the processing shown in FIG.
First, each record in the shared memory 55 is sequentially processed, and the process of steps S71 to S78 is repeated for the process target record.

  That is, first, the processing target record data 84, cyclic access counter 85, sudden frequency access counter 86, and upgrade determination flag 87 are acquired as memory information 71 (step S71). However, in the following explanation, the symbols such as “84” and “85” are used as they are without using the symbols such as “101” and “102” of the memory information 71.

  Using the memory information 71, it is first determined whether or not it is a rating object (step S72). Records related to sudden access associated with the logic processing are subject to rating. Therefore, when the cyclic access counter 85 of the processing target record is “1” or more, since the processing target record is a record related to the refresh processing, it is determined that it is not a rating target (step S72). , NO).

  On the other hand, when the cyclic access counter 85 is less than “1” (in this example, “0”), it is determined that the processing target record is a rating target (YES in step S72), and then the processing It is determined whether or not the target record is an upgrade target (step S73). For example, if the value of the sudden occurrence access counter 86 of the processing target record is equal to or greater than a first threshold value set in advance, it is determined that the target is an upgrade target (step S73, YES). In this case (step S73, YES), the upgrade determination flag 87 of the processing target record is turned on to “upgrade” (step S74). Then, the process proceeds to step S77.

  Here, “upgrade” means that the sudden access process related to the processing target record is included in the cyclic access process related to the refresh process.

  If it is determined that the processing target record is not the upgrade target (step S73, NO), it is determined whether or not the processing target record is the downgrade target (step S75). For example, if the value of the sudden occurrence frequency access counter 86 of the processing target record is less than a second threshold value set in advance, it is determined that the target is a downgrade target (YES in step S75). In this case (step S75, YES), the upgrade determination flag 87 of the processing target record is turned OFF to “downgrade” (step S76). Then, the process proceeds to step S77.

  In other words, in this example, after the sudden access process related to the record to be processed becomes a state included in the cyclic access process, this state is not always maintained and is excluded from the cyclic access process. In some cases (ie, “downgrading”) it is possible. Therefore, as described above, even if step S64 is YES, the process of step S68 (the process of updating (+1) the sudden frequency access counter 86) is executed.

The values of the first threshold value and the second threshold value may be set arbitrarily, but are preferably set so as to satisfy the condition of “first threshold ≧≧ second threshold”.
If the determination in step S75 is NO, the process proceeds to step S77 as it is. If the upgrade determination flag 87 is OFF, the determination in step S75 may be forcibly set to NO.

  The processing in FIG. 14 and the like is executed periodically (every predetermined period of time) as described above, and each time the unexpected frequency access counter 86 of the processing target record is set to the initial state by the processing in step S77 described later. It returns to ('0'). Accordingly, the value of the sudden frequency access counter 86 at the time of the processing of FIG. 14 and the like is the number of times sudden access has occurred within the predetermined period (the processing of FIG. It can be said that the number of occurrences) is shown.

  Here, it is assumed that there is an arbitrary predetermined period A and a predetermined period B thereafter. In the predetermined period A, since the frequency of sudden access related to an arbitrary access destination is high, the upgrade process in step S74 is executed in the process of FIG. 14 when the predetermined period A has elapsed. To do. As a result, regarding this access destination, step S64 is YES in the process of FIG. 12 and the like during the subsequent predetermined period, but the process of step S68 is also executed in this case as described above. Here, if the occurrence frequency of the sudden access related to the access destination is low in the predetermined period B, the downgrade process in step S76 may be executed in the process of FIG. It will be possible.

  Then, no matter what the determination results of steps S72, S73, and S75 described above are, the incident frequency access counter 86 of the processing target record is set to the initial state ('0' clear) (step S77). When there is an unprocessed record in the shared memory 55 (step S78, YES), the process returns to step S71.

  Each record in the shared memory 55 is sequentially set as the above processing target record, and the above-described processing is executed. When all the records are processed (NO in step S78), the process proceeds to step S79.

In the processes in steps S79 and S80, the optimum command list 54 is recreated based on the shared memory 55 after the processes in steps S71 to S78.
That is, first, the cyclic access memory list 72 is generated based on the shared memory 55 after the processing of steps S71 to S78 (step S79). This extracts all records satisfying a predetermined condition from the records in the shared memory 55, and generates the cyclic access memory list 72 based on the extracted records. The predetermined condition is that the cyclic access counter 85 is 1 or more, or the upgrade determination flag 87 is ON (whichever one is satisfied).

  Note that the processes in steps S79 and S80 are executed by sequentially processing each port (connected device 4) as a processing target. Therefore, strictly speaking, the predetermined condition further includes that the port 81 is a processing target port.

A specific example of the cyclic access memory list 72 is shown in FIG.
In the example shown in FIG. 16B, the cyclic access memory list 72 includes a device name 91 and an address 92. In this example, the device name 82 and address 83 of each extracted record are stored in the device name 91 and address 92.

  Then, the generated cyclic access memory list 72 is transferred to the optimum command generation unit 69, and the optimum command generation unit 69 generates a new optimum command list 54 (step S80). Note that the generation process of the optimal command list 54 by the optimal command generation unit 69 is an existing technique disclosed in the above-mentioned Patent Documents 1 and 2, and the like, and therefore will not be described here.

  Finally, if there is an unprocessed port (step S81, YES), the process returns to step S79, and the processes of steps S79 and S80 are executed for the next processing target port. When the process is executed for all the ports (step S81, NO), this process is terminated.

Here, in FIG. 20, the processing function figure of the programmable display 1 of this example is shown.
The processing function diagram is already shown in FIG. 4 and the like, but FIG. 20 is shown from another viewpoint.

  In the processing function diagram shown in FIG. 20, the programmable display 1 includes a logic control unit 151, an external memory reference reception unit 152, a data cache reading unit 153, a reference frequency update unit 154, a rating determination unit 155, an integration unit 156, cyclic Each processing function unit includes a reading unit 157 and a communication processing unit 158. These various processing function units are realized, for example, when the CPU 11 executes application programs stored in advance in the ROM 12 or the like.

  The logic control unit 151 executes an arbitrary logic process, and when an irregular (sudden) access process to an arbitrary access destination associated with the logic process occurs, the logic control unit 151 passes through the external memory reference reception unit 152 Get access destination data. For example, the external memory reference receiving unit 152 is requested to acquire data from the access destination by passing the external memory identifier 162 indicating the access destination. The external memory identifier 162 is, for example, an arbitrary address of an arbitrary external memory in an arbitrary connected device 4.

  In response to this request, the external memory reference receiving unit 152 acquires the access destination data (external memory data 161) from the data verse 160 via the data cache reading unit 153, and passes it to the logic control unit 151. Further, the reference frequency update unit 154 updates the reference frequency data related to the access destination stored in the database 160.

  The database 160 may be regarded as corresponding to the shared memory 55, for example. The database 160 stores various data such as an access destination, a data cache (acquired data from the access destination), a reference frequency, a rating state, and the like.

In addition, when the requested access destination is not registered in the database 160, the external memory reference receiving unit 152 registers the access destination or the like in the database 160.
The communication processing unit 158 is basically a processing function unit that performs communication processing with the connection device 4 via the communication line in response to some data acquisition request (access processing). Then, the data acquired by this communication process is passed to the request source or stored in the database 160.

  Here, the external memory reference accepting unit 152 causes the communication processing unit 158 to acquire data from the connected device 4 when processing for acquiring the corresponding data from the data verse 160 in response to the request is performed immediately. It may be performed after it is stored in the database 160. The latter may be regarded as a data acquisition method of the existing technology. In either of these two methods, the reference frequency data is updated.

  When the access destination requested by the logic control unit 151 is integrated into the cyclic access destination group described later by the integration unit 156 described later, the external memory reference receiving unit 152 immediately acquires the corresponding data from the database 160. get. On the other hand, if they are not integrated, the requested access destination is passed to the communication processing unit 158 to request data acquisition. Note that the determination of whether or not they are integrated is performed based on, for example, the rating state. For example, it is determined that the rating status is integrated when the rating status is an upgraded status described later.

  Upon receiving the data acquisition request, the communication processing unit 158 performs communication processing with the connection device 4 to acquire the access destination data, stores the acquired data in the database 160, and refers to the external memory for data acquisition completion. The reception unit 152 is notified.

  Receiving this notification, the external memory reference receiving unit 152 reads the acquired data from the database 160 and passes it to the logic control unit 151 as the external memory data 161.

  The cyclic reading unit 157 holds a cyclic access destination group (not shown). For example, cyclic acquisition of data from each access destination of the cyclic access destination group is performed by the communication processing unit 158. Do through. A cyclic access destination group (not shown) is an access destination for each item related to the refresh process, for example.

  The cyclic access destination group (not shown) corresponds to, for example, the access destination group related to the refresh process described above. That is, it corresponds to an access destination group related to each item on the display screen (in particular, it corresponds to the optimum command list 54 but is not limited to this example).

  Here, the rating determination unit 155 performs rating determination, for example, periodically for each access destination registered in the database 160 based on the corresponding reference frequency data, and stores the determination result as the rating status. To do. The rating state includes a normal state and an upgraded state. Rating judgment results include upgrades, downgrades, and current status. When it is determined that the upgrade is made in the normal state, the state is shifted to the upgraded state. If it is determined that the rating is downgraded in the upgraded state, it shifts to the normal state.

  For example, if the reference frequency is equal to or higher than a predetermined first threshold, it is determined that the upgrade is made. If the reference frequency is less than the predetermined second threshold, it is determined that the rating is downgraded. The threshold value may be set arbitrarily, but is preferably set so as to satisfy the condition “first threshold ≧ second threshold”.

  When the requested access destination is in the upgraded state, the external memory reference receiving unit 152 performs the above-described “process for immediately acquiring the corresponding data from the database 160”. On the other hand, in the normal state, the data acquisition by the communication processing unit 158 is performed as described above.

  Then, the integration unit 156 determines, for example, periodically (every predetermined period), an access destination in which the rating state is the “upgraded state” in the database 160. Then, the determined access destination is set as the upgraded state access destination, and the upgraded state access destination is integrated into the cyclic access destination group. As a result, even if the access destination is associated with the logic process, the access process is periodically performed together with the access process to the external memory of the cyclic connection device 4 associated with the refresh process or the like. Become. Then, the cyclic reading unit 157 overwrites and stores the data acquired by the cyclic access process in the corresponding area of the database 160.

Note that the integration unit 156 may also perform processing for excluding the access destination determined to be downgraded from the cyclic access destination group.
In addition, the cyclic access destination group may correspond to the optimum command list 54 as an example. In this example, the integration unit 156 may also have a processing function corresponding to the optimum command generation unit 69. In this example, the rating determination unit 155 and the integration unit 156 may be regarded as corresponding to the rating determination processing unit 70.

  However, the cyclic access destination group does not necessarily have to be optimized. That is, the cyclic access destination group may be simply a collection of access destinations related to the refresh process.

  As described above, the programmable display device 1 of this example basically includes an external memory access related to the refresh processing of the item display on the display screen and an external memory (regular; sudden) accompanying the execution of the logic processing. Assume a programmable display that performs access. Even when the frequency of external memory access accompanying the execution of logic processing is high, the operation can be prevented from slowing down.

  That is, in the programmable display 1 of this example, for example, access destinations with high access frequency in external memory access accompanying logic processing execution are integrated into an access destination group related to refresh processing. Accordingly, it is possible to suppress a situation in which external memory access associated with execution of logic processing greatly hinders external memory access processing associated with refresh processing.

  In particular, the optimal command list 54 is generated by performing optimization after including an access destination having a high access frequency in the external memory access accompanying the execution of logic processing in the access destination group related to the refresh processing. This improves the overall processing efficiency related to external memory access.

Furthermore, since it is not necessary to access the external memory every time a sudden external memory access accompanying the execution of the logic processing occurs, the processing efficiency related to the logic processing is improved.
In addition, the programmable display 1 of this example can also consider what has the following processing function part not shown, for example.

An item information storage unit that stores access information indicating each access destination corresponding to each item on the display screen;
First data acquisition means for periodically acquiring data from each access destination in the connected device and storing it in an internal memory based on the access information;
-Arbitrary logic processing is executed, and when access processing to an irregular access destination that is an access destination accompanying the logic processing occurs, it is determined whether or not the irregular access destination is integrated with the access information. To do. And a logic processing execution unit that acquires data corresponding to the irregular access destination from the internal memory when it is determined that the irregular access destination is integrated with the access information;
A rating unit that sets the above-mentioned irregular access destination whose access frequency is equal to or higher than a predetermined first threshold every time a predetermined period elapses as an upgraded state access destination;
-An integration unit that integrates the above-mentioned access information into the irregular access destination that is the above-mentioned access status;
A second data acquisition unit that acquires data from the irregular access destination in the connected device when the logic process execution unit determines that the irregular access destination is not integrated with the access information;
In addition, for example, when any one or more of the irregular access destinations are integrated with the access information, the first data acquisition unit acquires data from each of the irregular access destinations and stores the internal data Store in memory.

  In addition, for example, the logic processing execution unit performs the irregular processing every time access processing to any irregular access destination occurs regardless of whether the irregular access destination is integrated into the access information. The access frequency related to the access destination is updated.

  In addition, for example, when the access frequency related to the irregular access destination that is the upgraded access destination is less than a predetermined second threshold, the rating unit performs the downgrade to perform the access information. Do n’t integrate with

Further, for example, an access optimization unit that generates the optimized access information based on each access destination corresponding to each item on the display screen may be included.
In the case of this example, for example, the integration unit causes the optimization unit to execute the optimization process based on each access destination according to each item on the display screen and the above-described upper-level access destination. The optimized access information is regenerated.

  In the case of this example, the first data acquisition unit executes processing for acquiring data from each access destination and storing it in the internal memory based on the regenerated optimized access information. . The apparatus further includes an item display control unit that controls the display contents of each item on the display screen using the data of each access destination corresponding to each item acquired by the first data acquisition unit. Also good.

The item information storage unit may be regarded as corresponding to the item list 51, for example.
For example, the first data acquisition unit may be regarded as corresponding to the cyclic reading unit 157 or may be regarded as corresponding to the optimum command list 54 and the communication processing unit 63.

  The logic processing execution unit may be considered to correspond to, for example, the logic processing unit 64 or the like, or may be considered to correspond to the logic control unit 151 and the external memory reference reception unit 152, for example.

The rating unit may be regarded as corresponding to the rating determination unit 155, for example.
The integration unit may be regarded as corresponding to the integration unit 156, for example.
Alternatively, it may be considered that the rating unit and the integrating unit correspond to the rating determination processing unit 70.

  The second data acquisition unit may be regarded as corresponding to the external memory reference reception unit 152 and the communication processing unit 158, for example. Alternatively, the second data acquisition unit may be regarded as corresponding to the command list 53 and the communication processing unit 63.

The access optimization unit may be considered to correspond to the optimum command generation unit 69, for example.
For example, it is assumed that there are addresses D102 and D105 as access destinations related to item display. In this case, in the optimum command list 54 generated by the optimum command generator 69, the access destination is “address D102 to address D105”. Therefore, the stored data of “address D102 to address D105” are collectively acquired from the connected device 4 in one communication. This itself is an existing technology as described above.

  Here, for example, it is assumed that there is an address D108 as an irregular access destination related to logic processing. In the case of this example, conventionally, the stored data of “address D102 to address D105” is acquired periodically. Then, the stored data at address D108 is acquired irregularly (suddenly) with the logic processing. Therefore, conventionally, if the access process to the address D108 is frequently performed, the access process to the "address D102 to address D105" is affected, and both the refresh process and the logic process may be delayed.

  On the other hand, in this method, when the irregular access destination is upgraded, the access destination should be “address D102 to address D108” in the optimum command list 54 generated by the optimum command generation unit 69. is there. Therefore, the stored data of “address D102 to address D108” are collectively acquired from the connected device 4 in one communication. Therefore, the conventional problem described above can be solved.

  Conventionally, every time access processing to the address D108 occurs, it is necessary to request access processing by storing the command 130 in the command list 53, for example, and wait until data is acquired. It was. On the other hand, in this method, it is only necessary to read data stored in the shared memory 55 along with the periodic refresh process, so that the processing efficiency related to the logic process is improved.

Claims (9)

A programmable display connected to any connected device,
Item information storage means for storing access information indicating each access destination corresponding to each item on the display screen;
First data acquisition means for periodically acquiring data from each access destination in the connected device based on the access information and storing the data in an internal memory;
When arbitrary logic processing is executed and access processing to an irregular access destination that is an access destination accompanying the logic processing occurs, it is determined whether or not the irregular access destination is integrated into the access information. When the irregular access destination is integrated with the access information, logic processing execution means for acquiring data corresponding to the irregular access destination from the internal memory;
A rating means that sets the irregular access destination whose access frequency is equal to or higher than a predetermined first threshold every time a predetermined period elapses as an upgraded state access destination;
An integration unit that integrates the non-periodic access destination that is the above-mentioned upper-level access destination into the access information;
A programmable display device comprising:   When the logic processing execution unit determines that the irregular access destination is not integrated with the access information, the logic processing execution unit further includes a second data acquisition unit that acquires data from the irregular access destination in the connected device. The programmable display device according to claim 1.   The first data acquisition unit acquires data from each irregular access destination and stores it in the internal memory when any one or more irregular access destinations are integrated into the access information. The programmable display device according to claim 1.   The logic processing execution unit relates to the irregular access destination every time access processing to the irregular access destination occurs regardless of whether or not the irregular access destination is integrated into the access information. The programmable display according to claim 1, wherein the access frequency is updated.   The rating means, when the access frequency related to the irregular access destination that is the upgraded access destination is less than a predetermined second threshold, does not integrate the access information by downgrading The programmable display device according to claim 1. Further comprising access optimization means for generating the optimized access information based on each access destination corresponding to each item on the display screen,
The integration unit is configured to cause the optimization unit to execute the optimization process based on each access destination corresponding to each item on the display screen and the upgraded state access destination, so that the optimized access information is obtained. Is regenerated,
2. The programmable display device according to claim 1, wherein the first data obtaining unit obtains the data and stores the data in the internal memory based on the regenerated optimized access information. 3. .   The apparatus further comprises item display control means for controlling display contents of each item on the display screen using data of each access destination corresponding to each item acquired by the first data acquisition means. The programmable display according to claim 1.   2. The programmable display according to claim 1, wherein each access destination is an arbitrary address in an arbitrary memory device in an arbitrary connected device. Programmable display computer connected to any connected device
Item information storage means for storing access information indicating each access destination corresponding to each item on the display screen;
First data acquisition means for periodically acquiring data from each access destination in the connected device based on the access information and storing the data in an internal memory;
When arbitrary logic processing is executed and access processing to an irregular access destination that is an access destination accompanying the logic processing occurs, it is determined whether or not the irregular access destination is integrated into the access information. When the irregular access destination is integrated with the access information, logic processing execution means for acquiring data corresponding to the irregular access destination from the internal memory;
A rating means that sets the irregular access destination whose access frequency is equal to or higher than a predetermined first threshold every time a predetermined period elapses as an upgraded state access destination;
Integration means for integrating the irregular access destination that is the above-mentioned access status destination into the access information;
Program to function as.

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