JPWO2014102924A1 - Bit determination circuit, bit string data selection circuit, and bit string data selection method - Google Patents

Abstract

In order to output information for selecting bit string data from a plurality of bit string data at high speed, the bits in the same bit position of the plurality of bit string data and the bits in the search bit string are sequentially compared from the most significant to the least significant. Bit string data that matches the search bit string with the bit string data to which the bit selected at the least significant bit position belongs by excluding the bit string data bit whose bit did not match the bit of the search bit string from the comparison target. And

Description

The present invention relates to a bit determination circuit that determines a bit at the same bit position of a plurality of bit string data, and a bit string data selection that outputs information for selecting bit string data among the plurality of bit string data using the bit determination circuit The present invention relates to a circuit and a bit string data selection method.

In the technical field of information processing, obtaining bit string data satisfying a certain condition from a plurality of bit string data, for example, bit string data matching a certain search bit string is performed. For example, as shown in Patent Document 1 below, the processing for obtaining bit string data that matches the search bit string is to read bit string data one by one from the memory storing the bit string data to be searched and compare it with the search bit string. Has been executed by.

FIG. 1 is a diagram for explaining a processing example of the above-described conventional search processing.
In the example of the search process shown in FIG. 1, the bit string data group 101, which is a set of a plurality of bit string data, is composed of four bit string data, D1, D2, D3, and D4. 111, D2 = 010, D3 = 011, and D4 = 100. The search bit string S260 is “010”.

As shown in FIG. 1, in step 1, for example, the bit string data D1 positioned at the head indicated by the arrow 111a in the bit string data is matched with the search bit string S260 121a, and the bit string data D1 does not match the search bit string S. It is determined.

Next, in step 2, a match determination 121b between the next bit string data D2 indicated by the arrow 111b and the search bit string S260 is performed, and it is determined that the bit string data D2 matches the search bit string S.

Next, in step 3, a match determination 121c between the next bit string data D3 indicated by the arrow 111c and the search bit string S260 is performed, and it is determined that the bit string data D3 does not match the search bit string S.

Finally, in step 4, a match determination 121d between the last bit string data D4 indicated by the arrow 111d and the search bit string S260 is performed, and it is determined that the bit string data D4 does not match the search bit string S.

The search process described above is executed using hardware suitable for the search, as described in the following patent document. Moreover, it is realizable by the process by software using CPU. In any case, however, the bit string data is read one by one from the memory storing the bit string data to be searched and is compared with the search bit string.

On the other hand, as disclosed in Patent Document 2 below, there is also known one that compares bit string data using a plurality of comparators corresponding to the number of bit string data to be processed in parallel.

JP-A-10-222535 JP 2010-224818 A

The search processing described in the above-mentioned Patent Document 1 reads out bit string data one by one from the memory storing the bit string data to be searched and compares it with the search bit string. Time increases.
Further, the bit string data comparison process described in Patent Document 2 requires a large number of comparators as the number of bit string data increases.

Therefore, the problem to be solved by the present invention is that the processing time does not increase in proportion to the increase in the bit string data to be processed, and the search bit string among the plurality of bit string data without the need for a large number of comparators. To provide a method for outputting information for selecting matching bit string data.

The first embodiment of the present invention is for an exact match search. According to one aspect of the first embodiment of the present invention, the same bit position i of each of N (N is an integer of 2 or more) bit string data whose bit length is m (m is an integer of 1 or more). (I = 0 to m−1) are bits taken out from (i = 0 to m−1), and each bit of the same position bit string composed of N bits corresponding to each bit string data and the bit position i of the search bit string having a bit length of m A bit comparison with the search bit is performed, and a determination bit string including a determination bit indicating whether or not the bit in the same position bit string matches the search bit is output. A bit string operation is performed on the selected bit string including the N selected bits corresponding to each bit string data and the determination bit string, each bit indicating whether or not each bit in the same position bit string is selected as a bit determination target. The bit extracted from the next bit position (i + 1) of the same bit position i of each bit string data and each bit of the next same position bit string composed of N bits corresponding to each bit string data This bit indicates whether or not to select as a determination target. Each bit string data includes N next selection bits corresponding to each bit string data. If it is a significant bit indicating selection as a target, it corresponds to the selected bit The constant bit is set as the next selection bit, and if the selection bit of the selected bit string is not a significant bit, the selection bit is output as the next selection bit, so that the bit at the same bit position i of the N bit string data is bit-determined. .

According to another aspect of the first embodiment of the present invention, the above bit determination is sequentially executed for the bit width of the bit string data. Then, the next selected bit string output by the bit determination for the bit at the same bit position (m−1) is output as information for selecting bit string data that completely matches the search bit string.

The second embodiment of the present invention is for partial match search. According to one aspect of the second embodiment of the present invention, each bit represents whether or not to exclude a bit in the same position bit string made up of bits extracted from the same bit position i from a bit determination target. A skip bit string composed of m skip bits corresponding to the same bit position i is given, and the skip bit is a significant bit indicating that the bits constituting the corresponding same position bit string are excluded from the bit determination target. For example, the selected bit string in the bit determination of the first embodiment is output as the next selected bit string, and if the skip bit is not a significant bit, the next selected bit string output by the bit determination of the first embodiment is next selected. By outputting as a bit string, the bit at the same bit position i of N bit string data is determined.

According to another aspect of the second embodiment of the present invention, the above bit determination is sequentially executed for the bit width of the bit string data. Then, the next selected bit string output by the bit determination for the bit at the same bit position (m−1) is output as information for selecting bit string data partially matching the search bit string.

The third embodiment of the present invention is for the longest match search. According to one aspect of the third embodiment of the present invention, it is determined whether or not the bits of the same position bit string selected by the selected bits of the selected bit string match all the corresponding search bits, and all the unmatched bits are output. . In addition, all the unmatched bits are significant bits indicating that all the bits in the same position bit string selected by the selected bits of the selected bit string do not match the corresponding search bits, or the same bit extracted from the bit string data. If all the bits in the same position bit string in the upper bit position do not match the corresponding search bits at the bit position higher than the bit position i, the selected bit string in the bit determination of the first embodiment is the next selected bit string. All the inconsistent bits are not significant, and all the bit positions in the same position bit string at the higher bit positions corresponding to all the bit positions higher than the same bit position i from which the bits are extracted from the bit string data If the bit does not match the search bit, the bit determination of the first embodiment By outputting the next selected bit string to be more outputted as the next selected bit string to determine identical bits at bit position i of the N-bit string data.

According to another aspect of the third embodiment of the present invention, the above bit determination is sequentially executed for the bit width of the bit string data. Then, the next selected bit string output by the bit determination with respect to the bit at the same bit position (m−1) is output as information for selecting the bit string data having the longest match with the search bit string.

According to the present invention, even if the number of bit string data to be processed increases, the processing time does not increase proportionally, and bit string data that matches the search bit string among a plurality of bit string data without requiring a large number of comparators. A method of outputting information for selection can be provided.
By using the technique provided by the present invention, it is possible to acquire bit string data that matches the search bit string from among a plurality of bit string data.

It is a figure explaining the conventional search process. It is a figure which illustrates notionally an example of the exact matching selection process in the 1st Embodiment of this invention. It is a figure which illustrates notionally another example of the exact matching selection process in the 1st Embodiment of this invention. FIG. 2 is a diagram conceptually illustrating a complete match selection circuit according to the first embodiment of the present invention. It is a figure explaining the Example of the bit determination circuit in the 1st Embodiment of this invention. It is a figure which illustrates notionally the partial matching selection process in the 2nd Embodiment of this invention. It is a figure which illustrates notionally the partial coincidence selection circuit in the 2nd Embodiment of this invention. It is a figure explaining the Example of the bit determination circuit in the 2nd Embodiment of this invention. It is a figure which illustrates notionally the longest match selection process in the 3rd Embodiment of this invention. It is a figure which illustrates notionally the longest match selection circuit in the 3rd Embodiment of this invention. It is a figure explaining the Example of the bit determination circuit in the 3rd Embodiment of this invention.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
FIG. 2A is a diagram conceptually illustrating an example of a complete match selection process according to the first embodiment of the present invention. In this example, the bit string data group 101 and the search bit string S260 illustrated in FIG. 2A are the same as those illustrated in FIG. In this example, the bit string data group 101 includes bit string data that completely matches the search bit string S.

As shown in FIG. 2A, in step 1, “1111” is set as the initial value in the selected bit string 210a. The initial value of the selected bit string is all “1111” in each embodiment described below. E1, E2, E3, and E4 described on the left side of the selected bit string 210a indicate bits of the selected bit string, and each bit of E1, E2, E3, and E4 corresponds to the bit string data D1, D2, D3, and D4, respectively. ing. If the bit Ex is “1”, the bit extracted from the corresponding bit string data Dx is selected as a bit determination target. As a mode of processing, as will be described later, the bit extracted from the bit string data Dx is subjected to bit determination by performing a bit operation on the bit representing the comparison result between the bit extracted from the bit string data Dx and the bit of the search bit string S. select. Therefore, in the following description, performing the above bit calculation sometimes means performing bit determination on the result of bit comparison. In addition, the selected bit string may be represented by the symbol E.

In the bit string data group 101, bit positions 0, 1, and 2 of each bit string data are shown. A bit string obtained by extracting bits surrounded by a dotted line for each bit position is defined as the same position bit string. By extracting the bits at bit positions 0, 1, and 2 of the bit string data D1, D2, D3, and D4, the same position bit strings F1 (240), F2 (241), and F3 (242) are configured. In step 2 and subsequent steps, reference numerals 240, 241, and 242 of the same bit string are omitted. In the following description, the same position bit string may be represented by the symbol F with the suffix omitted.

In FIG. 2A, the bit positions 0, 1, and 2 are also shown in the search bit string S260. The search bits at each bit position are denoted as S1, S2, and S3. In the following description, the search bit may be represented by the symbol S with the suffix omitted.

In step 1, as indicated by a bidirectional arrow 160a, each bit of the same position bit string F1 (240) is compared with the search bit S1 located at the bit position 0 of the search bit string S260. Furthermore, as indicated by a bidirectional arrow 220a, bit determination is performed on the result of the bit comparison 160a for each bit of the same position bit string F1 (240) by each corresponding selected bit of the selected bit string 210a.

In each embodiment of the present invention, by comparing each bit of the same position bit string with the search bit, the bit “1” represents the result of the comparison if they match and the bit “0” represents the result of the comparison if they do not match. In the bit determination, it is determined whether the result of bit comparison corresponding to the selected bit that is “1” in the selected bit string is “1”. Based on this determination result, the next selected bit string used as the selected bit string in the next step is output. In the following description, the bits constituting the next selection bit string may be referred to as selection bits instead of the next selection bits.

If it is determined in the above determination that the result of the bit comparison is “1”, the next selected bit of the next selected bit string corresponding to the same bit string data as the bit string data corresponding to the selected bit of “1” is “1”. If the result of bit comparison is determined to be “0”, the next selected bit of the next selected bit string corresponding to the same bit string data as the bit string data corresponding to the selected bit of “1” is set to “0”. To do. Further, the next selection bit of the next selection bit string corresponding to the same bit string data as the bit string data corresponding to the selection bit of “0” is set to “0”, that is, the above-described selection bit of “0”.

In the example of FIG. 2A, the search bit S1 is “0”, the same position bit string F1 (240) is “1001”, and the selected bit string 210a is “1111”. Therefore, as shown by the dotted arrow 230a, The next selection bit string 211a is “0110”.

In the next step 2, as indicated by the bidirectional arrow 160b, each bit of the same position bit string F2 (241) is compared with the search bit S2 located at the bit position 1 of the search bit string S260. Further, as indicated by a bidirectional arrow 220b, the next selected bit string 211a, which is the determination result in step 1, is used as the selected bit string 210b and selected for the result of the bit comparison 160b for each bit of the same position bit string F2 (241). Bit determination is performed by each selection bit corresponding to the bit string 210b.

In the example of FIG. 2A, the search bit S2 is “1”, the same-position bit string F2 (241) is “1110”, and the selected bit string 210b is “0110”. Therefore, as shown by the dotted arrow 230b, The next selection bit string 211b is “0110”.

In the next step 3, as indicated by the bidirectional arrow 160c, each bit of the same position bit string F3 (242) is compared with the search bit S3 located at the bit position 2 of the search bit string S260. Further, as indicated by a two-way arrow 220c, the next selected bit string 211b, which is the determination result in step 2, is used as the selected bit string 210c and selected for the result of the bit comparison 160c for each bit of the same position bit string F3 (242). Bit determination is performed by each corresponding selection bit of the bit string 210c.

In the example of FIG. 2A, the search bit S3 is “0”, the same-position bit string F3 (242) is “1010”, and the selected bit string 210c is “0110”. Therefore, as shown by the dotted arrow 230c, The next selection bit string 211c is “0100”.

Since the determination of the bits up to the lowest bit position is completed by the processing up to step 3, “the next selection bit string 211c is information for selecting bit string data that completely matches the search bit string S.
In the example of FIG. 2A, as indicated by the arrow 250, only the selection bit E2 is “1”, and it can be seen that the bit string data D2 corresponding to the selection bit E2 is bit string data that completely matches the search bit string S.

If the above processing steps are compared to the winning competition, it is determined from the most significant bit to the least significant bit of the bit string data whether the bit at the same bit position of the winning bit string data matches the search bit of the search bit string S, This is equivalent to selecting the remaining bit string data with the matching bit string data as the winner and the unmatched bit string data as the loser. However, in the data processing, the bit comparison with the search bit is performed first, and it is next determined whether or not the bit string data corresponding to the matched bit at the same bit position has been won.

In the above description, if the selected bit Ex is “1”, the bit extracted from the corresponding bit string data Dx is selected as a bit determination target. However, if the selected bit Ex is “0”, It is obvious that the complete match selection process can be performed even when the bit extracted from the corresponding bit string data Dx is selected as the bit determination target. Therefore, the selection bit Ex indicating that the bit extracted from the bit string data Dx is selected as a bit determination target is a significant bit, or the selected bit Ex is a significant bit, and the bit extracted from the bit string data Dx. May not be a significant bit.

Furthermore, in the above description, the match of the bit comparison results is represented by bit “1” and the mismatch is represented by bit “0”. However, it is obvious that this can be reversed. Therefore, as will be described later, a bit representing the result of bit comparison is defined as a decision bit, and a decision bit representing coincidence is a significant bit or is significant, and indicates that the comparison result is inconsistent. The decision bit may not be significant or not significant.

Furthermore, the same bit string data may be included in the bit string data group. In this case, there is a possibility that a plurality of bits “1” exist in the next selected bit string that is the output of the bit determination at the least significant bit position.
The description about the overlap of the selection bit, the determination bit, and the bit string data described above is not limited to the first embodiment, and similarly applies to the second embodiment and the third embodiment described later.

FIG. 2B is a diagram conceptually illustrating another example of the exact match selection process according to the first embodiment of the present invention. The bit string data group 101 illustrated in FIG. 2B is the same as that illustrated in FIG. 2A. The search bit string S261 described in FIG. 2B is “001”, which is different from the search bit string S260 described in FIG. 2A. 2B, the bit string data group 101 does not include bit string data that completely matches the search bit string S261.

In step 1, as indicated by a bidirectional arrow 161a, each bit of the same position bit string F1 (240) is compared with the search bit S1 located at the bit position 0 of the search bit string S261. Further, as indicated by a bidirectional arrow 221a, bit determination is performed on the result of the bit comparison 161a for each bit of the same position bit string F1 (240) by each corresponding selected bit of the selected bit string 212a.

In the example of FIG. 2B, the search bit S1 is “0”, the same position bit string F1 (240) is “1001”, and the selected bit string 212a is “1111”. The next selection bit string 213a is “0110”.

In the next step 2, as indicated by the bidirectional arrow 161b, each bit of the same position bit string F2 (241) is compared with the search bit S2 located at the bit position 1 of the search bit string S261. Further, as indicated by the bidirectional arrow 221b, the next selected bit string 213a, which is the determination result in step 1, is used as the selected bit string 212b, and is selected for the result of the bit comparison 161b for each bit of the same position bit string F2 (241). Bit determination is performed by each corresponding selection bit of the bit string 212b.

In the example of FIG. 2B, the search bit S2 is “0”, the same-position bit string F2 (241) is “1110”, and the selected bit string 210b is “0110”, so that the determination result is as shown by the dotted arrow 231b. The next selection bit string 213b is “0000”.

In the next step 3, as indicated by a bidirectional arrow 161c, each bit of the same position bit string F3 (242) is compared with the search bit S3 located at the bit position 2 of the search bit string S261. Further, as indicated by a bidirectional arrow 221c, the next selected bit string 213b, which is the determination result in step 2, is used as the selected bit string 212c, and is selected for the result of the bit comparison 161c for each bit of the same position bit string F3 (242). Bit determination is performed by each corresponding selection bit of the bit string 212c.

In the example of FIG. 2B, the search bit S3 is “1”, the same-position bit string F3 is “1010”, and the selection bit string 212c is “0000”, so that the next selected bit string of the determination result is indicated by a dotted arrow 231c. 213c becomes “0000”.

Since the determination of the bits up to the lowest bit position is completed by the processing up to step 3, “the next selection bit string 213c becomes information for selecting bit string data that completely matches the search bit string S”.
In the example of FIG. 2B, as indicated by the arrow 250-1, there is no selection bit that is “1”, and therefore, there is no case in the bit string data group that corresponds to the bit string data that completely matches the search bit string S. I understand.

Next, a circuit according to the first embodiment of the present invention will be described with reference to FIGS. In FIG. 3 and FIG. 4, the description of the same parts as in FIG. 2A and FIG. 2B is omitted.

FIG. 3 is a diagram conceptually illustrating the exact match selection circuit in the first embodiment of the present invention.
In the data register group 301 illustrated in FIG. 3, the bit string data group 101 illustrated in FIGS. 2A and 2B is stored. The search bit register 370 stores the search bit string S260 illustrated in FIG. 2A. The selection bit register 310 stores an initial value “1111” of the selection bit string.

As shown in FIG. 3, the exact match selection circuit 300a includes a bit determination circuit 320a corresponding to the same position bit string F1 (240), a bit determination circuit 320b corresponding to the same position bit string F2 (241), and a same position bit string F3 (242). ) Corresponding to the bit determination circuit 320c. These bit determination circuits can basically use the same configuration.

The same-position bit strings F1, F2, and F3 from which the bits at the same bit positions of the bit string data D1, D2, D3, and D4 stored in the data register group 301 are extracted are respectively obtained by 4-bit parallel buses 340a, 340b, and 340c. Input to the bit determination circuits 320a, 320b, and 320c. In the bit determination circuits 320a, 320b, and 320c, steps 1, 2, and 3 shown in FIG. 2A are executed.

The selected bit string stored in the selected bit register 310 is input to the bit determination circuit 320a through the 4-bit parallel bus 330a. The bit determination result output 310b of the bit determination circuit 320a is input to the bit determination circuit 320b through the 4-bit parallel bus 330b. Next, the bit determination result output 310c of the bit determination circuit 320b is input to the bit determination circuit 320c through the 4-bit parallel bus 330c. Further, the bit determination result output of the bit determination circuit 320c is input to the selection result register 360 through the 4-bit parallel bus 330d.

In the example of FIG. 3, the selection result register 360 stores the next selection bit string 211 c shown in FIG. 2A, and as indicated by the arrow 350, the search is performed by storing the bit string data D2 corresponding to the bit E <b> 2 in the search bit string register 370. It can be seen that the bit string S completely matches.

FIG. 4 is a diagram for explaining an example of the bit determination circuit according to the first embodiment of the present invention. FIG. 4A shows a circuit configuration of an example of the bit determination circuit according to the first embodiment of the present invention. This circuit configuration is common to the bit determination circuits 320a, 320b, and 320c shown in FIG. FIG. 4B illustrates the input / output logic of the constituent elements of the bit determination circuit according to the first embodiment of the present invention. In the following description, it is assumed that the bit string data group includes n bit string data. Each bit of the n-bit parallel bus may be represented by a subscript x.

As shown in FIG. 4A, the bit determination circuit 320 includes a bit comparator 410 and a next selection bit setting unit 420. The bit determination circuit 320 receives the same-position bit string F from the n-bit parallel bus 340, receives the selected bit string E from the n-bit parallel bus 330, and receives the search bit S from the single bit bus 341. .

The input same-position bit string F and search bit S are input to the bit comparator 410, and a determination bit string P including the above-described determination bits is obtained by logical operation of each bit of the same-position bit string F and the search bit S. It is done. The determination bit string P and the selection bit string E are input to the next selection bit string setting unit 420. The next selected bit string setting unit 420 performs a logical operation for each bit of the determination bit string P and the selected bit string E to obtain a new bit string Q. The bit string Q is output to the n-bit parallel bus 331 as the next selected bit string. As described above, obtaining a new bit string having the same bit width by a logical operation for each bit of a bit string, or obtaining one bit may be referred to as a bit string operation.

FIG. 4B shows logical expressions of the bit string operation P of the bit comparator 410 and the bit string operation Q of the next selected bit string setting unit 420 in the first embodiment of the present invention. The symbol “*” represents a logical product.

The bit Px of the bit string P, which is the output of the bit string operation of the bit comparator 410, is the logical product of the logical negation of the bit Fx of the same position bit string F and the logical negation of the search bit S, and the logical product of the bit Fx and the search bit S. Is the exclusive OR of the bit Fx and the search bit S, and is “1” when the bit Fx and the search bit S match, and “0” when they do not match.

The bit Qx of the bit string Q, which is the output of the bit string operation of the next selected bit string setter 420, is the logical product of the above Px and Ex. That is, when the selection bit Ex is “1”, Qx is Px, and when the selection bit Ex is “0”, Qx is “0”, that is, Ex.
The bit determination of each bit of the same position bit string F with respect to the search bit S is performed by the bit string calculation P and the bit string calculation Q described above, and the next selection bit string is output from the bit determination circuit 320.

Next, a second embodiment of the present invention will be described with reference to FIGS. This second embodiment relates to partial match selection.
FIG. 5 is a diagram conceptually illustrating the partial match selection process in the second embodiment of the present invention. As shown in FIG. 5, the bit string data group 101 and the search bit string S261 are the same as those described in FIG. 2B. Therefore, description of similar parts is omitted.

FIG. 5 shows a skip bit string K280 made up of skip bits indicating the bit positions of the bits of the bit string data Dx for which the identity determination with the search bit S is not performed. The skip bit K1 at bit position 0 is “0”, the skip bit K2 at bit position 1 is “1”, and the skip bit K3 at bit position 2 is “0”.

In the following description, it is assumed that the skip bit “1” indicates that the identity of the bit string data Dx corresponding to the bit position of the skip bit and the search bit S is not determined. It is obvious to those skilled in the art that "" may indicate that the identity of the bit string data Dx corresponding to the bit position of the skip bit and the search bit S is not determined. Therefore, similarly to the selected bit or the like, a skip bit indicating that the identity of the bit string data Dx and the search bit S is not determined is a significant bit, or the skip bit is a significant bit. The skip bit indicating that the determination of the identity between the bit string data Dx and the search bit S is not skipped may not be a significant bit. In the following description, the skip bit may be represented by the symbol K with the suffix omitted.

In step 1, as indicated by a bidirectional arrow 162a, each bit of the same position bit string F1 (240) is compared with the search bit S1 located at the bit position 0 of the search bit string S261. Further, as indicated by a bidirectional arrow 222a, bit determination is performed on the result of bit comparison 162a for each bit of the same position bit string F1 (240) by each corresponding selected bit of the selected bit string 214a.

In the example of FIG. 5, the search bit S1 is “0”, the same position bit string F1 (240) is “1001”, the selection bit string 214a is “1111”, and the skip bit K1 is “0”. As indicated by the arrow 292a, the determination result indicated by the dotted arrow 232a is output, and the next selected bit string 215a becomes “0110”.

In the next step 2, as indicated by a bidirectional arrow 162b, each bit of the same position bit string F2 (241) is compared with the search bit S2 “0” located at the bit position 1 of the search bit string S261. However, since the skip bit K2 is “1” in the example of FIG. 5, the comparison result is ignored or the bit determination is skipped without being compared, and the determination in step 1 is performed as indicated by the dotted arrows 292b and arrows 272b. The selected bit string 214b using the resulting next selected bit string 215a is used as the next selected bit string 215b that is the output of step 2.

In the next step 3, as indicated by a bidirectional arrow 162c, each bit of the same position bit string F3 (242) is compared with the search bit S3 located at the bit position 2 of the search bit string S261. Further, as indicated by a bidirectional arrow 222c, the next selected bit string 214b, which is the determination result in step 2, is used as the selected bit string 214c, and is selected for the result of the bit comparison 162c for each bit of the same position bit string F3 (242). Bit determination is performed by each corresponding selection bit of the bit string 214c.

In the example of FIG. 5, the search bit S3 is “1”, the same position bit string F3 (242) is “1010”, the selection bit string 214c is “0110”, and the skip bit K2 is “0”. As indicated by the arrow 292c, the determination result indicated by the dotted arrow 232c is output, and the next selected bit string 215c becomes “0010”.

Since the determination of the bits up to the least significant bit position is completed by the processing up to step 3, “the next selection bit string 215c is information for selecting bit string data partially matching the search bit string S.
In the example of FIG. 5, as indicated by the arrow 251, it can be seen that the selection bit E3 is “1” and the bit string data D3 corresponding to the selection bit E3 is bit string data that partially matches the search bit string S.

Next, a circuit according to a second embodiment of the present invention will be described with reference to FIGS. 6 and 7, the description of the same part as in FIG. 5 is omitted.

FIG. 6 is a diagram conceptually illustrating a partial match selection circuit according to the second embodiment of the present invention.
In the data register group 301 illustrated in FIG. 6, the bit string data group 101 illustrated in FIG. 5 is stored. The search bit register 370 stores the search bit string S261 illustrated in FIG. The skip bit register 380 stores the skip bit string K280 illustrated in FIG. The selection bit register 310 stores an initial value “1111” of the selection bit string.

As shown in FIG. 6, the partial match selection circuit 300b includes a bit determination circuit 321a corresponding to the same position bit string F1 (240), a bit determination circuit 321b corresponding to the same position bit string F2 (241), and the same position bit string F3 (242). ) Corresponding to the bit determination circuit 321c. These bit determination circuits can basically use the same configuration.

The same-position bit strings F1, F2, and F3 from which the bits at the same bit positions of the bit string data D1, D2, D3, and D4 stored in the data register group 301 are extracted are respectively obtained by 4-bit parallel buses 342a, 342b, and 342c. Input to the bit determination circuits 321a, 321b, and 321c. In the bit determination circuits 321a, 321b, and 321c, steps 1, 2, and 3 shown in FIG. 5 are executed.

The selected bit string stored in the selected bit register 310 is input to the bit determination circuit 321a through the 4-bit parallel bus 331a. The bit determination result output 313b of the bit determination circuit 321a is input to the bit determination circuit 321b through a 4-bit parallel bus 331b. Next, the bit determination result output 313c of the bit determination circuit 321b is input to the bit determination circuit 321c through the 4-bit parallel bus 331c. Further, the bit determination result output of the bit determination circuit 321c is input to the selection result register 360 via the 4-bit parallel bus 331d.

In the example of FIG. 6, the selection result register 360 stores the next selected bit string 215 c shown in FIG. 5, and the bit string data D <b> 3 corresponding to the bit E <b> 3 is stored in the search bit string register 370 as indicated by the arrow 351. It can be seen that the bit string S partially matches.

FIG. 7 is a diagram illustrating an example of the bit determination circuit according to the second embodiment of the present invention. FIG. 7A shows a circuit configuration of an example of the bit determination circuit according to the second embodiment of the present invention. This circuit configuration is common to the bit determination circuits 321a, 321b, and 321c shown in FIG. FIG. 7B illustrates the input / output logic of the constituent elements of the example of the bit determination circuit according to the second embodiment of the present invention.

As shown in FIG. 7A, the bit determination circuit 321 includes a bit comparator 410, a next selection bit setting unit 420, and a determination result selection unit 440. The bit determination circuit 321 receives the same position bit string F through the n-bit parallel bus 342, receives the selection bit string E through the n-bit parallel bus 331, and further receives the search bit S through the single bit bus 343. The skip bit K is input by the single bit bus 381.

The bit comparator 410 and the next selection bit setter 420 shown in FIG. 7A are the same as those described in FIG. 4A, and therefore their input / output logic is also the same. The description of the logical expressions shown in FIG. 7 and the next selection bit setting unit 420 and FIG.
If the skip bit K is significant, the determination result selector 440 sets the selected bit string E as the output bit string Z. If the skip bit K is not significant, the determination result selector 440 converts the bit string Q output from the next selected bit setter 420 into the output bit string Z. And This output bit string Z is output from the bit determination circuit 321 as the next selected bit string.

Next, a third embodiment of the present invention will be described with reference to FIGS. This third embodiment relates to the longest match selection. The longest match here means that the bit length from the most significant bit of the bit string data matching the most significant bit of the search bit string is the longest.
FIG. 8 is a diagram conceptually illustrating the longest match selection process in the third embodiment of the present invention. As shown in FIG. 8, the bit string data group 101 and the search bit string S261 are the same as those described in FIG. 2B. Therefore, description of similar parts is omitted.

In step 1, as indicated by a bidirectional arrow 163a, each bit of the same position bit string F1 (240) is compared with the search bit S1 located at the bit position 0 of the search bit string S261. Further, as indicated by a bidirectional arrow 224a, bit determination is performed on each bit corresponding to the selected bit string 216a with respect to the result of the bit comparison 163a for each bit of the same position bit string F1 (240).

In the example of FIG. 8, the search bit S1 is “0”, the same-position bit string F1 (240) is “1001”, and the selected bit string 216a is “1111”. Therefore, as shown by the dotted arrow 234a, The next selection bit string 217a is “0110”.

In the next step 2, as indicated by the bidirectional arrow 163b, each bit of the same position bit string F2 (241) is compared with the search bit S2 located at the bit position 1 of the search bit string S261. Further, as indicated by a bidirectional arrow 224b, the next selected bit string 217a that is the determination result in step 1 is used as the selected bit string 216b, and is selected for the result of the bit comparison 163b for each bit of the same position bit string F2 (241). Bit determination is performed by each corresponding selection bit of the bit string 216b.

In the example of FIG. 8, the search bit S2 is “0”, the same position bit string F2 (241) is “1110”, and the selected bit string 216b is “0110”. Therefore, as shown by the dotted arrow 234b, The next selection bit string 217b-1 is “0000”, and there is no bit string data in which all the bits from the search bit string S to the bit position 0 to the bit position 1 match.

Therefore, the selected bit string 216b is output as the next selected bit string 217b in step 2, as indicated by the dotted arrow 235b and the arrow 224b-1. In step 2, there is no bit string data in which all the bits from bit position 0 to bit position 1 which are the most significant bit positions match the search bit string S, that is, there is no bit string data that completely matches the search bit string S. The history determined as (hereinafter also referred to as determination history) is inherited by step 3 as indicated by the dotted arrow 235c.

In the next step 3, as indicated by a bidirectional arrow 163c, each bit of the same position bit string F3 (242) is compared with the search bit S3 located at the bit position 2 of the search bit string S261. Further, as indicated by the bidirectional arrow 224c, the next selected bit string 217b, which is the determination result in step 2, is used as the selected bit string 216c, and is selected for the result of the bit comparison 163c for each bit of the same position bit string F3 (242). Bit determination is performed by each corresponding selection bit of the bit string 216c.

In the example of FIG. 8, the search bit S3 is “1”, the same-position bit string F3 (242) is “1010”, and the selected bit string 216c is “0110”. Therefore, as shown by the dotted arrow 234c, The next selection bit string 217c-1 is “0010”.
However, since the determination history in step 2 is inherited by step 3 as indicated by the dotted arrow 235c, the selected bit string 217b is output as the next selected bit string 217c in step 3 as indicated by the arrow 224c-1. .

Since the determination of the bits up to the lowest bit position is completed by the processing up to step 3, “the next selection bit string 217c is information for selecting the bit string data that has the longest match with the search bit string S.
In the example of FIG. 8, as indicated by an arrow 252, the selection bits E2 and E3 are “1”, and the bit string data D2 and D3 corresponding to the selection bits E2 and E3 are the bit string data that is the longest match with the search bit string S. I understand that.

Next, a circuit according to a third embodiment of the present invention will be described with reference to FIGS. In FIG. 9 and FIG. 10, the description of the same part as FIG. 8 is omitted. In the following description, the bit indicating the presence / absence of the determination history described with reference to FIG. 8 is referred to as a history bit, and the history bit indicating that there is a determination history is referred to as a significant bit, or the history bit is significant. Sometimes. In addition, a history bit indicating that there is no determination history may not be a significant bit or may not be significant.

FIG. 9 is a diagram conceptually illustrating the longest match selection circuit in the third embodiment of the present invention.
In the data register group 301 illustrated in FIG. 9, the bit string data group 101 illustrated in FIG. 8 is stored. The search bit register 370 stores the search bit string S261 illustrated in FIG. The selection bit register 310 stores an initial value “1111” of the selection bit string.

As shown in FIG. 9, the longest match selection circuit 300c includes a bit determination circuit 324a corresponding to the same position bit string F1 (240), a bit determination circuit 324b corresponding to the same position bit string F2 (241), and the same position bit string F3 (242). ) Corresponding to the bit determination circuit 324c. These bit determination circuits can basically use the same configuration.

The same-position bit strings F1, F2, and F3 from which the bits at the same bit position of the bit string data D1, D2, D3, and D4 stored in the data register group 301 are extracted are respectively obtained by 4-bit parallel buses 344a, 344b, and 344c. Input to the bit determination circuits 324a, 324b, 324c. In the bit determination circuits 324a, 324b, and 324c, the processes of steps 1, 2, and 3 shown in FIG. 8 are executed.

The selected bit string stored in the selected bit register 310 is input to the bit determination circuit 324a through the 4-bit parallel bus 334a. Further, the history bit indicating the presence / absence of the determination history corresponds to the same position bit string for the most significant bit position by the bit determination circuit 324a. Therefore, the history bit is not significant as an initial value. In the example of FIG. "Is input to the bit determination circuit 324a by the single bit bus 335a. The bit determination result output 314b of the bit determination circuit 324a is input to the bit determination circuit 324b through a 4-bit parallel bus 334b. A history bit indicating the presence / absence of the determination history of the bit determination circuit 324a is input to the bit determination circuit 324b through the single bit bus 335b. Next, the bit determination result output 314c of the bit determination circuit 324b is input to the bit determination circuit 324c through the 4-bit parallel bus 334c. The history bit output from the bit determination circuit 324b is input to the bit determination circuit 324c through the single bit bus 335c. Further, the bit determination result output of the bit determination circuit 324c is input to the selection result register 360 through the 4-bit parallel bus 334d.

In the example of FIG. 9, the selection result register 360 stores the next selection bit string 217c shown in FIG. 8, and as shown by the arrow 352, the bit string data D2 corresponding to the bit E2 and the bit string data D3 corresponding to the bit E3 are stored. It can be seen that the search bit string S stored in the search bit string register 370 is the longest match.

FIG. 10 is a diagram illustrating an example of the bit determination circuit according to the third embodiment of the present invention. FIG. 10A shows a circuit configuration of an example of the bit determination circuit according to the third embodiment of the present invention. FIG. 10B illustrates the input / output logic of the components of the example of the bit determination circuit in the third embodiment of the present invention.

As shown in FIG. 10A, the bit determination circuit 324 includes a bit comparator 410, a next selection bit setting unit 420, an all mismatch determination unit 430, a determination result selection unit 440, and an OR circuit 470. The bit determination circuit 324 receives the same position bit string F through the n-bit parallel bus 344, receives the selection bit string E through the n-bit parallel bus 334, and further receives the search bit S through the single bit bus 345. The history bit M is input by the single bit bus 335.

The bit comparator 410 and the next selection bit setter 420 shown in FIG. 10A are the same as those described in FIG. 7A, and therefore their input / output logic is also the same. The description of the logical expressions of Px and Qx shown in FIG.
The determination result selector 440 shown in FIG. 10A is different from that shown in FIG. 7A in that the bit input to the selector terminal s is not the skip bit K, and the input and output are the same. It is. That is, only the input switching logic is different.

The total mismatch determination unit 430 performs a bit string operation on the determination bit string P and the selected bit string E according to the logical expression shown in FIG. The total mismatch bit R is a logical negation of the logical product of Px and Ex for each bit and the logical product of all bits. The value of R is “1” only when Px is “0” for all bits where Ex is “1”, and there is at least one bit where Ex is “1” and Px is “1”. In this case, it is “0”. That is, when all the determination bits corresponding to the bits of the same position bit string in which the corresponding selected bits are significant are not significant, in other words, only when all the bits of the same position bit string do not match the corresponding search bits, R is “1”.

All mismatch bits R and history bit M are input to OR circuit 470. The output U of the OR circuit 470, which is the logical sum of all the mismatch bits R and the history bit M, is output as a history bit from the bit determination circuit 324 via the single bit bus 335-1 and also the determination result via the line 335-2. The signal is input to the selector terminal s of the selector 440.
If the output U of the OR circuit 470 is “0”, the determination result selector 440 sets the bit string Q that is the output of the next selection bit setting unit 420 as the output bit string Z, and the output U of the OR circuit 470 is “1”. For example, the selected bit string E is set as the output bit string Z. This output bit string Z is output from the bit determination circuit 324 as the next selected bit string through the n-bit parallel bus 331.

When an exceptional input that the most significant bit of all bit string data belonging to the bit string data group does not match the most significant bit of the search bit string is assumed, the bit determination circuit 320 shown in FIG. Is used to determine the coincidence of the most significant bit of the bit string data, and the determination result output is input to the bit determination circuit 324a through the 4-bit parallel bus 334a instead of the selection bit register 310 as the selected bit string. do it.

As described above, the embodiments of the present invention have been described in detail, and according to the present invention, a circuit for selecting bit string data from a bit string data group can be configured by a passive circuit, so that high-speed operation is possible. Moreover, it will be apparent to those skilled in the art that various modifications can be made to the embodiment of the present invention in addition to the above description.
In addition to the bit determination circuit and bit string data selection circuit described in detail, the embodiment of the present invention includes a bit string data selection method according to the processing steps described in FIGS. 2A, 5, and 8. Although these bit string data selection methods have been described as being executed by a hardware circuit, it is obvious to those skilled in the art that these bit string data selection methods can be realized by software on a computer.

Claims (9)

Bit determination circuit for determining bits at the same bit position i (i = 0 to m−1) of N (N is an integer of 2 or more) bit string data having a bit length of m (m is an integer of 1 or more) In
Bits extracted from the same bit position i of each of the bit string data, each bit of the same position bit string consisting of N bits corresponding to each bit string data, and the bit position i of the search bit string whose bit length is m A bit comparator that outputs a determination bit string including a determination bit that indicates whether or not the bit in the same position bit string matches the search bit;
It is a bit indicating whether or not to select each bit of the same position bit string as an object of bit determination, and a bit string operation between a selection bit string composed of N selection bits corresponding to each bit string data and the determination bit string The bit extracted from the bit position (i + 1) next to the same bit position i of each bit string data, and each bit of the next same position bit string composed of N bits corresponding to each bit string data , And a next selection bit setter that outputs a next selection bit string composed of N next selection bits corresponding to each bit string data,
The next selected bit setter sets the determination bit corresponding to the selected bit if the selected bit of the selected bit string is a significant bit indicating that the bit of the same position bit string is selected as a bit determination target. A bit determination circuit, characterized in that the bit is a selection bit, and if the selection bit of the selection bit string is not a significant bit, the selection bit is the next selection bit. Bit string data for selecting bit string data that matches a search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more) In the selection circuit,
The bit determination circuit according to claim 1, wherein the next selection bit string output from the bit determination circuit for determining the bit at the same bit position i is selected as the bit determination circuit for determining the bit at the same bit position (i + 1). Connect m stages in series to input as a bit string,
A bit string data selection circuit for outputting a next selection bit string, which is an output of an m-th stage bit determination circuit, as information for selecting bit string data matching the search bit string. The bit determination circuit according to claim 1,
A judgment result selector;
The determination result selector is a bit indicating whether or not to exclude a bit of the same position bit string made up of bits extracted from the same bit position i from the object of bit determination, and corresponds to the same bit position i. If the skip bit of the skip bit string composed of m skip bits is a significant bit indicating that the bit constituting the corresponding same-position bit string is excluded from the bit determination target, the next selection bit setter is The selected bit string is output as the next selected bit string instead of the next selected bit string to be output, and if the skip bit is not a significant bit, the next selected bit string output by the next selected bit setter is output as the next selected bit string A bit determination circuit characterized by: Bit string for selecting bit string data partially matching a search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more) In the data selection circuit,
The bit determination circuit according to claim 3, wherein the next selection bit string which is an output of the bit determination circuit for determining the bit at the same bit position i is selected by the bit determination circuit for determining the bit at the same bit position (i + 1). Connect m stages in series to input as a bit string,
A bit string data selection circuit for outputting a next selection bit string, which is an output of an m-th stage bit determination circuit, as information for selecting bit string data partially matching the search bit string. The bit determination circuit according to claim 1,
A total discriminator and a judgment result selector;
The all mismatch judgment unit judges whether all the bits of the same position bit string selected by the selection bit of the selected bit string are logical negation of the judgment bit, and outputs a judgment result as a whole mismatch bit,
The determination result selector is a significant bit indicating that the all unmatched bits do not match all the search bits corresponding to the bits of the same position bit string selected by the selected bits of the selected bit string, or If the bit in the same bit position at the upper bit position does not match all corresponding search bits at the bit position higher than the same bit position i from which the bit has been extracted from the bit string data, the next selection bit setter The selected bit string is output as the next selected bit string in place of the next selected bit string output from the above, and the all unmatched bits are not significant and are higher than the same bit position i from which the bit is extracted from the bit string data. In all the bit positions, the bit in the same position bit string in the upper bit position corresponds. If matches any search bit, to output the next selection bit string, which is the output of the next selected bit setter,
A bit determination circuit characterized by the above. A bit string for selecting bit string data having the longest match with the search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more). In the data selection circuit,
6. The bit determination circuit according to claim 5, wherein the next selection bit string which is an output of the bit determination circuit for determining the bit at the same bit position i is selected by the bit determination circuit for determining the bit at the same bit position (i + 1). M stages are connected in series so as to be input as a bit string, and all non-matching bits output from the previous stage bit determination circuit are input to the next stage bit determination circuit.
A bit string data selection circuit for outputting a next selection bit string, which is an output of an m-th stage bit determination circuit, as information for selecting bit string data having the longest match with the search bit string. Bit string data for selecting bit string data that matches a search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more) In the selection method,
Bits extracted from the same bit position i (i = 0 to m−1) of each of the bit string data, each bit of the same position bit string composed of N bits corresponding to each bit string data, and the bit length a bit comparison sub-step for performing a bit comparison with a search bit at a bit position i of a search bit string of m and outputting a determination bit string including a determination bit indicating whether or not the bit in the same position bit string matches the search bit When,
It is a bit indicating whether or not each bit of the same position bit string is selected as a bit determination target, and a bit string operation is performed between the selected bit string including N selection bits corresponding to each bit string data and the determination bit string. The bit extracted from the next bit position (i + 1) of the same bit position i of each bit string data and each bit of the next same position bit string composed of N bits corresponding to each bit string data, respectively. , Which represents whether or not to select as a bit determination target, and outputs a next selection bit string composed of N next selection bits corresponding to each bit string data, and the selection bit of the selection bit string is the bit Significant bit indicating that the bit in the same position bit string is selected as a bit judgment target. If so, the determination bit corresponding to the selection bit is the next selection bit, and if the selection bit of the selection bit string is not the significant bit, the next selection bit setting substep in which the selection bit is the next selection bit; Including a bit determination step including
In this bit determination step, the next selected bit string, which is the output of the bit determination step for determining the bit at the same bit position i, is input as the selected bit string for the bit determination step for determining the bit at the same bit position (i + 1). Repeated sequentially,
Bit sequence data characterized in that the next selected bit sequence output in the bit determination step for determining the bit at the same bit position (m-1) is output as information for selecting bit sequence data that matches the search bit sequence Selection method. Bit string for selecting bit string data partially matching a search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more) In the data selection method,
Bits extracted from the same bit position i (i = 0 to m−1) of each of the bit string data, each bit of the same position bit string composed of N bits corresponding to each bit string data, and the bit length a bit comparison sub-step for performing a bit comparison with a search bit at a bit position i of a search bit string of m and outputting a determination bit string including a determination bit indicating whether or not the bit in the same position bit string matches the search bit When,
It is a bit indicating whether or not each bit of the same position bit string is selected as a bit determination target, and a bit string operation is performed between the selected bit string including N selection bits corresponding to each bit string data and the determination bit string. The bit extracted from the next bit position (i + 1) of the same bit position i of each bit string data and each bit of the next same position bit string composed of N bits corresponding to each bit string data, respectively. , Which represents whether or not to select as a bit determination target, and outputs a next selection bit string composed of N next selection bits corresponding to each bit string data, and the selection bit of the selection bit string is the bit Significant bit indicating that the bit in the same position bit string is selected as a bit judgment target. If so, the determination bit corresponding to the selection bit is the next selection bit, and if the selection bit of the selection bit string is not the significant bit, the next selection bit setting substep in which the selection bit is the next selection bit; ,
It is a bit indicating whether or not bits in the same position bit string composed of bits taken out from the same bit position i are excluded from the bit determination targets, and each of m skip bits corresponding to the same bit position i. If the skip bit in the skip bit string is a significant bit indicating that the bits constituting the corresponding same-position bit string are excluded from the bit determination target, the next selection output in the next selection bit setting sub-step Determination result of outputting the selected bit string as a next selected bit string in place of the bit string and outputting the next selected bit string output in the next selected bit setting substep if the skip bit is not a significant bit Including a selection substep, and the determination result selection substep Comprising a bit determination step of outputting a next selection bit string Oite output,
In this bit determination step, the next selected bit string, which is the output of the bit determination step for determining the bit at the same bit position i, is input as the selected bit string for the bit determination step for determining the bit at the same bit position (i + 1). Repeated sequentially,
A bit string characterized in that the next selected bit string output in the bit determining step for determining the bit at the same bit position (m-1) is output as information for selecting bit string data partially matching the search bit string Data selection method. A bit string for selecting bit string data having the longest match with the search bit string having a bit length of m from N (N is an integer of 2 or more) bit string data each having a bit length of m (m is an integer of 1 or more). In the data selection method,
Bits extracted from the same bit position i (i = 0 to m−1) of each of the bit string data, each bit of the same position bit string composed of N bits corresponding to each bit string data, and the bit length a bit comparison sub-step for performing a bit comparison with a search bit at a bit position i of a search bit string of m and outputting a determination bit string including a determination bit indicating whether or not the bit in the same position bit string matches the search bit When,
It is a bit indicating whether or not each bit of the same position bit string is selected as a bit determination target, and a bit string operation is performed between the selected bit string including N selection bits corresponding to each bit string data and the determination bit string. The bit extracted from the next bit position (i + 1) of the same bit position i of each bit string data and each bit of the next same position bit string composed of N bits corresponding to each bit string data, respectively. , Which represents whether or not to select as a bit determination target, and outputs a next selection bit string composed of N next selection bits corresponding to each bit string data, and the selection bit of the selection bit string is the bit Significant bit indicating that the bit in the same position bit string is selected as a bit judgment target. If so, the determination bit corresponding to the selection bit is the next selection bit, and if the selection bit of the selection bit string is not the significant bit, the next selection bit setting substep in which the selection bit is the next selection bit; ,
Determining whether the bits of the same-position bit string selected by the selected bits of the selected bit string do not match all the corresponding search bits, and outputting all mismatch bits;
The all unmatched bits are significant bits indicating that the bits of the same position bit string selected by the selected bits of the selected bit string do not match all corresponding search bits, or bits from the bit string data If the bits in the same bit sequence at the higher bit position do not match all the corresponding search bits at the bit position higher than the same bit position i from which the data is taken out, output in the next selected bit setting sub-step The selected bit string is output as the next selected bit string in place of the next selected bit string, and all the bits that are not significant and are higher than the same bit position i from which the bit is extracted from the bit string data Bit position of the same position bit string of the upper bit position. Is not in agreement with all the corresponding search bits, includes a determination result selection substep for outputting the next selection bit string output in the next selection bit setting substep, and is output in the determination result selection substep. A bit determination step of outputting the next selected bit string and outputting all the non-matching bits,
In this bit determination step, the next selected bit string, which is the output of the bit determination step for determining the bit at the same bit position i, is input as the selected bit string for the bit determination step for determining the bit at the same bit position (i + 1). Repeated sequentially,
A bit string characterized in that the next selected bit string output in the bit determining step for determining the bit at the same bit position (m-1) is output as information for selecting bit string data having the longest match with the search bit string. Data selection method.

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