JPWO2012172683A1 - Arithmetic processing device, information processing device, and control method of arithmetic processing device - Google Patents

Abstract

  The L2 cache control unit searches the cache memory based on the memory access request input from the request storage unit 0 via the CPU core unit, and requests the memory access request in which a cache miss has occurred to the request storage unit 1 and the request storage unit 2. Hold on. The bank abort generation unit counts the number of memory access requests to the main storage device for each bank based on the memory access requests held in the request storage units 1 and 2, and also counts the number of memory access requests for each bank. If any of the values exceeds a predetermined value, the L2 cache control unit is notified of a bank abort notification to instruct access interruption. Based on this instruction, the L2 cache control unit suspends processing of the memory access request held in the request storage unit 0. The main storage control unit issues a memory access request held in the request storage unit 2 to the main storage device.

Description

  The present invention relates to an arithmetic processing device, an information processing device, and a control method for the arithmetic processing device.

  A CPU (Central Processing Unit) is known as an arithmetic processing unit having a mechanism in which a cache memory is connected to a main storage device, and a memory access request to the cache memory and the main storage device is pipelined. Specifically, such an arithmetic processing device is implemented in a computer system as an information processing device, for example, as an L2 (Level-2: secondary) cache system.

  If the CPU core that is an instruction processing unit that processes an instruction misses a load instruction, for example, and the CPU core misses access to the L1 (Level-1: primary) cache memory, a new memory access request is issued to the L2 cache control unit. Issued and received by the new request storage unit. A memory access request is input from the new request storage unit to the pipeline of the L2 cache memory. When a memory access request input to the pipeline causes a cache miss in the L2 cache memory, the memory access request having the cache miss is stored in the request storage unit 1 and the request storage unit 2 in the system controller having a main memory control function. Is done. A memory access request is selected from the request storage unit 2 and issued to a DRAM (Dynamic Random Access Memory) access processing unit, and the memory access request is released from the request storage unit 2. The DRAM access processing unit accesses the DRAM by pipeline processing. A data response is made from the DRAM via the system controller to the L2 cache control unit. The L2 cache control unit that has received the data response activates the request response pipeline. When the processing of the request response pipeline is completed, the cache tag portion is updated, the data is stored in the cache data portion, the data response to the CPU core that issued the memory access request (when the load request is not a prefetch request), and the like are performed. Finally, the request storage unit 1 is released.

  Generally, a main storage device composed of a DRAM is divided into a predetermined number of memory banks (hereinafter referred to as “banks”). When processing of a memory access request for one bank is started, the same bank has a characteristic that processing for the next memory access request cannot be performed for a certain period of time. Therefore, in the above configuration, when a memory access request is input from the request storage unit 2 to the DRAM access processing unit, the same bank as the memory access request is excluded from selection targets for extraction from the request storage unit 2 for a certain period of time. Is done. Then, processing is performed by sequentially selecting the oldest memory access requests of banks that can be processed.

  Therefore, for example, in a system in which a plurality of CPU cores are mounted, a case where data load requests for the same bank are continuously generated from a plurality of CPU cores can be considered. In such a case, when the L2 cache system causes a cache miss, memory access requests to the same bank on the main storage device are concentrated, and the data transfer efficiency from the main storage device to the L2 cache memory and the CPU core deteriorates. A situation can arise.

  In response to this problem, even when the access request destination bank for the main storage device divided into a plurality of banks that can be shared and accessed independently by a plurality of processors is biased, the memory access wait time is shortened, A technique capable of improving the memory access performance is known. In this prior art, a priority determination waiting stack circuit corresponding to the priority determination circuit and corresponding to the access request stack circuit is provided in the storage controller between the priority determination circuit corresponding to the storage bank and the access request stack circuit. Configured. As a result, even when an access request destination storage bank is biased, subsequent access requests to other storage banks can be processed without waiting. The priority determination waiting stack circuit is configured to be able to send an input access request directly to the storage device via the priority determination circuit when there is an access request not stacked inside.

  However, this conventional technique has a problem that optimum access control cannot be realized for the entire system including the L2 cache control unit.

Japanese Patent Laid-Open No. 11-85605

  An object of the present invention is to equalize access to a memory bank in a system including a cache memory and a main storage device having a plurality of memory banks.

  In one example, in an arithmetic processing unit connected to a storage device having a plurality of banks, an instruction processing unit that issues a memory access request, a cache memory that has a plurality of cache lines that hold data, and the instruction processing unit A first request holding unit that inputs an issued memory access request, a second request holding unit that holds a memory access request in which a cache miss has occurred, and a memory access request input from the first request holding unit. The cache memory is searched based on the cache control unit that holds the memory access request in which the cache miss has occurred in the second request holding unit, and the processing among the memory access requests held in the second request holding unit A third request holding unit that holds a memory access request that has not been interrupted, the second request holding unit, When the number of memory access requests to the storage device is counted for each bank based on the memory access requests held in the three request holding units, and the counted number of memory access requests in any bank exceeds a predetermined value An access counting unit that instructs the cache control unit to interrupt processing of a memory access request for a bank in which the number of memory access requests exceeds a predetermined value, which is held in the first request holding unit; And a main storage control unit that issues a memory access request held in the request holding unit to the storage device.

  In a configuration in which a cache control unit and a main storage device having a plurality of memory banks are connected, even if the bank demands for the cache control unit and the main storage device are equalized and a bank access bias occurs, the memory access of the same bank It is possible to stop requests from being issued excessively. As a result, the memory access request issuance state can be changed so that memory access requests of various types of banks are always stored in the pipelines of the cache control unit and the main memory control unit. Can be equalized.

FIG. 2 is a diagram (No. 1) illustrating a general configuration of an information processing apparatus having a mechanism that pipelines a memory access request to an L2 cache memory and a main storage device. FIG. 3 is a diagram (No. 2) illustrating a general configuration of an information processing apparatus having a mechanism that pipelines a memory access request to an L2 cache memory and a main storage device. FIG. 11 is a diagram (No. 3) illustrating a general configuration of an information processing apparatus having a mechanism for performing pipeline processing on a memory access request to the L2 cache memory and the main storage device; FIG. 14 is a diagram (No. 4) illustrating a general configuration of an information processing apparatus having a mechanism for pipeline processing of memory access requests to the L2 cache memory and the main storage device; It is an operation | movement sequence diagram which shows the pipeline process of the L2 cache system which has a structure of FIG. 1A and FIG. 1B. It is the figure which showed the image of the pipeline process of the L2 cache system of FIG. 1A and FIG. 1B. It is a block diagram (the 1) of 1st Embodiment. It is a block diagram (the 2) of 1st Embodiment. 4B is a detailed circuit configuration diagram of a new request storage unit 102 (request storage unit 0) and a bank address equalization control unit (bank standby control unit) 402 of FIG. 4A. 4B is a detailed circuit configuration diagram of the pipeline control unit 103 and its peripheral circuits in FIG. 4A. FIG. FIG. 4B is a detailed circuit configuration diagram of the request storage unit 1 104 in FIG. 4A. 4B is a detailed circuit configuration diagram of a bank address equalization control unit (bank abort generation unit) 401 in FIG. 4A. FIG. It is a flowchart which shows the process of 1st Embodiment. It is a block diagram (the 1) of 2nd Embodiment. It is a block diagram (the 2) of 2nd Embodiment.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
1A and 1B are diagrams showing a general configuration of an information processing apparatus having an L2 cache memory connected to a main storage device and having a mechanism for pipeline processing of memory access requests to the L2 cache memory and the main storage device. is there. In this configuration, a CPU core portion and a portion that performs main memory access are divided into a multi-core CPU chip 1 with an external main memory access function and a system controller chip 107.

  The CPU core unit 100 in FIG. 1A is an arithmetic processing processor that executes arithmetic processing, and one or more CPU core units 100 may be mounted. The CPU core unit 100 is an example of an instruction processing unit.

  The new request storage unit 102 (also referred to as “request storage unit 0”), the pipeline control unit 103, and the request storage unit 104 (hereinafter simply referred to as “request storage unit 1”) in FIG. Configure.

  The new request storage unit 102 is provided with one or more entries corresponding to each CPU core unit 100. When the L1 (primary) cache in the CPU core unit 100 has a cache miss, the new request storage unit 102 sends a memory access request to the CPU core for pipeline processing in the L2 (secondary) cache memory. Held in the entry corresponding to the section 100.

  The pipeline control unit 103 executes control for pipeline processing of cache access and main memory access of a memory access request stored in the new request storage unit 102.

  The cache tag unit 105 and the cache data unit 106 in FIG. 1A constitute an L2 cache memory. The cache tag unit 105 stores a tag for each cache line. For each cache line, the cache data unit 106 is a DIMM (Dual Inline Memory Module) 110 (main memory device) 110 (determined by an index corresponding to the cache line and a tag on the cache tag unit 105 corresponding to the cache line. 1B) holds the data at the upper address. From the pipeline control unit 103 to the cache tag unit 105, a tag read command is issued to read the tag, or a tag update command is issued to update the tag. Also, a data read or write instruction (R / W instruction) is issued from the pipeline control unit 103 to the cache data unit 106, and a data read or write operation is performed.

  The request storage unit 1 104 (hereinafter, simply referred to as “request storage unit 1”) in FIG. 1A is a memory access request that causes a cache miss when a cache access to the cache tag unit 105 by the pipeline control unit 103 is a cache miss. Hold. The request storage unit 1 receives each memory access request until the access to the DIMM 110 (FIG. 1B) is completed, the cache tag unit 105 and the cache data unit 106 are updated, or data transfer to the CPU core unit 100 is completed. Hold.

  The CPU side bus interface unit 111 in FIG. 1A is a main memory access function external multicore CPU chip 1 side interface circuit of a system bus connecting the main memory access function external multicore CPU chip 1 and the system controller chip 107.

  A system controller side bus interface unit 112 in the system controller chip 107 of FIG. 1B is an interface circuit on the system controller chip 107 side of the system bus.

  A request storage unit 2 108 (hereinafter simply referred to as “request storage unit 2”) in the system controller chip 107 of FIG. 1B holds a memory access request that has been missed by the L2 cache control unit 101 of FIG. 1A. The request storage unit 2 holds each memory access request until the memory access request is read to the DIMM access control unit 109 in the system controller chip 107 and is input to the main memory access pipeline.

  When storing a memory access request in the request storage units 1 and 2, a request storage instruction is issued from the pipeline control unit 103 to the request storage units 1 and 2, and the request storage units 1 and 2 receive a memory access request based on this instruction. Execute the storing operation.

  The DIMM access control unit 109 in the system controller chip 107 in FIG. 1B selects a memory access request for a bank that can be entered from the request storage unit 2 and issues a memory access command and address to the DIMM 110. When read from the request storage unit 2 to the DIMM access control unit 109, the request storage unit 1 in FIG. 1A from the request storage unit 2 through the system controller side bus interface unit 112 and the CPU side bus interface unit 111 in FIG. 1A. In response to this, a request release notification is notified.

  The DIMM 110 in FIG. 1B is a memory module in which a plurality of DRAM chips are mounted on a printed circuit board, and is used as a main storage device.

  The data response from the main storage device acquired by accessing the DIMM 110 is returned to the cache data unit 106, the request storage unit 1, and the CPU core unit 100 that requested the memory access request in FIG. 1A.

  The pipeline control unit 103 in FIG. 1A issues a write command to the cache data unit 106 in response to the data response. As a result, the pipeline control unit 103 writes the data returned from the main storage unit to a writable cache way in the cache line corresponding to the address of the response data on the cache data unit 106. Also, the pipeline control unit 103 issues a tag update command to the cache tag unit 105 in response to the data response. As a result, the pipeline control unit 103 updates the tag corresponding to the cache line and the cache way on the cache tag unit 105 with the tag corresponding to the address of the response data.

  1C and 1D, similarly to FIGS. 1A and 1B, an L2 cache memory is connected to a main storage device, and an information processing apparatus having a mechanism for pipeline processing memory access requests to the L2 cache memory and the main storage device It is a figure which shows the general structure of. In this configuration, a portion that performs main memory access is mounted as a single chip in the external multi-core CPU chip 1 having a main memory access function.

  In this configuration, the CPU side bus interface unit 111 in FIG. 1A and the system controller side bus interface unit 112 in FIG. 1B are omitted, and the function of the request storage unit 2 in FIG. Has been. The control is the same as in the case of FIG. 1A and FIG. 1B except that the request storage unit 1 is responsible for the function of the request storage unit 2 and communication control between the request storage unit 1 and the request storage unit 2 is omitted. .

  FIG. 2 is an operation sequence diagram showing pipeline processing of the L2 cache system having the configuration of FIGS. 1A and 1B.

  First, when the CPU core unit 100 misses, for example, a load instruction and the CPU core misses access to the L1 (primary) cache memory, a new memory access request is issued to the L2 cache control unit 101. Thereby, the memory access request is received by the new request storage unit 102 in the L2 cache control unit 101 (sequence S1).

  A memory access request is input from the new request storage unit 102 to the pipeline of the L2 cache memory (described as “L2-PIPE” in FIG. 2) (sequence S2). Note that L2-PIPE is not a physical circuit, but a diagram showing the status of pipeline processing over time.

  When a memory access request input to the L2-PIPE causes a cache miss in the L2 cache memory (sequence S3), the memory access request having the cache miss is stored in the request storage unit 1 (sequence S4). Further, the memory access request is stored in the request storage unit 2 in the system controller chip 107 of FIG. 1B (sequence S5). Transfer of the memory access request from the request storage unit 1 to the request storage unit 2 is executed from the CPU side bus interface unit 111 in FIG. 1A via the system bus via the system controller side bus interface unit 112 in FIG. 1B. . Further, the pipeline control unit 103 notifies the new request storage unit 102 of an entry release notification corresponding to the memory access request (sequence S6). As a result, the new request storage unit 102 releases the entry corresponding to the memory access request and becomes ready to accept the next memory access request.

  Each of the request storage unit 1 and the request storage unit 2 includes a plurality of entries that hold memory access requests. The pipeline control unit 103 retrieves one memory access request from one entry in the new request storage unit 102 and executes cache access. As a result, a cache hit occurs and the data response to the CPU core unit 100 is completed, or a memory access request is stored in the request storage units 1 and 2 due to a cache miss.

  The memory access requests held in the request storage unit 2 in the system controller chip 107 are expressed in order from the memory access request having a bank address that can be processed to the DIMM 110 access pipeline (referred to as “main memory access pipe” in FIG. 2). ). The main memory access pipe is not a physical circuit, as in the case of L2-PIPE, but is a diagram illustrating the status of pipeline processing for main memory access over time. The DIMM access control unit 109 extracts the memory access request from the request storage unit 2 (sequence S7), releases the entry in the request storage unit 2, and notifies the request storage unit 1 to that effect (sequence S8). The notification from the request storage unit 2 to the request storage unit 1 is executed from the system controller side bus interface unit 112 of FIG. 1B via the system bus via the CPU side bus interface unit 111 of FIG. 1A. As a result, the request storage unit 2 becomes ready to accept a new memory access request for the released entry. The DIMM access control unit 109 generates a command and an address corresponding to the fetched memory access request, and executes memory access to the DIMM 110 (sequence S9).

  When the memory access in the DIMM 110 is completed, a data response is transmitted from the DIMM 110 to the request storage unit 1 (sequence S10). A data response from the request storage unit 2 to the request storage unit 1 is executed from the system controller side bus interface unit 112 of FIG. 1B via the system bus via the CPU side bus interface unit 111 of FIG. 1A. As a result, a request response pipe is activated on the L2-PIPE from the request storage unit 1 via the pipeline control unit 103 (sequence S11). In the request response pipe, the pipeline control unit 103 writes the response data to the cache data unit 106 and updates the tag of the cache tag unit 105 (sequence S12). Further, the pipeline control unit 103 makes a data response to the CPU core unit 100 (sequence S13). The data response to the CPU core unit 100 is executed when the memory access request is a load request and is not a prefetch request for reading data necessary for the cache memory in advance. Finally, the request storage unit 1 is notified of the release of the corresponding memory access request entry (sequence S14). As a result, the corresponding entry in the request storage unit 1 is released.

  In the above control operation, the pipeline control unit 103 extracts one memory access request from a plurality of entries in the new request storage unit 102, executes cache access, and releases the entry in the new request storage unit 102. . Thereafter, when a cache miss occurs in one memory access request and the main memory access is necessary, the pipeline control unit 103 delivers the memory access request to the request storage units 1 and 2. As a result, the pipeline control unit 103 can once release the process corresponding to the memory access request on the L2-PIPE and read another memory access request from the new entry in the new request storage unit 102. . As a result, the DIMM access control unit 109 can sequentially read memory access requests from the new request storage unit 102 and continuously pipeline the cache access corresponding to each memory access request.

  Also, the DIMM access control unit 109 in the system controller chip 107 extracts one memory access request from the request storage unit 2, then releases the corresponding entry in the request storage unit 2, and uses that entry as the next memory access. Make the request ready. Then, if the bank address is not the same, the DIMM access control unit 109 can retrieve the next memory access request from the request storage unit 2 and process it continuously. In this manner, also in the system controller chip 107, efficient main memory access is realized by pipeline processing using the main memory access pipe.

  The pipeline control unit 103 includes a counter that counts the number of entries used in the request storage unit 1. Then, the pipeline control unit 103 reads the memory access request from the new request storage unit 102 and performs cache access. As a result, when a cache miss occurs and the request storage unit 1 has no free space, the pipeline control unit 103 stores the new request storage unit 102. Inform the user of the return instruction. As a result, the corresponding entry in the new request storage unit 102 is not released and enters a standby state.

  Further, the pipeline control unit 103 is notified to the request storage unit 1 of the pipe address (the address requested by the memory access request) that the pipeline control unit 103 is currently pipeline processing. As a result, when the request storage unit 1 detects a match between the address requested by the memory access request in its entry and the pipe address, the request storage unit 1 notifies the pipeline control unit 103 of an address match notification. In this case, the memory access request address data for which the pipeline control unit 103 is to start pipeline processing is currently stored in the entry of the request storage unit 1 and occupies that entry ( Since it is in progress), it is not necessary to perform main memory access again. Therefore, when the pipeline control unit 103 receives an address match notification, the pipeline control unit 103 notifies the new request storage unit 102 of a return instruction. As a result, the corresponding entry in the new request storage unit 102 is not released and enters a standby state. After the corresponding memory access request in the request storage unit 1 is executed and the cache tag unit 105 and the cache data unit 106 are updated, the memory access request for requesting the same address in the new request storage unit 102 is processed by pipeline processing. Is done. As a result, the memory access request hits the cache, and the corresponding data is loaded from the cache data unit 106 to the CPU core unit 100 that is the request source.

  In addition, when the pipeline abort condition is satisfied in the pipeline control unit 103, the pipeline control unit 103 notifies the new request storage unit 102 and the request storage unit 1 of a return instruction. As a result, the corresponding entry in the new request storage unit 102 and the request storage unit 1 is not released and enters a standby state.

  In the configuration of the L2 cache system shown in FIGS. 1A and 1B, the main storage device including the DIMM 110, which is a kind of DRAM, is divided into a certain number of banks. When a memory access request for a certain bank is processed, the same bank has a characteristic that it cannot process the next memory access request for a certain period of time. For this reason, when a memory access request is input from the request storage unit 2 to the DIMM access control unit 109, a memory access request having the same bank address as the request is selected from a selection target to be extracted from the request storage unit 2 for a certain period of time. Excluded. Then, among the memory access requests having processable bank addresses in the entry of the request storage unit 2, the oldest ones are sequentially selected and processed.

  FIG. 3 is a diagram showing an image of pipeline processing of the L2 cache system of FIGS. 1A and 1B.

  Now, consider a case where four processors Core 0, Core 1, Core 2, and Core 3 are mounted as the CPU core unit 100 in FIG. 1A. In FIG. 3, BANK: 0, BANK: 1, BANK: 2, BANK: 3, BANK: 4, BANK: 5, BANK: 6, and BANK: 7 are bank addresses indicated by respective labels on the request pipe. Indicates that the memory access request is being pipelined. These labels indicate that the data response of the bank address indicated by each label is pipeline processed on the request response pipe. In the following description, “BANK: 0” is simply “0”, “BANK: 1” is simply “1”, and the label “BANK:” is omitted.

  First, consider a case where a service that handles streaming data such as online video distribution is executed in a system in which the four CPU cores 100 of Core 0 to 3 are mounted. In this case, consider a case where a plurality of CPU core units 100 are requested almost simultaneously for reproduction of the same streaming data. In such a case, as indicated by 301 in FIG. 3A, from each of the CPU cores 100 of Core 0 to 3, for example, 0 → 0 → 0 → 0 → 1 → 1 → 1 → 1 There is a possibility that memory access requests of the same bank are issued continuously on the request pipe. In this case, when a cache miss occurs in the L2 cache memory, the DIMM access control unit 109 reads the first BANK: 0 memory access request from the request storage unit 2 and executes memory access to the DIMM 110. After that, for a certain period of time, the DIMM access control unit 109 cannot read out the same BANK: 0 memory access request from the request storage unit 2. That is, in the example 301 in FIG. 3A, after the first BANK: 0 memory access request is executed, the subsequent three memory access requests having the same BANK: 0 remain in the request storage unit 2 for a certain period of time. Will remain. Then, as indicated by 302 in FIG. 3A, the memory access request for other BANK: 1 or BANK: 2 is read from the request storage unit 2 to the DIMM access control unit 109, and the memory to the DIMM 110 is read out. Access is performed. As a result, as shown by 302 in FIG. 3A, the data response on the request response pipe is the data of BANK: 1, BANK: 2, etc. with an interval after the first BANK: 0 data response. The response continues. Then, only after a certain time has passed after the first BANK: 0 data response, the next BANK: 0 data response appears.

  In the situation shown in FIG. 3A, not only the data response to the same bank is greatly delayed, but also many memory access requests for the same bank stay on the request storage units 1 and 2. As a result, a new memory access request cannot be stored in the request storage units 1 and 2, and usable entries in the request storage units 1 and 2 are exhausted. In other words, it can be said that the entries of the request storage units 1 and 2 are wasted and the number of entries is substantially reduced, and the performance of the L2 cache control unit 101 is greatly reduced from the theoretical performance. To do.

  A possible solution to this problem is to increase the number of entries in the request storage units 1 and 2. For example, if a large number of entries sufficient to store memory access requests on the DIMM 110 are prepared for all streams, it can be expected to reduce the influence of local bias. However, this means has a problem that the physical area occupied on the integrated circuit is increased.

  Therefore, it is important to keep the banks of the request storage units 1 and 2 always uniform without increasing the physical area. In other words, on the main memory access pipeline at the time of a cache miss, it is possible to perform access control so that the banks on the main memory requested by the memory access request are evenly distributed without being biased to specific banks. Top important. In the embodiment described below, such access control is referred to as bank equalization in pipeline access from the cache control unit to the main storage device.

  As indicated by reference numeral 303 in FIG. 3B, one CPU core unit 100 outputs a memory access request for streaming data for continuous bank access such as 0 → 1 → 2 → 3 → 4. However, when looking at the CPU core units 100 of Core 0 to 3 as a whole, for example, memory access requests of various types of banks are sequentially made, such as 0 → 4 → 2 → 6 → 1 → 5 → 3 → 7. Consider a case where it is issued on a request pipe. In this case, even if a cache miss occurs in the L2 cache memory, the memory access requests for each bank address can be successively read from the request storage unit 2 to the DIMM access control unit 109. As a result, as shown as 304 in FIG. 3B, on the request response pipe executed as the sequence 12 in FIG. 2, the data response corresponding to each bank address is sent in the same order as on the request pipe. , Can be processed without interruption. In this case, the data transfer performance from the main storage unit to the L2 cache control unit 101 and the CPU core unit 100 is maximized. However, as shown in FIG. 3B, memory access requests to various types of banks are not always generated. Therefore, it is desired that bank equalization in pipeline access from the memory cache control unit to the main storage unit be performed more accurately.

  A first embodiment described below includes a main storage device having a configuration divided into banks, a main storage control device that controls the main storage device, a cache memory for the main storage device, and a cache that controls the cache memory It has a control device. In response to a new memory access request, the cache controller searches for a tag holding the state of the cache memory through pipeline processing from the new request storage unit through the pipeline input unit. As a result, if a cache miss occurs, it is stored in the request storage unit 1 as an in-process memory access request for the main storage device in units of cache lines and the memory access request is issued to the main storage control device. After receiving the data response from the main storage device, the request storage unit 1 updates the tag unit and the data storage unit of the cache memory by pipeline processing and releases the entry of the request storage unit 1. The request storage unit 1 performs an address match on the subsequent memory access request in a pipeline, and interrupts the processing for the same address. Then, a memory access request from the cache control device is temporarily stored in the request storage unit 2 shared by each bank in the main storage control device, and a request for a bank not being processed is selected from the request storage unit 2 to select the main storage device. In the information processing apparatus that performs processing for the number of memory access requests that match the bank, how many memory access requests corresponding to the new memory access request during pipeline processing are stored in the request storage unit 1. Counting, if the count value exceeds a predetermined threshold value, the process is interrupted. If the count value is not exceeded, the process is continued and a memory access request is issued to the request storage unit 2 of the main storage control device It is. The memory access request in the request storage unit 1 to be counted is a memory access request that has not received the release notification of the request storage unit 2 among the memory access requests stored in the request storage unit 1. As a result, the request banks stored in the request storage unit 2 in the main storage control device are guided to be equal, and the main memory transfer performance close to the theoretical performance can be obtained.

  The first embodiment has a system configuration shown in FIGS. 4A and 4B, which is an improvement of the system configuration shown in FIGS. 1A and 1B. 4A and 4B, the same reference numerals are given to portions that perform the same operations as those in FIGS. 1A and 1B. In the configuration of this embodiment, as in the case of FIGS. 1A and 1B, the CPU core part and the part that performs main memory access are divided into a multi-core CPU chip 1 with an external main memory access function and a system controller chip 107. It is a configuration.

The configuration of the system controller chip 107 in FIG. 4B is the same as the configuration in FIG. 1B.
4A, the L2 cache control unit 101 includes a bank address equalization control unit (bank abort generation unit) 401 and a bank address equalization control unit (bank standby control unit) 402.

  The bank abort generation unit 401 counts the number of memory access requests to the DIMM 110 of the main storage unit for each bank based on the memory access requests held in the request storage unit 1 and the request storage unit 2. At the same time, when any of the counted number of memory access requests for each bank exceeds a predetermined value, the bank abort notification is issued to instruct the pipeline control unit 103 to interrupt the main memory access. As a result, the pipeline control unit 103 notifies the new request storage unit 102 of a return instruction. As a result, the corresponding entry in the new request storage unit 102 is not released and enters a standby state, and execution of the corresponding memory access request is delayed.

  In addition, the bank abort generation unit 401 notifies the bank standby control unit 402 of a request standby notification for each bank that exceeds a predetermined value among the counted number of memory access requests to the DIMM 110 for each bank.

  Of the memory access requests output from the entry in the new request storage unit 102, the bank standby control unit 402 determines the memory access request that is on standby for requesting the bank address corresponding to the request standby notification output from the bank abort generation unit 401. Suppress output. As a result, until the count value of the memory access request of the corresponding bank for the DIMM 110 falls below a predetermined value, the corresponding memory access request is prevented from being input to the pipeline of the L2 cache control unit 101.

  Each time a memory access request is read from the request storage unit 2 to the DIMM access control unit 109 and executed, the count value of the bank corresponding to the memory access request is decremented by one.

  The bank address equalization control unit including the bank abort generation unit 401 and the bank standby control unit 402 can prevent the memory access requests of the same bank from being issued excessively. Furthermore, it is possible to cause the DIMM 110 to issue a memory access request of a bank that is issued less frequently than other banks with priority. As a result, the memory access request issuance state naturally becomes a state where memory access requests of various types of banks are always stored in the request storage units 1 and 2 as illustrated in FIG. This makes it possible to equalize bank access.

  FIG. 5A is a detailed circuit configuration diagram of the new request storage unit 102 (request storage unit 0) and the bank address equalization control unit (bank standby control unit) 402 of FIG. 4A.

  The new request storage unit 102 includes an entry unit 501, an entry output gate 502, a pipe entry entry selection unit 503, and a reset OR gate 504.

  The entry unit 501 is mounted corresponding to each of the one or more CPU core units 100. The entry unit 501 holds a memory access request for pipeline processing in the L2 cache memory when the L1 cache in the CPU core unit 100 has a cache miss. At this time, a VAL flag is set by a memory access request from the CPU core unit 100, and physical address data for requesting access is written as PA (Physical Address) data. The VAL flag is a flag indicating whether or not the memory access request set in the entry unit 501 is valid. The physical address data is composed of 40 bits, for example, and 21 bits from the 39th bit to the 19th bit represent a tag. Also, 12 bits from the 18th bit to the 7th bit represent an index (= number of cache lines). That is, the number of cache lines of the L2 cache memory in the first embodiment is 2 12 = 4096 lines. Three bits from the ninth bit to the seventh bit in the index represent the bank address. That is, the number of banks of the DIMM 110 in the first embodiment is 2 to the third power = 8 banks. Further, 7 bits from the 6th bit to the 0th bit represent an offset address in the same line. In the entry unit 501, the HLD flag and the WAIT flag are reset when the power is turned on. The HLD flag is a flag indicating that the memory access request of the entry unit 501 is in a state of occupying the entry of the request storage unit 1 in the L2 cache control unit. The WAIT flag is a flag indicating that the memory access request is once aborted in the L2 cache control unit 101 and is waiting to be reissued to the L2 cache control unit 101.

  The entry output gate 502 is provided corresponding to one or more entry units 501 and determines whether or not to enable the output of each entry unit 501. The entry output gate 502 is turned on when the VAL flag of the entry unit 501 is on, the HLD flag is off, and the output of the bank standby control unit 402 is off. When a memory access request is first set from the CPU core unit 100 to the entry unit 501, the HLD flag is off. Since the WAIT flag is also off, the AND gate group 511 and the AND gate 513 corresponding to the entry unit 501 in the bank standby control unit 402 are all turned off, and the output of the OR gate 512 is turned off. Thus, when a memory access request is first set in the entry unit 501, the entry output gate 502 corresponding to the entry unit 501 is always turned on, and the memory access request is sent to the pipe entry entry selection unit 503. Output to. That is, a new memory access request is always unconditionally piped once. This is because there is no need to wait in the new request storage unit 102 if the memory access request causes a cache hit.

  The pipe entry entry selection unit 503 issues a memory access request according to a predetermined rule (for example, in the oldest order) from among the memory access requests held in the entry unit 501 corresponding to the entry output gate 502 whose output is turned on. select. Then, the selected memory access request is input to the pipeline control unit 103 in FIG. 4A. At this time, the HLD flag of the corresponding entry unit 501 is reset (rst) according to the output of the pipe entry entry selection unit 503. As a result, the entry output gate 502 corresponding to the entry unit 501 is turned off. Then, unless the pipeline return notification 528 from the pipeline control unit 103 is turned on and the HLD flag is reset through the reset OR gate 504, the memory access request of the entry unit 501 is input to the pipeline control unit 103 again. It will never be done. That is, the entry unit 501 waits for the execution result after the memory access request is input to the pipeline control unit 103.

  When the pipeline control unit 103 satisfies the abort condition of the memory access request input to the L2-PIPE (see FIG. 2), the pipeline control unit 103 notifies the new request storage unit 102 of the pipeline return notification 528. The As a result, the HLD flag is turned off through the reset OR gate 504 and the WAIT flag is set. As a result, the memory access request in the entry unit 501 enters a standby state. In this state, in the entry output gate 502 corresponding to the entry unit 501, the VAL flag is on and the HLD flag is off. Accordingly, whether or not the entry output gate 502 outputs is determined depending on the output of the bank standby control unit 402.

  An AND gate 513 and a bank standby control unit 402 are provided corresponding to each entry unit 501. The AND gate 513 receives the WAIT flag of the entry unit 501 and the request storage unit 1 resource counter value 515 output from the pipeline control unit 103 in FIG. 4A. The request storage unit 1 resource counter value 515 counts the number of entries currently in use in the request storage unit 1 of FIG. 4A. The request storage unit 1 resource counter value 515 is 0 when the number of entries in the request storage unit 1 is empty, and the request storage unit 1 resource counter value 515 is 1 when there is no space. Therefore, when the memory access request of the entry unit 501 is returned from the pipeline control unit 103 and is in a standby state, and the number of entries in the request storage unit 1 is not empty, the following control operation is executed. The When the output of the AND gate 513 is turned on (1) and the entry output gate 502 is turned off (0) through the OR gate 512, the memory access request in the standby state is input to the pipeline control unit 103. Deterred.

  On the other hand, when the memory access request of the entry unit 501 is returned from the pipeline control unit 103 and is in a standby state, and the number of entries in the request storage unit 1 is empty, the output of the AND gate 513 is turned off. . In this case, the output of the AND gate group 511 is further determined. The AND gate group 511 includes eight AND gates corresponding to, for example, eight banks from bank 0 to 7. Each AND gate of the AND gate group 511 receives the result of decoding the bank address (for example, the 9th to 7th bits) in the PA data of the corresponding entry unit 501 by the bank address decoder 510. That is, the bank address decoder 510 has a plurality of output lines such that any one of the eight outputs corresponding to the banks 0 to 7 is turned on by decoding the bank address. Each of these output lines is input to each AND gate of the AND gate group 511. Further, the WAIT flag of the corresponding entry unit 501 is input to each AND gate of the AND gate group 511. Further, a request waiting notification 514 for each bank generated by the bank abort generation unit 401 is input to each AND gate of the AND gate group 511. For example, the AND gate corresponding to bank 0 in the AND gate group 511 includes a WAIT flag, a signal that is turned on when the bank address of the PA data is equal to bank 0, and a signal that is turned off at other times. A corresponding request waiting notification 514 is input.

  For example, the request waiting notification 514 corresponding to the bank 0 is turned on when the number of memory access requests corresponding to the bank 0 requested to the DIMM 110 by the bank abort generation unit 401 exceeds a predetermined value. Become. Therefore, the AND gate corresponding to the bank 0 in the AND gate group 511 is waiting for the memory access request of the corresponding entry unit 501, the bank address of the request is the bank 0, and the current main memory access to the bank 0. Turns on when exceeds a predetermined number. As a result, the entry output gate 502 corresponding to the entry unit 501 is turned off through the OR gate 512, and the entry of the memory access request for requesting the bank 0 waiting in the entry unit 501 to the pipeline control unit 103 is suppressed. Is done. This avoids the concentration of memory access requests to bank 0, which currently has more main memory accesses than other banks 1-7.

The same control operation as in the case of bank 0 is executed for banks 1 to 7 as well.
As described above, the function of the bank standby control unit 402 avoids the concentration of memory access requests to some banks with respect to the memory access requests that are waiting in the entry unit 501, and the memory to each bank. It is possible to equalize the input of access requests.

FIG. 5B is a detailed circuit configuration diagram of the pipeline control unit 103 and its peripheral circuits in FIG. 4A.
The memory access request output from the pipe entry entry selection unit 503 in the new request storage unit 102 in FIG. 5A is sent to the L2-PIPE pipeline (which is controlled by the pipeline control unit 103 via the pipe entry control unit 520 in FIG. 5B). 2).

  The pipeline control unit 103 includes a tag read control unit 521, various other pipe abort condition generation units 522, a request storage unit 1 resource counter 523, an abort OR gate 524, and a pipeline command generation unit 525.

  The tag read control unit 521 executes the following processing for the memory access request input from the pipe input control unit 520 to the L2-PIPE pipeline. First, the address data in the memory access request is set as a pipe address 530, for example, the 18th to 7th bits are taken out to generate a tag read address 533 as an index. Next, the tag reading control unit 521 generates a request tag by taking out, for example, the 39th to 19th bits of the pipe address 530. Then, the tag read control unit 521 outputs a tag read notification 532 to the cache tag unit 105 and also outputs a tag read address 533. As a result, the cache tag unit 105 designates a cache line corresponding to the tag read address 533, and reads each tag data stored in each cache way corresponding to the cache line. Then, the cache tag unit 105 compares whether any of the tag data matches the request tag generated by the tag read control unit 521.

  When any tag data matches the request tag, the tag read control unit 521 determines a cache hit, and the matched tag is output from the cache tag unit 105 to the cache data unit 106 as a tag read output. As a result, on the cache data unit 106, cache data is read from the cache way corresponding to the tag read output for which a match is detected in the cache line corresponding to the tag read address 533. Then, this cache data is connected as a cache data portion read output data 535 to a data response 562 of FIG. 5C described later, thereby being returned to the CPU core portion 100 of FIG. At this time, a pipeline processing success notification (entry release notification) 529 is output from the pipeline command generation unit 525 to the new request storage unit 102 in FIG. 5A. As a result, in the corresponding entry unit 501 in FIG. 5A described above, the VAL flag, HLD flag, and WAIT flag of the corresponding entry unit 501 are reset, and the corresponding entry in the new request storage unit 102 is released.

  If none of the tag data matches the request tag and the tag read control unit 521 determines a cache miss, the abort OR 524 determines whether or not a memory access request to the request storage unit 1 can be issued. Is done. First, the abort or gate 524 determines whether the abort condition is turned on from the other various pipe abort condition generation units 522. Further, the abort OR gate 524 determines whether or not the request storage unit 1 resource counter 523 outputs a request storage unit 1 resource counter value 515 having a value of 1 indicating a count full (FULL). Further, the abort OR gate 524 determines whether or not an address match notification 558 indicating that a memory access request with the same address has already been input has been received from the request storage unit 1 in FIG. 4A. Further, the abort or gate 524 determines whether or not the bank abort notification 539 is notified from the bank abort generation unit 401 of FIG. 4A.

  The abort OR gate 524 turns off the abort output to the pipeline command generation unit 525 when none of the above determinations are satisfied. As a result, the pipeline command generation unit 525 searches for a free entry in the request storage unit 1 in FIG. 4A and sends a request storage unit 1 entry acquisition notification 527 to the request storage unit together with the memory access request that caused the cache miss. 1 is notified. Thereafter, the main memory access is executed through the request storage unit 1 and the request storage unit 2, and the cache missed data is acquired. When the pipeline processing for the cache miss is successful, the pipeline command generation unit 525 outputs a pipeline processing success notification (entry release notification) 529 to the new request storage unit 102 in FIG. 5A. As a result, in the corresponding entry unit 501 of FIG. 5A described above, the VAL flag, HLD flag, and WAIT flag of the corresponding entry unit 501 are reset, and the corresponding entry in the new request storage unit 102 is released.

  The request storage unit 1 resource counter value 515 in the pipeline control unit 103 is added when the request storage unit 1 entry acquisition notification 527 is issued from the pipeline command generation unit 525 and a memory access request is registered in the request storage unit 1. 1 (incremented). Also, when a pipeline processing success notification (entry release notification) 529 is issued from the pipeline command generation unit 525 and the entry in the request storage unit 1 is released, it is decremented by 1 (decrement). That is, the request storage unit 1 resource counter 523 counts the number of entries currently used in the request storage unit 1. The request storage unit 1 resource counter value 515 is 0 when the number of entries in the request storage unit 1 is empty, and the request storage unit 1 resource counter value 515 is 1 when there is no space. When the request storage unit 1 resource counter 523 outputs a request storage unit 1 resource counter value 515 having a value of 1 indicating a full count (FULL), and the output of the abort or gate 524 is turned on, the pipeline command generation unit 525 On the other hand, an abort is set. As a result, the pipeline command generation unit 525 outputs a pipeline return notification 528 to the new request storage unit 102 in FIGS. 4A and 5A. As a result, the HLD flag is reset and the WAIT flag is set through the reset OR gate 504 in FIG. 5A. As a result, the memory access request in the entry unit 501 enters a standby state. Further, the request storage unit 1 resource counter value 515 of value 1 is output to the new request storage unit 102. As a result, as described above, in FIG. 5A, the output of the AND gate 513 is turned on, and the entry output gate 502 is turned off via the OR gate 512. Thereby, the memory access request that is in the standby state is prevented from being input to the pipeline control unit 103. As described above, issuance of excessive memory access requests to the request storage unit 1 is suppressed.

  When the address storage notification 558 indicating that the memory access request with the same address has already been input is notified from the request storage unit 1 in FIG. 4A, the abort OR gate 524 is turned on. As a result, abort is set for the pipeline command generation unit 525. In such a case, the memory access request address data that the pipeline control unit 103 intends to issue to the request storage unit 1 is currently stored in the entry of the request storage unit 1 and occupies that entry. Therefore, it is not necessary to perform main memory access again. Therefore, when the pipeline command generation unit 525 receives the address match notification 558, the pipeline command generation unit 525 notifies the new request storage unit 102 of the pipeline return notification 528. As a result, the HLD flag is reset and the WAIT flag is set through the reset OR gate 504 in FIG. 5A. As a result, the memory access request in the entry unit 501 enters a standby state. After the corresponding memory access request in the request storage unit 1 is executed and the cache tag unit 105 and the cache data unit 106 are updated, a standby memory access request for requesting the same address in the new request storage unit 102 is piped. Re-enter the line. As a result, the memory access request has a cache hit, and the cache data portion read output data 535 is loaded from the cache data portion 106 to the CPU core portion 100 that is the request source.

  Further, when the bank abort notification 539 is notified from the bank abort generation unit 401 in FIG. 4A, the abort OR gate 524 is turned on, and the pipeline command generation unit 525 is set to abort. The bank abort generation unit 401 counts the number of memory access requests to the DIMM 110 of the main storage unit for each bank based on the memory access requests held in the request storage unit 1 and the request storage unit 2. At the same time, when any of the counted number of memory access requests for each bank exceeds a predetermined value, a bank abort notification 539 is issued to instruct the pipeline control unit 103 to interrupt the main memory access. As a result, the pipeline command generation unit 525 outputs a pipeline return notification 528 to the new request storage unit 102. As a result, the corresponding entry unit 501 of the new request storage unit 102 is not released and enters a standby state, and execution of the corresponding memory access request is delayed. In addition to the operation of the bank standby control unit 402 in FIG. 5A described above, the control operation using the bank abort notification 539 from the bank abort generation unit 401 described above prevents the memory access request of the same bank from being issued excessively. be able to. Furthermore, it is possible to cause the DIMM 110 to issue a memory access request of a bank that is issued less frequently than other banks with priority. As a result, the memory access request issuance state naturally becomes a state where memory access requests of various types of banks are always stored in the request storage units 1 and 2 as illustrated in FIG. This makes it possible to equalize bank access.

  The abort or gate 524 determines whether or not various abort conditions are turned on from various other pipe abort condition generation units 522, and sets abort to the pipeline command generation unit 525 according to the determination result. To do.

FIG. 5C is a detailed circuit configuration diagram of the request storage unit 1104 of FIG. 4A.
The request storage unit 1 includes an entry unit 550, an entry output gate 551, a pipe entry entry selection unit 552, and a reset OR gate 553. A plurality of entry units 550 are mounted so that a plurality of memory access requests can be pipelined. A plurality of entry output gates 551 and reset OR gates 553 are also mounted corresponding to each entry unit 550. Further, the request storage unit 1 has the following configuration corresponding to each entry unit 550. First, a comparison (match detection) circuit 554 for detecting a match between the PA data of the corresponding entry unit 550 and the pipe address 530 given from the pipeline control unit 103 is provided. Furthermore, an AND gate 555 that outputs the output of the comparison (match detection) circuit 554 is provided on condition that the VAL flag of the corresponding entry unit 550 and the pipe address match detection instruction 531 supplied from the pipeline control unit 103 are turned on. Further, an OR for the output of the AND gate 555 for each entry unit 550 is calculated and provided to the abort OR gate 524 in the pipeline control unit 103 of FIG. 5B as an address match notification 558. Furthermore, the request storage unit 1 temporarily holds a main memory data response 561 from the DIMM 110 that is the main memory unit. Thereafter, the main memory data response 561 is transferred as the cache data portion write data 538 to the cache data portion 106 of FIG. 5B or as the CPU data response 563 to the CPU core portion 100 of FIG. 5A.

  When the pipeline command generation unit 525 in FIG. 5B notifies the request storage unit 1 entry acquisition notification 527 and the memory access request for main memory access, the following operations are executed. In the corresponding entry unit 550 of the request storage unit 1, the request storage unit 1 entry acquisition notification 527 sets the VAL flag, and the physical address data requesting access is written as PA data. The VAL flag is a flag indicating whether or not the memory access request set in the entry unit 550 is valid. The physical address data has the same format as the PA data of the entry unit 501 in FIG. 5A described above, and is composed of, for example, 40 bits. The RDY flag and the HLD flag are initially reset. The RDY flag is a flag indicating that preparation for input to the request response pipe (see sequence S12 in FIG. 2) has been completed. The HLD flag is a flag indicating that the memory access request of the entry unit 550 is being processed in the request response pipe of the L2 cache control unit 101.

  In parallel with the registration of the request storage unit 1 in the entry unit 550, a memory access request for main memory access notified together with the request storage unit 1 entry acquisition notification 527 from the pipeline command generation unit 525 of FIG. The request storage unit 2 is also registered. Transfer of the memory access request from the request storage unit 1 to the request storage unit 2 is executed from the CPU side bus interface unit 111 in FIG. 4A via the system bus via the system controller side bus interface unit 112 in FIG. 4B. . Control for operating the request storage unit 1 and the request storage unit 2 in cooperation is the same as the operation sequence described above with reference to FIG. That is, the memory access requests held in the request storage unit 2 in the system controller chip 107 are read by the DIMM access control unit 109 in order from those having a processable bank address, and the main memory access pipe for accessing the DIMM 110 is read. It is thrown into. The DIMM access control unit 109 generates a command and address corresponding to a bank address memory access request that can be processed from the request storage unit 2, and executes memory access to the DIMM 110. When the memory access in the DIMM 110 is completed, the main memory data response 561 is transmitted from the DIMM 110 to the data buffer 557 in the request storage unit 1. A data response from the request storage unit 2 to the data buffer 557 is executed from the system controller side bus interface unit 112 in FIG. 4B via the system bus via the CPU side bus interface unit 111 in FIG. 4A.

  Based on the transmission of the main memory data response 561, the RDY flag is set in the corresponding entry unit 550 of FIG. 5C. Here, the entry output gate 551 is provided corresponding to each entry unit 550 and determines whether or not to enable the output of each entry unit 550. The entry output gate 551 is turned on when the VAL flag of the entry unit 550 is on, the HLD flag is off, and the RDY flag is on. As described above, the RDY flag is turned on when the main memory data response 561 corresponding to the memory access request of the entry unit 550 is returned from the DIMM 110. As a result, the entry output gate 551 corresponding to the entry unit 550 is turned on, and the memory access request is output to the pipe entry entry selection unit 552.

  The pipe entry entry selection unit 552 sends memory access requests according to a predetermined rule (for example, in the oldest order) from among the memory access requests held in the entry unit 550 corresponding to the entry output gate 551 whose output is turned on. select. Then, the selected memory access request is input to the pipe input control unit 520 in FIG. 5B. At this time, the HLD flag of the corresponding entry unit 550 is set according to the output of the pipe entry entry selection unit 552. As a result, the entry output gate 551 corresponding to the entry portion 550 is always turned off. Then, unless the pipeline return notification 528 from the pipeline control unit 103 is turned on and the HLD flag is reset via the reset OR gate 553, the memory access request of the entry unit 550 is again input to the pipe input control unit 520. It will never be done. That is, the entry unit 550 waits for the execution result after the memory access request is input to the pipeline control unit 103. As a result, the request response pipe is activated on the pipeline control unit 103 (see sequence S11 in FIG. 2).

  When an abort condition is not generated in the request response pipe, the pipeline control unit 103 writes the main storage data response 561 to the cache data unit 106 and updates the tag of the cache tag unit 105 (FIG. 2 sequence S12). More specifically, the pipeline command generation unit 525 in FIG. 5B executes the following operation in accordance with the memory access request input from the pipe input entry selection unit 552 in FIG. 5C to the pipe input control unit 520 in FIG. 5B. . First, for example, the 18th to 7th bits of the address data in the memory access request are extracted to generate a tag update address 537 as an index. Next, the pipeline command generation unit 525 extracts the 39th to 19th bits of the address data, for example, and generates a request tag. Then, the pipeline command generation unit 525 outputs a tag update notification 536 to the cache tag unit 105 and also outputs a tag update address 537. As a result, the cache tag unit 105 designates a cache line corresponding to the tag update address 537, and one cache block of each cache way corresponding to the cache line is evicted. Then, the request tag is newly overwritten in the cache block. At the same time, the data response 562 temporarily stored in the data buffer 557 of FIG. 5C is written as cache data portion write data 538 in the area corresponding to the cache block on the cache data portion 106. Along with the above operation, the data response 562 is transferred to the CPU core unit 100 in FIG. 5A as a CPU data response 563 (see sequence S13 in FIG. 2). The data response to the CPU core unit 100 is executed when the memory access request is a load request and not a prefetch request.

  After the above operation of the request response pipe, the pipeline command generation unit 525 in FIG. 5B informs the request storage unit 1 to release the entry of the corresponding memory access request as a pipeline processing success notification (entry release notification) 529. Notification is made (see sequence S14 in FIG. 2). Based on this notification, in FIG. 5C, the VAL flag, RDY flag, and HLD flag of the corresponding entry unit 550 are reset, and the corresponding entry unit 550 of the request storage unit 1 is released.

  When the request response pipeline in the pipeline control unit 103 is aborted due to some factor, a pipeline return notification 528 is notified from the pipeline command generation unit 525 in FIG. 5B to the request storage unit 1 in FIG. 5C. As a result, the HLD flag of the corresponding entry unit 550 is reset via the reset OR gate 553 in FIG. 5C. As a result, the entry output gate 551 corresponding to the entry unit 550 can select the memory access request for the entry again, and the entry to the pipe entry control unit 520 in FIG. Will be tried.

  When a memory access request is registered in the request storage unit 1 from the pipeline control unit 103, the comparison (match detection) circuit 554 for each entry unit 550 has a PA address and pipeline registered in each entry unit 550. A match with the pipe address 530 notified from the control unit 103 is detected. Each AND gate 555 outputs the detection result of each comparison (match detection) circuit 554 on condition that the VAL flag of each entry unit 550 and the pipe address match detection instruction 531 given from the pipeline control unit 103 are turned on. To do. As a result, when the PA address of any valid entry unit 550 matches the pipe address 530, the address match notification 558 output via the OR gate 556 is turned on. As described above, in FIG. 5B, when the address match notification 558 is notified from the request storage unit 1, the abort OR gate 524 is turned on, and the abort is set for the pipeline command generation unit 525. In this way, the occurrence of redundant useless main memory access is suppressed.

FIG. 5D is a detailed circuit configuration diagram of the bank address equalization control unit (bank abort generation unit) 401 of FIG. 4A.
The bank abort generation unit 401 includes a bank address decoder 540, a count-up AND gate group 541, a counter group 542, a size comparison circuit group 544, a bank address decoder 548, and a count-down AND gate group 549. The bank abort generation unit 401 includes a bank address decoder 545, a bank abort notification AND gate group 546, and a bank abort notification OR gate 547.

  The counter group 542 counts the number of memory access requests to the DIMM 110 of the main storage unit for each bank 0 to 7 based on the memory access requests held in the request storage unit 1 and the request storage unit 2. To do.

  In order to realize this counting, the count-up AND gate group 541 is composed of eight AND gates corresponding to, for example, eight banks from banks 0 to 7. The result of decoding the pipe bank address 526 input from the pipeline command generation unit 525 of FIG. 5B by the bank address decoder 540 is input to each AND gate of the count-up AND gate group 541. The decoding unit 540 has a plurality of output lines such that any one of the eight outputs corresponding to the banks 0 to 7 is turned on by decoding the pipe bank address 526. Each of these output lines is input to each AND gate of the count-up AND gate group 541. If the pipe bank address 526 indicates the bank 0, only the bank 0 of the outputs of the bank address decoder 540 is turned on, and the other banks 1 to 7 are turned off. If the pipe bank address 526 indicates bank 1, only bank 1 of the outputs of the bank address decoder 540 is turned on, and the other outputs are turned off. The same applies to banks 2-7. Further, the request storage unit 1 entry acquisition notification 527 input from the pipeline command generation unit 525 of FIG. 5B is input to each AND gate of the count-up AND gate group 541. As a result, the following control is executed at the timing when the memory access request for which the request storage unit 1 entry acquisition notification 527 is issued from the pipeline command generation unit 525 is registered in the request storage units 1 and 2. The output of the AND gate in the count-up AND gate group 541 corresponding to the bank indicated by the pipe bank address 526 corresponding to the memory access request is turned on, and the counter in the counter group 542 corresponding to the bank is counted up. .

  On the other hand, at the timing when the memory access request is read from the request storage unit 2 in FIG. 5C to the DIMM access control unit 109, the request storage unit 2 entry release notification 559 indicating the release of the request storage unit 2 is sent to the request storage unit 2 in FIG. Is output from. Also, the request storage unit 2 outputs a request storage unit 2 open bank address 560 indicating the bank of the read memory access request. The request storage unit 2 entry release notification 559 and the request storage unit 2 release bank address 560 are input to the bank abort generation unit 401 in FIG. 5D. Transfer of the above two data from the request storage unit 2 to the bank abort generation unit 401 is executed from the system controller side bus interface unit 112 in FIG. 4B via the system bus via the CPU side bus interface unit 111 in FIG. 4A. Is done. Here, the countdown AND gate group 549 is composed of eight AND gates corresponding to, for example, eight banks from banks 0 to 7. Each AND gate of the countdown AND gate group 549 receives a result obtained by decoding the bank address decoder 548 of the request storage unit 2 open bank address 560 input from the request storage unit 2 of FIG. 5C. In other words, the bank address decoder 548 decodes the request storage unit 2 open bank address 560 so as to set a plurality of output lines such that any one of the eight outputs corresponding to the banks 0 to 7 is turned on. Have. Each of these output lines is input to each AND gate of the countdown AND gate group 549. If the request storage unit 2 open bank address 560 indicates bank 0, only bank 0 of the outputs of the bank address decoder 548 is turned on, and the other banks 1 to 7 are turned off. The same applies to banks 1-7. Further, a request storage unit 2 entry release notification 559 is input from the request storage unit 2 of FIG. 5C to each AND gate of the countdown AND gate group 549. As a result, the next control is executed at the timing when the memory access request is read from the request storage unit 2 and the main memory is accessed. The output of the AND gate in the count down AND gate group 549 corresponding to the bank indicated by the request bank 2 corresponding to the memory access request is turned on, and the counter in the counter group 542 corresponding to the bank counts down. Is done.

  As described above, the counter group 542 can count, for each bank, the number of memory access requests currently being processed from the L2 cache control unit 101 in FIG. 4A to the DIMM 110 in FIG. 4B.

  Next, each size comparison circuit in the size comparison circuit group 544 performs size comparison between each counter value for each bank in the counter group 542 and the threshold value set in the threshold setting register 543. The comparison result of each size comparison circuit is output as a request standby notification 514 for each bank, and is output to the bank standby control unit 402 in FIG. 5A. As described above, the bank standby control unit 402 in FIG. 4A or 5A requests a bank address corresponding to the request standby notification 514 among the memory access requests that are waiting in the entry unit 550 of the new request storage unit 102. Suppresses output of memory access requests. As a result, until the count value of the memory access request corresponding to the corresponding bank in the counter group 542 falls below a predetermined value, the corresponding memory access request is prevented from being input to the pipeline of the L2 cache control unit 101.

  The bank abort notification AND gate group 546 includes, for example, eight AND gates corresponding to eight banks from bank 0 to 7. The result of decoding the pipe bank address portion of the pipe address 530 input from the pipeline command generation unit 525 of FIG. 5B by the bank address decoder 545 is input to each AND gate of the bank abort notification AND gate group 546. In other words, the bank address decoder 545 decodes the pipe bank address portion of the pipe address 530, so that any one of the eight outputs corresponding to the banks 0 to 7 is turned on. With lines. Each of these output lines is input to each AND gate of the AND gate group 546. If the pipe bank address indicates bank 0, only bank 0 of the outputs of the bank address decoder 545 is turned on, and the other banks 1 to 7 are turned off. The same applies to banks 1-7. Further, a pipe address match detection instruction 531 input from the pipeline control unit 103 in FIG. 5B is input to each AND gate of the bank abort notification AND gate group 546. Further, the comparison result output of each size comparison circuit of the size comparison circuit group 544 is input to each AND gate of the bank abort notification AND gate group 546. As a result, when the pipe address 530 is input from the pipeline control unit 103 and the count value of the memory access request corresponding to the bank exceeds a predetermined value, the corresponding AND of the bank abort notification AND gate group 546 is displayed. The gate output is turned on. As a result, the bank abort notification 539 output from the bank abort notification or gate 547 is turned on, and the abort or gate 524 in the pipeline control unit 103 in FIG. 5B is turned on. As a result, the pipeline command generation unit 525 enters an abort state and outputs a pipeline return notification 528 to the new request storage unit 102. As a result, as described above, the corresponding entry unit 501 of the new request storage unit 102 is not released and enters a standby state, and execution of the corresponding memory access request is delayed. In addition to the operation of the bank standby control unit 402 in FIG. 5A described above, the control operation using the bank abort notification 539 from the bank abort generation unit 401 described above prevents the memory access request of the same bank from being issued excessively. be able to. Furthermore, it is possible to cause the DIMM 110 to issue a memory access request of a bank that is issued less frequently than other banks with priority. As a result, the memory access request issuance state naturally becomes a state where memory access requests of various types of banks are always stored in the request storage units 1 and 2 as illustrated in FIG. This makes it possible to equalize bank access.

  The bank access equalization will be described in more detail with reference to FIG. 3B described above. It is assumed that memory access requests for the same bank are issued continuously from the CPU core units 100 of Core 0 to 3. In this case, in the request storage unit 0 of FIG. 5A, the pipe entry entry selection unit 503 selects a memory access request from the entry unit 501 corresponding to each CPU core unit 100 and inputs it to the pipeline of the L2 cache memory. At this time, the bank standby control units 401 and 402 in FIG. 4A perform control so that memory access requests having the same bank address are not continuously input over a certain number. For example, if the count threshold value of the counter corresponding to each bank address in the counter group 542 in FIG. 5D is 1, the bank standby control unit 401 prevents the memory access requests having the same bank address from being input into the pipeline more than once. , 402 controls. As a result, in the request storage unit 0, the entry unit 501 in which memory access requests having different bank addresses are stored is preferentially selected, and the memory access request is input to the L2 cache pipeline. For example, consider a case where requests for the same bank address are stored almost simultaneously in the four entry sections 501 corresponding to Core 0, 1, 2, and 3. In this case, a memory access request having the bank address = 0 of the entry unit 501 of Core 0 is first selected and put into the pipeline. Immediately after that, if memory access requests having the same bank address = 0 are stored in the entry sections 501 of Cores 1, 2, and 3, all the outputs from them are suppressed. Then, as shown in FIG. 3B, in the entry unit 501 of Core0, immediately after the memory access request with bank address = 0 is output to the DIMM 110, the next bank address = 4 memory access requests are output to the DIMM 110. That is, the entry unit 501 selected next to the entry unit 501 of the Core 0 in which the memory access request with the bank address = 0 is stored is the entry unit 501 of the Core 1 in which the memory access request with the bank address = 4 is stored. become. In this way, the memory access request with the bank address = 4 is output immediately after the memory access request with the bank address = 0, the bank access control is equalized, and the pipeline of the L2 cache is almost interrupted. Will be able to continue. Therefore, according to the present embodiment, as shown in FIG. 3B, the banks 0, 4, 2, 6, 1, 5, 3, and 7 are equally accessed, and the Cores 0, 1, 2, and 3 are equally accessed. Is done. Then, the CPU core unit 100 can access the DIMM 110 without interruption as indicated by 304 in FIG.

  Conventionally, many memory access requests having the same bank address that cannot be processed continuously remain in the pipeline of the L2 cache, and issuance of memory access requests to the main storage unit and corresponding data responses are intermittent. This has resulted in a significant drop in pipeline processing performance. On the other hand, in the present embodiment, the L2 cache pipeline can perform processing almost without interruption, so that the throughput of the L2 cache control unit 101 can be improved.

  Here, the memory access requests for Cores 1, 2, and 3 are waited until the bank address = 0 can be output. However, after the period during which the bank address = 0 can be output, the bank address = 0 of the next Core 1 is preferentially selected, and then the memory access request of the Core 1 is continuously selected. Control may be performed as follows. If such an algorithm is provided to the pipe entry entry selection unit 552 in FIG. 5A, the processing is not biased toward a specific CPU core unit 100.

FIG. 6 is a flowchart showing the process of the operation of the first embodiment described above.
The CPU core 1602 issues a new memory access request to the L2 cache control unit 101. As a result, the memory access request is sent to the entry unit 501 (see FIG. 5A) of the request storage unit 0 (new request storage unit 102; the same applies hereinafter). Stored (step S601).

  Thereafter, in FIG. 5A, the request pipe is input from the entry unit 501 of the request storage unit 0 to the pipe input control unit 520 of FIG. 5B via the entry output gate 551 and the pipe input entry selection unit 552 (step S602).

  The tag read control unit 521 (see FIG. 5B) of the pipeline control unit 103 determines whether or not a cache miss has occurred as a result of searching the cache tag unit 105 (step S603).

  When the cache hit occurs and the determination in step S603 is NO, the pipeline command generation unit 525 in FIG. 5B determines whether the pipe processing of the request pipe has succeeded (step S604).

  If the pipe process is successful and the determination in step S604 is YES, a pipeline process success notification (entry release notification) 529 is sent from the pipeline command generation unit 525 in FIG. 5B to the request storage unit 0 in FIG. 5A. As a result, the VAL flag, HLD flag, and WAIT flag are reset in the corresponding entry unit 501 of the request storage unit 0, and the entry unit 501 is released (step S605).

  If the pipe process is not successful and the determination in step S604 is NO, the pipeline return notification 528 is notified from the pipeline command generation unit 525 in FIG. 5B to the request storage unit 0 in FIG. 5A. As a result, in the corresponding entry unit 501, the HLD flag is reset and the WAIT flag is set, and the memory access request of the entry unit 501 enters a standby state. As a result, a request pipe is repeatedly tried from the request storage unit 0 to the pipeline control unit 103 (steps S604 to S602).

  If the pipeline control unit 103 results in a cache miss and the determination in step S603 is YES, it is determined whether there is an empty entry in the request storage unit 1 (step S606). This determination function is realized by the request storage unit 1 resource counter 523 and the abort OR gate 524. That is, if the count value of the request storage unit 1 resource counter 523 is full and the request storage unit 1 resource counter value 515 indicates 1, it is determined that there is no empty entry in the request storage unit 1. If the request storage unit 1 resource counter value 515 indicates 0, it is determined that there is an empty entry in the request storage unit 1.

  If there is an empty entry in the request storage unit 1 and the determination in step S606 is YES, it is determined whether or not the number of memory access requests held in the request storage unit 1 is smaller than a predetermined threshold (step S607). Specifically, in the magnitude comparison circuit corresponding to the request bank of the magnitude comparison circuit group 544 of the bank abort generation unit 401 in FIG. 5D, the counter value corresponding to the request bank of the counter group 542 is stored in the threshold setting register 543. It is determined whether it is smaller than a predetermined threshold.

  If the determination in step S607 is YES, the bank abort notification 539 is not issued from the bank abort generation unit 401 in FIG. 5D to the abort OR gate 524 in FIG. 5B. As a result, a pipeline processing success notification (entry release notification) 529 is sent as a request release instruction from the pipeline command generation unit 525 of FIG. 5B to the request storage unit 0 of FIG. 5A. As a result, the VAL flag, HLD flag, and WAIT flag are reset in the corresponding entry unit 501 of the request storage unit 0 in FIG. 5, and the entry unit 501 is released. Also, a request storage unit 1 entry acquisition notification 527 is issued together with a memory access request from the pipeline command generation unit 525 of FIG. 5B to the entry unit 550 and the request storage unit 2 of the request storage unit 1 of FIG. 5C. The above notification from the pipeline command generation unit 525 to the request storage unit 2 is executed from the system controller side bus interface unit 112 in FIG. 4B via the system bus via the CPU side bus interface unit 111 in FIG. 4A. As a result, a memory access request is issued from the pipeline control unit 103 to the request storage unit 1 and the request storage unit 2. Further, in response to the request storage unit 1 entry acquisition notification 527, in the bank abort generation unit 401 in FIG. 5D, the count value (bank storage number) of the request bank in the counter group 542 is incremented by 1 (increment). This function is realized by the bank address decoder 540 and the count-up AND gate group 541 shown in FIG. 5D (step S608).

  Next, when the memory access request to the request storage unit 1 and the request storage unit 2 is issued, the bank abort notification 539 is not output from the bank abort generation unit 401 in FIG. 5D, so that the request bank can be processed. ing. Therefore, the DIMM access control unit 109 can select a memory access request from the request storage unit 2, and access to the DIMM 110 is executed. At the same time, the request storage unit 2 entry release notification 559 is notified from the request storage unit 2 in FIG. 5C to the bank abort generation unit 401 in FIG. 5D. As a result, in the bank abort generation unit 401 shown in FIG. This function is realized by the bank address decoder 548 and the count-down AND gate group 549 shown in FIG. 5D (step S609).

  As a result of the access to the DIMM 110, the main memory data response 561 is transferred from the DIMM 110 as the main memory unit to the data buffer 557 of the request storage unit 1 (step S610).

  Subsequently, in response to the transfer of the main memory data response 561, a request response pipe is inserted from the request storage unit 1 (step S611). This function is an operation in which, after the RDY flag is set in the corresponding entry unit 550 of the request storage unit 1 in FIG. 5C, the corresponding entry output gate 551 is turned on and the entry is selected by the pipe entry entry selection unit 552. As realized.

  As a result, the pipeline command generation unit 525 in FIG. 5B determines whether or not the pipe processing is successful (step S612).

  If the pipe processing is not successful and the determination in step S612 is NO, the pipeline control unit 103 issues a pipeline return notification 528 to the request storage unit 1. As a result, the corresponding entry output gate 551 is turned on by resetting the HLD flag in the corresponding entry unit 550 of the request storage unit 1 in FIG. 5C. As a result, the pipe entry entry selection unit 552 of the request storage unit 1 repeatedly executes the entry to the request response pipe for the memory access request of the corresponding entry unit 550 (steps S612 → S611).

  If the pipe process is successful and the determination in step S612 is YES, the pipeline control unit 103 registers data in the cache (cache tag unit 105, cache data unit 106). Thereafter, a pipeline processing success notification (entry release notification) 529 is issued from the pipeline control unit 103 to the request storage unit 1. As a result, in the corresponding entry unit 550 of the request storage unit 1 in FIG. 5C, the VAL flag, RDY flag, and HLD flag are reset, and the entry unit 550 is released (step S613).

  When the memory access request from the CPU core 1602 is a load request and not a prefetch request, the CPU core 1602 of FIG. 5A (requested from the data buffer 557 in the request storage unit 1 of FIG. 5C) The CPU data response 563 is transferred to the requesting core) (step S614). Thus, the process for one memory access request is completed.

  When the determination in step S606 or S607 described above is NO, the following control process is executed. If the determination in step S606 is NO, the count value of the request storage unit 1 resource counter 523 in FIG. This is the case when it is determined that there is no. The case where the determination in step S607 is NO is the following case. In the magnitude comparison circuit corresponding to the request bank of the magnitude comparison circuit group 544 of the bank abort generation unit 401 of FIG. This is a case where it is determined that

  First, a pipeline return notification 528 is notified from the pipeline control unit 103 to the request storage unit 0 (step S615). As a result, in the request storage unit 0 of FIG. 5A, the WAIT flag of the corresponding entry unit 501 is set, and the memory access request of the entry unit 501 enters a standby state (step S616).

  Next, in the standby state, the count value of the request storage unit 1 resource counter 523 in FIG. 5B does not become full, the request storage unit 1 resource counter value 515 indicates 0, and an empty entry occurs in the request storage unit 1 It is determined whether or not (step S617). This function is realized by the AND gate 513 in FIG. 5A.

  In the standby state, if no empty entry has yet occurred in the request storage unit 1 and the determination in step S617 is NO, the standby state in step S616 is repeated (steps S617 → S616). In this case, in FIG. 5A, since the request storage unit 1 resource counter value 515 is 1 and the WAIT flag of the corresponding entry unit 501 is 1, the output of the AND gate 513 is turned on and the output of the OR gate 512 is turned on. It becomes. As a result, the entry output gate 502 is turned off, the output of the memory access request from the corresponding entry unit 501 is suppressed, and the standby state is maintained.

  In the standby state, when an empty entry occurs in the request storage unit 1 and the determination in step S617 is YES, whether or not the number of memory access requests held by the request storage unit 1 for the request bank has become smaller than a predetermined threshold value. Determination is made (step S618). Specifically, in FIG. 5A, first, the output of the AND gate 513 is turned off when the request storage unit 1 resource counter value 515 becomes 0. As a result, the function of the AND gate group 511 becomes effective. The AND gate corresponding to each bank of the AND gate group 511 receives a request standby notification 514 corresponding to each bank from each size comparison circuit of the size comparison circuit group 544 of FIG. 5D. In each of the magnitude comparison circuits of the magnitude comparison circuit group 544 of the bank abort generation unit 401 in FIG. 5D, when the corresponding counter value of the counter group 542 is equal to or greater than a predetermined threshold stored in the threshold setting register 543, the magnitude comparison circuit is The request waiting notification 514 to be output is turned on. Each AND gate group 511 is mounted corresponding to each entry unit 501, and the AND gate group 511 is AND gate depending on the result of decoding the bank address part of the PA address registered in each entry unit 501 by the bank address decoder 510. In the group 511, only the AND gate corresponding to the bank address of the PA address of the entry unit 501 is turned on. As a result, in the AND gate in the AND gate group 511 corresponding to the request bank of the entry unit 501 that is currently processed, it is determined whether the request waiting notification 514 input thereto is OFF or ON. The Thereby, it is determined whether or not the number of memory access requests held by the request storage unit 1 is smaller than a predetermined threshold for the request bank.

  If the number stored in the request storage unit 1 is not smaller than the predetermined threshold stored in the threshold setting register 543 and the determination in step S618 is NO, the standby state in step S616, the determination in step S617, the determination in step S618 Is repeated. Specifically, if the request waiting notification 514 input to the AND gate in the AND gate group 511 corresponding to the request bank of the entry unit 501 currently processed is turned on, the AND gate The gate is turned on and the output of the OR gate 512 is turned on. As a result, the entry output gate 502 corresponding to the corresponding entry unit 501 is turned off, the output of the memory access request of the entry unit 501 is suppressed, and the standby state is maintained.

  When the number stored in the request storage unit 1 is smaller than the predetermined threshold stored in the threshold setting register 543 and the determination in step S618 is YES, the process proceeds to step S602. As a result, a request pipe is input from the request storage unit 0 to the pipeline control unit 103, and L2 cache control is executed (steps S618 → S602). Specifically, in the AND gate in the AND gate group 511 corresponding to the request bank of the entry unit 501 currently being processed, if the request waiting notification 514 input thereto is turned off, the AND gate Turn off. In addition, all other AND gates in the AND gate group 511 and the AND gate 513 are also turned off. As a result, the output of the OR gate 512 is turned off, the entry output gate 502 corresponding to the corresponding entry unit 501 is turned on, and the memory access request of the entry unit 501 can be output. As a result, the pipe entry entry selection unit 552 selects the memory access request of the corresponding entry unit 501, and inputs it to the pipe entry control unit 520 of FIG. 5B, whereby the L2 cache control is executed.

  FIGS. 7A and 7B are based on the configuration of the first embodiment of FIGS. 4A and 4B, and the main memory access part is mounted as a single chip in the main memory access function external multi-core CPU chip 1. It is a block diagram of 2nd Embodiment.

  In this configuration, the CPU side bus interface unit 111 in FIG. 4A and the system controller side bus interface unit 112 in FIG. 4B are omitted, and the function of the request storage unit 2 in FIG. Has been. The request storage unit 1 is responsible for the function of the request storage unit 2 and is the same control as in FIGS. 4A and 4B except that communication control between the request storage unit 1 and the request storage unit 2 is omitted. 7A is a detailed circuit configuration diagram of the new request storage unit 102, the bank standby control unit 402, the pipeline control unit 103, the request storage unit 1, and the bank abort generation unit 401 in FIG. 5A of the first embodiment. It is the same as 5B, FIG. 5C, and FIG. 5D.

  In the second embodiment, the request storage unit 2 entry release notification 559 and the information corresponding to the request storage unit 2 release bank address 560 of the first embodiment are transferred from the request storage unit 1 to the bank abort generation unit of FIGS. 7A and 5D. 401 is output. These pieces of information are output when the DIMM access control unit 109 in FIG. 7B reads a memory access request from the request storage unit 1 in FIG. 7A and executes access to the DIMM 110.

  According to the first and second embodiments described above, the request banks for the main memory are equalized so that even if the bank is biased for some reason, the memory access requests for the same bank are not issued excessively. I can stop. Furthermore, it is possible to preferentially issue a memory access request of a bank that is issued less frequently than other banks to the main storage unit. These functions are realized by the bank address equalization control units 401 and 402 of FIG. 4A or FIG. 7A that includes the bank abort generation unit 401 of FIG. 5D and the bank standby control unit 402 of FIG. 5A. As a result, the memory access request issuance state naturally becomes a high performance state in which memory access requests of various types of banks are always stored in the request storage units 1 and 2 as illustrated in FIG. This makes it possible to equalize bank access. Once the state of high performance is settled, even in the case of stream access, the CPU core units 100 are processed equally while maintaining the state in which the bank phases are shifted.

  In the above description of each embodiment, the description has focused on the fetch access operation for the main storage unit. In cache control using write-back control, a store request to the main storage unit occurs when a block that has been stored and rewritten by software is replaced by a new request. That is, when a fetch request is stored in the request storage unit 1, a replacement process is performed on the cache index and way secured by the fetch request. The bank of the block to be replaced is the same bank as the request in the request storage unit 1. That is, when the bank equalization for the fetch request of the main storage unit is realized, the bank equalization for the store request is necessarily realized at the same time, so the bank equalization processing for the store request is explicitly introduced. There is no need. That is, the configuration of each of the above embodiments makes it possible to realize bank equalization processing with sufficient performance.

Claims (12)

In an arithmetic processing unit connected to a storage device having a plurality of banks,
An instruction processing unit for issuing a memory access request;
A cache memory having a plurality of cache lines for holding data;
A first request holding unit that inputs a memory access request issued by the instruction processing unit;
A second request holding unit for holding a memory access request in which a cache miss has occurred;
A cache control unit that searches the cache memory based on a memory access request input from the first request holding unit and holds a memory access request in which a cache miss has occurred in the second request holding unit;
Of the memory access requests held in the second request holding unit, a third request holding unit holding a memory access request whose processing has not been interrupted;
Based on the memory access requests held in the second request holding unit and the third request holding unit, the number of memory access requests to the storage device is counted for each bank, and the memory access of any bank that has been counted When the number of requests exceeds a predetermined value, the cache control unit is instructed to interrupt the processing of the memory access request for the bank held in the first request holding unit and the number of memory access requests exceeds the predetermined value. An access counting unit,
A main storage control unit that issues a memory access request held in the third request holding unit to the storage device;
An arithmetic processing apparatus comprising: The access counting unit further includes:
Outputting a standby notification of a memory access request for a bank in which the number of counted memory access requests exceeds a predetermined value to the first request holding unit;
The first request holding unit includes:
Based on the standby notification of the memory access request output by the access counter, the memory access request to the corresponding bank is inhibited from being input to the cache controller.
The arithmetic processing apparatus according to claim 1. The access counter is
When the cache control unit holds the memory access request in the second request holding unit, it increments the count value of the bank corresponding to the memory access request,
When the main storage control unit issues a memory access request held in the third request holding unit to the main storage device, the count value of the bank corresponding to the memory access request is decremented;
The arithmetic processing apparatus according to claim 1. In an arithmetic processing unit connected to a main storage device having a plurality of banks,
An instruction processing unit for issuing a memory access request;
A cache memory having a plurality of cache lines for holding data;
A first request holding unit that inputs a memory access request issued by the instruction processing unit;
A second request holding unit for holding a memory access request in which a cache miss has occurred;
A cache control unit that searches the cache memory based on a memory access request input from the first request holding unit and holds a memory access request in which a cache miss has occurred in the second request holding unit;
Based on the memory access requests held in the second request holding unit, the number of memory access requests to the main storage device is counted for each bank, and the number of any memory access requests counted exceeds a predetermined value. An access counting unit that causes the cache control unit to suspend processing of a memory access request held in the first request holding unit;
A main storage control unit that issues a memory access request held in the second request holding unit to the main storage device;
An arithmetic processing apparatus comprising: The access counting unit further includes:
Outputting a standby notification of a memory access request for a bank in which the number of counted memory access requests exceeds a predetermined value to the first request holding unit;
The first request holding unit includes:
Based on the standby notification of the memory access request output by the access counter, the memory access request to the corresponding bank is inhibited from being input to the cache controller.
The arithmetic processing apparatus according to claim 4, wherein: The access counter is
When the cache control unit holds the memory access request in the second request holding unit, the count value of the bank corresponding to the memory access request is incremented by 1,
When the main storage control unit issues a memory access request held in the second request holding unit to the main storage device, the count value of the bank corresponding to the memory access request is decremented;
The arithmetic processing apparatus according to claim 4, wherein: In an information processing apparatus having a main storage device having a plurality of banks and an arithmetic processing device connected to the main storage device,
The arithmetic processing unit includes:
An instruction processing unit for issuing a memory access request;
A cache memory having a plurality of cache lines for holding data;
A first request holding unit that inputs a memory access request issued by the instruction processing unit;
A second request holding unit for holding a memory access request in which a cache miss has occurred;
A cache control unit that searches the cache memory based on a memory access request input from the first request holding unit and holds a memory access request in which a cache miss has occurred in the second request holding unit;
Of the memory access requests held in the second request holding unit, a third request holding unit holding a memory access request whose processing has not been interrupted;
Based on the memory access requests held in the second request holding unit and the third request holding unit, the number of memory access requests to the main storage device is counted for each bank, and the memory in any of the counted banks An access counter that interrupts the processing of the memory access request held in the first request holding unit when the number of access requests exceeds a predetermined value;
A main storage control unit that issues a memory access request held in the third request holding unit to the main storage device;
An information processing apparatus comprising: In an information processing apparatus having a main storage device having a plurality of banks and an arithmetic processing device connected to the main storage device,
The arithmetic processing unit includes:
An instruction processing unit for issuing a memory access request;
A cache memory having a plurality of cache lines for holding data;
A first request holding unit that inputs a memory access request issued by the instruction processing unit;
A second request holding unit for holding a memory access request in which a cache miss has occurred;
A cache control unit that searches the cache memory based on a memory access request input from the first request holding unit and holds a memory access request in which a cache miss has occurred in the second request holding unit;
Based on the memory access requests held in the second request holding unit, the number of memory access requests to the main storage device is counted for each bank, and the number of any memory access requests counted exceeds a predetermined value. An access counting unit (401) for causing the cache control unit to interrupt the processing of the memory access request held in the first request holding unit;
A main storage control unit that issues a memory access request held in the second request holding unit to the main storage device;
An information processing apparatus comprising: In a control method of an arithmetic processing unit having a cache memory connected to a main storage device having a plurality of banks and having a plurality of cache lines for holding data,
The instruction processing unit included in the arithmetic processing unit issues a memory access request,
A cache control unit included in the arithmetic processing unit holds a memory access request issued by the instruction processing unit in a first request holding unit included in the arithmetic processing unit;
The cache control unit searches the cache memory based on a memory access request input from the first request holding unit;
The cache control unit holds a memory access request in which a cache miss has occurred in a second request holding unit of the arithmetic processing unit;
The cache control unit holds the memory access request held in the second request holding unit in a third request holding unit included in the arithmetic processing unit;
The access counting unit included in the arithmetic processing unit counts the number of memory access requests to the main storage device for each bank based on the memory access requests held in the second request holding unit and the third request holding unit. And if the number of memory access requests counted exceeds a predetermined value, the cache control unit is suspended from processing the memory access request held in the first request holding unit,
The cache control unit issues a memory access request held in the third request holding unit to the main storage device;
A control method for an arithmetic processing unit. In the control method of the arithmetic processing unit,
The access counter is
Outputting a standby notification of a memory access request for a bank in which the number of counted memory access requests exceeds a predetermined value to the first request holding unit;
The first request holding unit suppresses the memory access request to the corresponding bank from being input to the cache control unit based on the standby notification of the memory access request output by the access counting unit.
The method of controlling an arithmetic processing unit according to claim 9. In the control method of the arithmetic processing unit,
The access counter is
When the cache control unit holds the memory access request in the second request holding unit, it increments the count value of the bank corresponding to the memory access request,
When the main storage control unit issues a memory access request held in the third request holding unit to the main storage device, the count value of the bank corresponding to the memory access request is decremented;
The method of controlling an arithmetic processing unit according to claim 9. In a control method of an information processing apparatus having a main storage device having a plurality of banks and an arithmetic processing device connected to the main storage device,
The instruction processing unit included in the arithmetic processing unit issues a memory access request,
A cache control unit included in the arithmetic processing unit holds a memory access request issued by the instruction processing unit in a first request holding unit included in the arithmetic processing unit;
The cache control unit searches the cache memory based on a memory access request input from the first request holding unit;
The cache control unit holds a memory access request in which a cache miss has occurred in a second request holding unit of the arithmetic processing unit;
The access counting unit included in the arithmetic processing unit counts the number of memory access requests to the main storage device for each bank based on the memory access request held with the second request holding unit, and When the number of memory access requests exceeds a predetermined value, the cache control unit is interrupted to process the memory access requests held in the first request holding unit,
The cache control unit interrupts processing of the memory access request held in the first request holding unit based on the access interruption instruction;
The cache control unit issues a memory access request held in the second request holding unit to the main storage device;
A method for controlling an information processing apparatus.

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