JPWO2006101159A1 - Signal processing apparatus and signal processing method - Google Patents

Abstract

Provided are a signal processing apparatus and a signal processing method for performing equalization processing that is simple in configuration, requires a small amount of calculation for adjustment, and can be converged with high accuracy. The equalizer includes a first pre-equalizer 40 that equalizes a portion before the signal time position and a first post equalizer 41 that equalizes a portion after the signal time position in cascade connection. 1 equalizer, the second post equalizer 42 and the second pre-equalizer 43 connected in cascade, the second equalizer, the first post equalizer 41 and the second pre-equalizer And an adjustment circuit 48 for independently adjusting the filter coefficients of the unit 43, and setting means for setting the adjusted filter coefficients in the second post equalizer 42 and the first pre-equalizer 40, respectively. The circuit configuration is simple, and the circuit scale and power consumption can be reduced when an IC is formed. In addition, the amount of calculation for adjustment is small, and convergence is possible with high speed and high accuracy.

Description

  The present invention relates to a signal processing apparatus and a signal processing method, and in particular, a signal processing apparatus and a signal for performing equalization processing that can be converged with high speed, high accuracy, with a simple configuration and a small amount of calculation for adjustment. It relates to a processing method.

  Conventionally, a PAM signal system has been adopted for high-speed baseband digital data transmission devices, and various equalizers and pre-emphasis circuits have been proposed to compensate for large losses in the high band of the transmission path. ing. As the equalizer, for example, there is a well-known equalizer using a transversal type (FIR) filter.

  FIG. 7 is a block diagram showing a configuration example of a conventional equalizer. The input signal Y input to the shift register 100 is delayed, multiplied by the filter coefficient set in the register 103 by the multipliers 101 and 102, added by the adder 104, and output. In addition, the reference signal is subtracted from the output signal and input to the adjustment algorithm arithmetic circuit 106 to adjust the filter coefficient.

  As the adjustment algorithm, a well-known stochastic gradient method (LMS) or Kalman filter method is employed. Patent Document 1 below discloses a configuration in which an equalizer using a transversal filter is adjusted by switching between the Kalman filter method and the LMS method.

Recently, a THP (Tomlinson Harashima Precoding) system has been attracting attention as a baseband data transmission using a metal wire. This THP method is an improvement of the pre-emphasis method, and inserts a modulo arithmetic circuit in the middle of a pre-emphasis circuit using a FIR filter that simulates a transmission line, thereby suppressing the amplitude of the transmission signal within a predetermined range. It is a method to do. Non-Patent Document 1 below discloses a THP waveform adjustment technique.
JP 2001-196978 A `` Matched-Transmission Technique for Channels With Intersymbol Interference '' IEEETRANSACTIONS ON COMMUNICATIONS, VOL.COM-20, NO.4 AUGUST 1972 774-780 pages

  For example, when high-speed digital data transmission such as 1 Gbps is performed, it is necessary to adjust the equalizer corresponding to a short symbol interval. Therefore, if the adjustment algorithm is not small in calculation amount, the calculation will not be in time. However, the Kalman filter method has a problem that the calculation is complicated and the calculation amount is large, so that the calculation is not in time, and the convergence speed of fine components is slow.

  On the other hand, the LMS method has a relatively small amount of calculation but has a slow convergence speed. If the frequency characteristic of the transmission line is greatly reduced over a wide band, it takes a long time to converge or may not converge. It was.

  In addition, when the above THP method is adopted, it is necessary to equalize the characteristics of the transmission path including the characteristics of the THP precoder. Therefore, the conventional training method using the PN (pseudo noise) code is not used as it is. There was a problem that it could not be adopted. The present invention provides a signal processing apparatus and a signal processing method for solving the above-described problems of the prior art, performing equalization processing that is simple in configuration, requires a small amount of calculation for adjustment, and can be converged at high speed and high accuracy. The purpose is to do.

The signal processing apparatus of the present invention includes a first pre-equalizer means for equalizing a portion before the signal time position and a first post-equalizer means for equalizing the portion after the signal time position. Cascade-connected first equalizer means, second post equalizer means for equalizing the portion after the signal time position, and second pre-equalizer for equalizing the portion before the signal time position A second equalizer means in cascade with each other, a first adjustment means for adjusting a filter coefficient of the first post equalizer means, and a filter coefficient of the second pre-equalizer means. Second adjusting means for adjusting, first setting means for setting the filter coefficient adjusted by the first adjusting means in the second post equalizer means, and adjusting by the second adjusting means Second setting means for setting the filtered filter coefficient also in the first pre-equalizer means The main feature that. Here, the signal time position is uniquely determined, and its meaning is described in Non-Patent Document 2 below.
Yoichi Sato, "Linear Equalization Theory", Maruzen Publishing 1990, Chapter 2 Inverse System, Section 2.3, pp. 50-57

  In the signal processing apparatus, the first pre-equalizer means, the first post-equalizer means, the second post-equalizer means, and the second pre-equalizer means are each an FIR filter circuit. It is also characterized by

  In the signal processing apparatus described above, the first and second adjustment units are also characterized in that the filter coefficients are adjusted using the stochastic gradient method.

  Further, in the signal processing apparatus described above, reference signal generating means for generating a reference signal synchronized with a transmission training signal obtained by passing the PN signal through the THP precoder, output signal of the first equalizer means, and the reference A first error signal generating means for calculating a difference from the signal and outputting the difference to the first adjusting means; a difference between the output signal of the second equalizer means and the reference signal; And a second error signal generating means for outputting to the second adjusting means.

  The signal processing method of the present invention comprises a first pre-equalizer means for equalizing a portion before a signal time position, and a first post-equalizer means for equalizing a portion after the signal time position. In the first equalizer means connected in cascade, the first step of adjusting the filter coefficient of the first post equalizer means and the signal time position after the first step in parallel with the first step. In the second equalizer means in which the second post equalizer means for equalizing the part and the second pre-equalizer means for equalizing the part before the signal time position are connected in cascade, the second equalizer means A second step of adjusting the filter coefficient of the pre-equalizer means, the filter coefficient adjusted by the first adjusting means is also set in the second post equalizer means, and the second The filter coefficient adjusted by the adjusting means is converted into the first pre-equalizer. Repeating a third step of setting in stages and main features.

  The signal processing device and the signal processing method of the present invention have the effects that the circuit configuration is simple and the circuit scale and power consumption when an IC is formed can be reduced by the above configuration. In addition, there is an effect that the amount of calculation for adjusting the filter coefficient is small and high-speed adjustment is possible. Furthermore, there is an effect that the equalizer can converge with high speed and high accuracy. Also, by compensating the frequency characteristics of the transmission line by the THP precoding means on the transmission side and the equalizer means on the reception side, the stability of the THP loop is increased, and the number of THP precoder stages can be reduced. There are also effects such as being able to.

FIG. 1 is a block diagram showing the configuration of the entire transmission apparatus of the present invention. FIG. 2 is a block diagram showing a partial configuration of the equalizer circuit 34 and the receiving side training control circuit 38. FIG. 3 is a block diagram showing the configuration of the equalizer circuit 34. FIG. 4 is a block diagram showing a configuration example of the U, V equalization algorithm calculation circuit 48. As shown in FIG. FIG. 5 is a block diagram showing the configuration of the THP precoder 14. FIG. 6 is a flowchart showing the contents of the training process. FIG. 7 is a block diagram showing a configuration example of a conventional equalizer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Transmission circuit 11 ... Code converter 12 ... PN signal generation circuit 13 ... Switch 14 ... THP precoder 15 ... D / A converter 16 ... Amplifier 17 ... Transmission side training control circuit 20 ... Hybrid circuit 21 ... Transmission cable 30 ... Reception Circuit 31 ... Variable gain amplifier 32 ... A / D converter 33 ... Symbol synchronization circuit 34 ... Equalizer circuit 35 ... Level determination circuit 36 ... Modulo calculator 37 ... Sign inverse conversion circuit 38 ... Reception side training control circuit

  The equalizer of the present invention was developed on the premise that it is used for an ultrahigh-speed digital data transmission device (LAN) of several Gbps or more using a balanced cable or a coaxial cable represented by a twisted pair cable. In this embodiment, an example in combination with the THP method will be described. However, the equalizer of the present invention is not limited to this, and can be applied to an apparatus for transmitting an arbitrary signal.

  FIG. 1 is a block diagram showing the configuration of the entire transmission apparatus of the present invention. This embodiment consists of a full-duplex data transmitter / receiver of the same configuration connected to both ends of the transmission cable 21. For example, in 10 Gigabit Ethernet (registered trademark), four sets of the transmission apparatus of FIG. 1 are used.

  The transmission circuit 10 includes a code converter 11, a PN signal generation circuit 12, switches 13 and 16, a THP precoder 14, a periodic signal generation circuit 15, a D / A converter (DAC) 17, an amplifier 18, and a transmission side training control circuit 19. Consists of. The code converter 11 divides the transmission data into predetermined bits and outputs one of a plurality of signal levels (voltage values) corresponding to the value of the bit string.

  FIG. 5 is a block diagram showing the configuration of the THP precoder 14. (A) is a functional block diagram. The THP precoder 14 includes an adder 90, a modulo arithmetic unit 91 modulo a multi-valued number of symbols, and an FIR filter 92. A filter coefficient corresponding to the average impulse response of the transmission path is set in the FIR filter 92 in advance. The FIR filter 92 receives and processes the output of the modulo arithmetic circuit 91 and outputs it to the adder 90. The adder 90 subtracts the output of the FIR filter 92 from the input signal and outputs it.

FIG. 5B is a diagram showing a more specific circuit configuration of the THP precoder 14. The adder 93 has both the function of the adder 90 and the function of the adder of the FIR filter 92. A plurality of delay circuits 94 which are components of the FIR filter 92 is a register for delaying signal 1 signal (symbol) period, the multiplier 95 is the coefficient of the impulse response of the channel (-a ₁ ~-a _n ). The number of stages of the FIR filter is, for example, 16 to 64.

  Returning to FIG. 1, the output of the THP precoder 14 is converted into an analog signal by the DAC 17, amplified by the amplifier 18, and transmitted via the hybrid circuit 20. The transmission side training control circuit 19 controls, for example, the switches 13 and 16, the PN signal generation circuit 12, the THP precoder 14, and the periodic signal generation circuit 15, and executes a training process described later.

  Next, the receiving circuit will be described. The reception circuit 30 includes a variable gain amplifier 31, an A / D converter (ADC) 32, a symbol synchronization circuit 33, an equalizer circuit 34, a level determination circuit 35, a modulo calculator 36, a sign inverse conversion circuit 37, and a reception side training control circuit. 38, an AGC circuit 39, and the like.

  The variable gain amplifier 32 amplifies the received signal so as to have a predetermined signal level under the control of the AGC circuit 39. The symbol synchronization circuit 33 regenerates a symbol synchronization signal (clock) from the received signal, and the ADC 32 A / D converts the received signal based on the symbol synchronization signal. The equalizer circuit (equalizer) 34 according to the present invention equalizes the frequency characteristics of the transmission line including the THP precoder 14 by the configuration described later. Therefore, in this embodiment, the equalizer circuit 34 equalizes the difference between the filter coefficient indicating the transmission line characteristic set in the THP precoder 14 and the frequency characteristic of the actual transmission line. There are many well-known methods for symbol synchronization, but the outline is as follows. First, periodic data is transmitted in initial training to establish symbol synchronization in advance, and subsequently follow-up control is performed after PN sequence transmission. The follow-up control includes a means for referring to the opening degree of the eye and a means for referring to the coefficient of the equalizer, but there is no method for clearly obtaining the control direction. According to the equalization of the present invention, the control direction of the sampling phase can be clearly obtained, and high-speed phase control becomes possible.

  The level determination circuit 35 is a circuit for determining in which region of the multi-level signal the received signal is, and when the input signal level is within a predetermined range of the multi-level signal, multi-level digital information corresponding to that range is obtained. Output. The modulo arithmetic unit 36 is a modulo arithmetic circuit having the same characteristics as the modulo arithmetic unit 91 in the THP precoder 14. The sign inverse converter 37 inversely converts the output of the modulo calculator 36 into the original bit information. The receiving side training control circuit 38 adjusts the filter coefficient of the equalizer circuit 34 using the training signal as described later.

FIG. 2 is a block diagram showing a partial configuration of the equalizer circuit 34 and the receiving side training control circuit 38. The equalizer circuit 34 includes four FIR filter circuits 40 to 43. Two pre-equalizers U (z ⁻¹ ) 40, 43 for equalizing the part before the signal time position, and two post equalizers V (z ⁻¹ ) for equalizing the part after the signal time position ) 41 and 42 perform the same function, and a set of a pre-equalizer U (z ⁻¹ ) 40 and a post equalizer V (z ⁻¹ ) 41, and a post equalizer V (z ⁻¹ ) 42 and Each set of pre-equalizers U (z ⁻¹ ) 43 constitutes one equalizer. The filter coefficients of the equalizers 40 to 43 are adjusted by the U and V equalization algorithm calculation circuit 48.

The output of the pre-equalizer U (z ⁻¹ ) 43 and the output of the post-equalizer V (z ⁻¹ ) 41 are level determination circuits 35 and 35 ′ and two adders 45, 45 ′, 46 and 46 ′, respectively. Is input to one of the The other of the adders 45 and 45 ′ receives a training reference signal generated from the shift circuit 56 and generated on the receiving side. The adders 45 and 45 'output error signals during training, respectively.

  The other of the adders 46 and 46 'receives the reception level signal output from the level determination circuit, and the adder 46 and 46' outputs an error signal during data transmission. Based on the control from the data head decision circuit, the switches 47 and 47 ′ perform U and V equalization algorithm operations on the output A of the adders 45 and 45 ′ during training and the output B of the adders 46 and 46 ′ during data transmission, respectively. It outputs to the circuit 48.

The PN signal head determination circuit 50 detects the head of the PN signal from the received digital signal and activates the PN signal generation circuit 51. The PN signal generation circuit 51 generates the same signal as the PN signal generation circuit 12 on the transmission side. An adder 54, a modulo arithmetic circuit Mod (L) 52, and an FIR filter P (z ⁻¹ ) 53 are reception side THP precoders having the same configuration as the transmission side precoder 14, and are added to the FIR filter P (z ⁻¹ ) 53. Has the same filter coefficients as those on the transmission side.

  The shift determination circuit 55 is a circuit for accurately synchronizing the signal time position of the reception signal with the signal time position of the THP generated on the reception side, and the signal time position of the reception signal and the signal time of the reception side THP. It is determined how many clocks the position shift has, and the shift number (delay amount) of the shift circuit 56 that shifts the input signal of the modulo arithmetic circuit 52 is controlled, and the signal delayed by a predetermined amount in the equalizer circuit 34 Take the synchronization. Note that the function of the shift determination circuit 55 is executed by a DSP, for example. The eye opening degree determination circuit 57 detects the stop of the reference signal and switches the switches 47 and 47 '.

FIG. 3 is a block diagram showing the configuration of the equalizer circuit 34. The two pre-equalizers U (z ⁻¹ ) 40 and 43 equalize the portion before the signal in time, and the two post equalizers V (z ⁻¹ ) 41 and 42 temporal in time than the signal. The filter coefficients are set so as to equalize the later part. A set of pre-equalizer U (z ⁻¹ ) 40 and post-equalizer V (z ⁻¹ ) 41, and post-equalizer V (z ⁻¹ ) 42 and pre-equalizer U (z ⁻¹ ) 43 Each of these sets constitutes one equalizer, and the output is the same even if the processing order of the pre-equalizer and post-equalizer is changed.

Each equalizer circuit comprises a well-known FIR filter circuit having the same configuration. For example, the pre-equalizer U (z ⁻¹ ) 40 includes a shift register 60 that shifts an input signal step by step based on a clock signal, a register (U) 64 in which a filter coefficient is set, and a shift register 60. It comprises a plurality of multipliers 61 and 62 for multiplying the output of the stage and the filter coefficient output from the register (U) 64, and an adder 63 for adding the outputs of each multiplier.

FIG. 4 is a block diagram illustrating a configuration example of the U / V equalization algorithm calculation circuit 48. A stochastic gradient method is used as the algorithm. The conventional probabilistic gradient method according to FIG. 7 is expressed as follows. W _k is a filter coefficient matrix composed of a plurality of filter coefficient values. ε is a coefficient, Y _K is an input signal matrix of the filter, Z _K is an output signal value of the filter, and a _k is a reference signal value. By repeating this calculation, the filter coefficient is updated.

W _{k + 1} = W _k −ε · Y _k (Z _k −a _k )

In the present invention, the pre-equalizer U (z ⁻¹ ) 43 and the post equalizer V (z ⁻¹ ) 41 are independently updated using this stochastic gradient method, and the update result is pre-equalized. Also used as filter coefficients of the equalizer U (z ⁻¹ ) 40 and the post equalizer V (z ⁻¹ ) 42. The filter coefficient update processing of the pre-equalizer U (z ⁻¹ ) 43 and the post equalizer V (z ⁻¹ ) 41 is expressed as follows:

V _{k + 1} = V _k −ε · _{P k} (Z _k −a _{kN / 2} )
U _{k + 1} = U _k −ε · Q _k (Z ′ _k −a _{kN / 2} )

V _k and U _k are filter coefficient matrices including a plurality of filter coefficient values. ε is a coefficient, P _K and Q _K are input signal matrices of the respective filters, Z _K and Z ′ _K are output signal values of the respective filters, and a _{kN / 2} is a reference signal value at a time position corresponding to the output signal. is there. By repeating this calculation, the filter coefficients V _k and U _k are updated.

FIG. 4 is an example in which the above calculation is executed by hardware. The adder 45 outputs a signal (Z _k −a _{kN / 2} ) _obtained by subtracting the reference signal from the output Zk of the post equalizer V (z ⁻¹ ) 41. The multiplier 81 multiplies this signal by a coefficient value ε, and the output value ε · (Z _k −a _{kN / 2} ) is input to a plurality of multipliers 79 and 80. The plurality of multipliers 79 and 80 multiply the output value of the multiplier 80 by the output P _{k of the} pre-equalizer U (z ⁻¹ ) 40 input to the shift register 82, and the signal ε · P _k (Z _k− a _{kN / 2} ) is output.

The plurality of adders 77 and 78 latch the values obtained by subtracting the output signals of the plurality of multipliers 79 and 80 from the respective filter coefficient values of the V register 76 in the V register 76 again to update the filter coefficients. The same calculation is performed for the U register 70 to update the filter coefficient. The value of the V register 76 is set to the two post equalizers V (z ⁻¹ ) 41 and 42, and the value of the U register 70 is set to the two pre equalizers U (z ⁻¹ ) 40 and 43. The

  The reason why this equalizer can converge faster than the transversal equalizer can be explained as follows. When the convergence of the pre-equalizer U and the post-equalizer V advances a little, equalization of the high-frequency part of (channel + U) and (channel + V) advances, and these high-frequency spectra are slightly lifted. As a result, the small eigenvalue of the correlation matrix between the received signal of the equalizer V (channel + U output) and the received signal of the equalizer V (channel + V output) is slightly increased. As a result, the convergence of the equalizers U and V is slightly accelerated. This effect is reflected in the equalizers U and V in the front part and raises the high-frequency spectrum. In this way, a synergistic effect is exhibited and convergence is accelerated more and more.

  Note that the filter coefficient update period may be longer than the symbol interval (clock period), and therefore the filter coefficient may be updated by executing the stochastic gradient method by software processing using a DSP.

  FIG. 6 is a flowchart showing the contents of the training process. In this embodiment, it is assumed that filter coefficients corresponding to the average impulse response of the transmission path are set in advance in the THP precoder 14 and the filter circuit 53 in the equalizer circuit. The training is different from the conventional transversal equalizer in that the timing of inserting the PN signal at the time of training (reference signal timing) is unique. Therefore, an algorithm for estimating the insertion timing has been added.

  In S10, the transmission circuit switches the switch 16 to the periodic signal generation circuit 15 side and sends out a periodic signal. In S11, the transmission circuit waits until a predetermined time elapses. The reception circuit waits until signal power is detected in S30, and starts the AGC operation of the AGC circuit 39 and starts symbol synchronization processing of the symbol synchronization circuit 33 in S31.

  The transmission circuit stops the periodic signal in S12, switches the switch 13 to the PN signal generation circuit 12 side in S13, and transmits the PN signal via the THP precoder 14. The transmission circuit waits until a predetermined time elapses while sending out the PN signal in S14, and starts data transmission in S15.

In S32, the reception circuit detects the stop of the periodic signal by the PN signal head determination circuit 50, and in S33, activates the local PN signal generation circuit 51 to start generation of the PN signal. In S34, PN signal synchronization processing (processing by the shift determination circuit 55 described above) is performed to achieve accurate synchronization with the received signal. The basic principle is based on zero-forcing equalization, and only the result of the algorithm is as follows.

Step (1) The correlation between the reference signal and the received signal is obtained, and the timing with the largest correlation is obtained. This timing is described as t = 0.
Step (2) it is first started equalization processing at this timing, U (z ^-1) of the inverse system 1 / U (z ^-1) and V (z ^-1) of the inverse system 1 / V (z ^-1 ) To determine whether they diverge or converge.

Step (3) If both converge, t = 0 is determined as the correct timing. If not, the determination of step (2) is sequentially executed at t = −3, −2, −1, 1, 2, 3 to find the timing when both converge.

The timing at which both converge is always found by this algorithm, and either 1 / U (z ^-1 ) or 1 / V (z ^-1 ) diverges at other timings. Also, this determination can be made at an early stage after the start of the equalization algorithm.

1 / U (z ^-1 )
And 1 / V (z ^-1 )
u ₀ , u ₁ , u ₂ , u ₃ , ...
v ₀ , v ₁ , v ₂ , v ₃ , ...
And At this time, for example, the second moment
Mu = u ₁ ² +2 ² u ₂ ² +3 ² u ₃ ² +
Mv = v ₁ ² +2 ² v ₂ ² +3 ² v ₃ ² +
Observe. If Mu> Mv, it can be seen that the sampling phase is shifted forward from the optimal time, and if Mu <Mv, it is shifted backward from the optimal time. Therefore, the control direction of the sampling phase can be detected, and the sampling phase can be optimally adjusted so that Mu = Mv.

  In response to the determination in S34, the receiving circuit executes the compulsory training process for the equalizer in S35. In S36, the output of the PN sequence generation circuit 51 of FIG. 2 is monitored, and the end time of the transmission PN sequence is calculated. A time point earlier than the end time is determined in advance, and S35 is continued until that time, but after that time, the temporary determination adaptive equalization process of S37 is executed.

  Although the embodiments have been disclosed above, the present invention may be modified as follows. In the embodiment, the configuration in which the equalizer circuit is digitally processed after the A / D converter is disclosed. However, the equalizer of the present invention may be placed in an analog circuit immediately before AD conversion. In this case, the circuit configuration is the same although there is a difference between digital and analog.

Although an example in which the impulse response coefficient set in the THP precoder 14 is fixed is disclosed, a test signal is transmitted from the transmission side, and an impulse response coefficient set in the THP precoder 14 returned from the circuit on the reception side is acquired. The THP precoder 14 may be set.

Claims (5)

A first equalization in which a first pre-equalizer means for equalizing a part before the signal time position and a first post-equalizer means for equalizing a part after the signal time position are connected in cascade. Instrument means,
A second equalizer in which a second post equalizer means for equalizing the portion after the signal time position and a second pre-equalizer means for equalizing the portion before the signal time position are connected in cascade. Means,
First adjusting means for adjusting a filter coefficient of the first post equalizer means;
Second adjusting means for adjusting a filter coefficient of the second pre-equalizer means;
First setting means for setting the filter coefficient adjusted by the first adjusting means to the second post equalizer means;
A signal processing apparatus comprising: a second setting unit that sets the filter coefficient adjusted by the second adjustment unit also in the first pre-equalizer unit.   The first pre-equalizer means, the first post-equalizer means, the second post-equalizer means, and the second pre-equalizer means each comprise an FIR filter circuit. 2. The signal processing apparatus according to 1.   2. The signal processing apparatus according to claim 1, wherein each of the first and second adjustment units adjusts a filter coefficient using a stochastic gradient method. A reference signal generating means for generating a reference signal synchronized with a transmission training signal that has passed the PN signal through the THP precoder;
First error signal generation means for calculating a difference between the output signal of the first equalizer means and the reference signal and outputting the difference to the first adjustment means;
Second error signal generating means for calculating a difference between the output signal of the second equalizer means and the reference signal and outputting the difference to the second adjusting means;
The signal processing apparatus according to claim 1, further comprising: A first equalization in which a first pre-equalizer means for equalizing a part before the signal time position and a first post-equalizer means for equalizing a part after the signal time position are connected in cascade. A first step of adjusting a filter coefficient of said first post equalizer means;
In parallel with the first step, a second post equalizer means for equalizing the portion after the signal time position and a second pre-equalizer means for equalizing the portion before the signal time position A second step of adjusting a filter coefficient of the second pre-equalizer means;
The filter coefficient adjusted by the first adjusting means is also set in the second post equalizer means, and the filter coefficient adjusted by the second adjusting means is set in the first pre-equalizer means. A signal processing method characterized by repeating the third step to be set.

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