JPWO2004003758A1 - Directional coupled bus system - Google Patents

Abstract

In a system composed of a board equipped with a memory module having a plurality of memories and a memory controller for controlling the memory module, a directional coupler is used to transfer data signals between the memory controller and the memory module. The main transmission line and the sub-transmission line are connected to each other in the first form in a DC manner, and the command and address signals are transferred between the memory controller and the memory module in the first form or in a direct and alternating manner. In the second type, a register for transferring command and address signals to a plurality of memories is provided, and the directional coupler and the register are mounted on the memory module or board. As a result, the data transfer rate of the command and address bus can be increased.

Description

  The present invention relates to a signal transmission technique between elements such as a multiprocessor and a memory in an information processing apparatus (for example, between digital circuits constituted by CMOSs or between functional blocks thereof), and in particular, a plurality of elements are connected to the same transmission line. The present invention relates to a technology for speeding up data transfer on a designated bus. In particular, the present invention relates to a system using a bus connecting a memory controller and a plurality of memory modules.

In a memory system in which a plurality of devices are connected on a transmission line connecting a memory controller (hereinafter referred to as MC) and a terminating resistor, a data signal transferred bidirectionally between the MC and the memory has a clock frequency of 2 There is a memory system using a DDR SDRAM (Double Data Rate Synchronous DRAM) having a double data transfer rate. Hereinafter, this memory system is referred to as a DDR memory system. In this DDR memory system, a command signal indicating a state such as read or write and an address signal indicating an address for access, which are transferred in one direction from the MC to the memory, have the same data transfer speed as the clock frequency, that is, the data signal The data transfer rate is 1/2 of that.
One of the bus systems for realizing this DDR memory system is a system called SSTL (Stub Series Terminated Logic). FIG. 24 shows a configuration diagram when the command and address bus and the data bus are both SSTL. The memory system includes a board 100, a plurality of memory modules (hereinafter abbreviated as modules) 20 on which a plurality of memories 10 are mounted, a plurality of connectors 50 for connecting the board and the modules, and a memory control mechanism. MC1, a plurality of registers 2 for transferring command and address signals to a plurality of memories on the module 20, a plurality of resistance elements 60 called stub resistors, and the farthest end of the transmission line as viewed from MC1 It comprises a termination resistor 61 (not shown) arranged and connected to an appropriate termination voltage Vtt, a data bus 40 comprising a plurality of wirings having branches, and a memory bus comprising an address and command bus 30.
In FIG. 24, for convenience of explanation, one bus wiring, four modules, one register and four memories are shown on each module, but actually, depending on the bus width. In addition, there are a plurality of bus lines, modules not limited to four, and a plurality of devices not limited to one register and four memories on each module. A plurality of memories may be mounted on the front and back of the module. FIG. 24 shows a memory module in which a signal is transferred to the memory via a register, that is, a memory module called Registered DIMM (Dual In-line Memory Module). This Registered DIMM usually has a device called PLL (Phase Locked Loop) having a function of distributing a clock signal to the register 2 on the module 20 and the plurality of memories 10. Not.
Further, a method for increasing the data transfer rate of the bus more than the SSTL is described in, for example, Japanese Patent Application Laid-Open No. 2001-256772 (US Application No. 09/803148) “Memory Module”. Although there is no general name for this method, it will be referred to as SLT (Stub Less Terminated Logic) in this specification for convenience of explanation.
FIG. 25 shows a configuration diagram when the command and address buses and the data bus are both SLTs. This memory system transfers commands and address signals to the board 100, the plurality of modules 20, the plurality of connectors 50 for connecting the board 100 and the module 20, the MC1, and the plurality of memories on the module 20. A plurality of registers 2, a terminal resistor (not shown) arranged at the farthest end of the transmission line as viewed from MC 1 and connected to an appropriate termination voltage Vtt, and a data bus 40 comprising a single-stroke wiring without branching The memory bus is composed of an address and command bus 30. As is apparent from the figure, the transmission lines in the data bus 40 and the address and command bus 30 have no branches. Further, by performing impedance matching in a lumped constant circuit near the device of the memory 10 or the register 2, signal reflection can be significantly suppressed as compared with the SLT. For this reason, the data transfer speed of the bus can be increased in the SLT as compared with the SSTL.
Further, methods for increasing the data transfer rate of the bus compared to SLT are disclosed in, for example, Japanese Patent Application Laid-Open No. 07-141079 (USP 5638402) “Non-Contact Bus” and Japanese Patent Application Laid-Open No. 2001-027987 (US Application No. 09/569876). ) "Directionally coupled memory system". In this specification, for the sake of explanation, this transfer method is referred to as XTL (Crosstalk Transfer Logic).
FIG. 26 shows a configuration diagram when the command and address bus is the SSTL and the data bus is XTL. This memory system includes a board 100, a plurality of modules 20, a plurality of connectors 50 for connecting the board 100 and the modules 20, MC1, a data bus 40 as a main transmission line extending from MC1, and the MC1. A terminating resistor (not shown) arranged at the farthest end of the main transmission line and connected to an appropriate terminating voltage Vtt, a data bus 41 as a sub transmission line extending from the memory 10, and the memory 10 The main transmission line and the sub-transmission line are separated into a direct current and an alternating current by a terminating resistor (not shown) disposed at the farthest end of the sub-transmission line and connected to an appropriate termination voltage Vtt, and inductive and capacitive coupling. It is comprised with the directional coupler 70 connected to this.
Note that this configuration only shows one form of XTL, and the form for realizing XTL is not limited to this. The state of signal transmission in XTL is as described in Japanese Patent Application Laid-Open No. 07-141079, “Non-Contact Bus”, but will be briefly described here.
The data signal output from MC1 propagates on the main transmission line 40. When the signal reaches the directional coupler 70, a backward crosstalk signal directed toward the memory 10 is generated on the sub-transmission line 41 by the action of the directional coupler 70. Usually, in the crosstalk, a front crosstalk signal directed toward the terminating resistance on the sub-transmission line 41 is also generated. However, the front crosstalk signal is generated by configuring the directional coupler with a strip line. It can also be prevented. Now, as shown in FIG. 27, the signal transmitted on the sub-transmission line 41 is an RTZ (Return To Zero) of a shape obtained by differentiating the NRZ (No Return to Zero) signal (A) transmitted on the main transmission line. Zero) Each memory 10 is reached in the state of the signal (B). This RTZ signal is detected and output in the memory 10 by, for example, the voltage comparison circuit 5 using the voltage Vref1 slightly larger than the termination voltage Vtt and the voltage Vref2 slightly smaller than the termination voltage Vtt by the input circuit 4 ′ shown in FIG. ) And restored to the original NRZ signal (D) by the demodulation circuit 6. Since the input portion of the memory 10 is not terminated, the signal reaching the memory 10 is almost totally reflected and travels toward the directional coupler 70 again. However, since the reflected wave is absorbed by the terminal resistor (not shown), multiple reflection does not occur on the sub-transmission line 41. As described above, in XTL, a main transmission line and a sub-transmission line are separated in a direct current through a directional coupler and connected in an alternating manner, and each transmission line having no branch is distributed like a distributed constant circuit. By impedance matching, the bus data transfer speed can be increased compared to the SSTL and SLT.

In the first conventional example, because of the transfer method using SSTL, signal reflection occurs at each branch point of the transmission line due to impedance mismatch due to branch wiring and branching. Stub resistors are installed to suppress signal reflection at these points, but as signal frequency increases, it becomes difficult to suppress reflection, and signal quality deteriorates due to multiple signal reflections. There was a problem that the increase in data transfer speed was limited. On the other hand, in the second conventional example, since the transmission system is based on SLT, there is no branch like SSTL in the transmission line, so that the signal quality can be improved as compared with the case of SSTL. However, although there is no branching on the transmission line, impedance mismatching occurs for signals in the frequency domain where it is necessary to handle the area where impedance matching is performed as a lumped constant circuit as a distributed constant circuit. As a result, there is a problem that even if this SLT is used, the increase in data transfer speed is limited. Furthermore, in the third conventional example, since the data bus uses the XTL transfer method, the bus data transfer speed can be increased as compared with the SSTL or SLT described above. Has a problem that the data transfer speed of the memory system is limited. In summary, in the first conventional example, the data transfer rate of both the command and address buses and the data bus is limited by the SSTL transfer method. In the second conventional example, the data transfer rate of the data bus is Limited by the SLT transfer method, in the third conventional example, the data transfer rate of the command and address bus is limited by the SSTL transfer method, which limits the speeding up of the data transfer of the entire memory system. There was a problem.
An object of the present invention is to provide a memory system capable of speeding up data transfer.
Another object of the present invention is to provide an inexpensive memory system capable of speeding up data transfer by reducing the number of command and address bus lines between a memory controller and a register.
In order to achieve the above object, the present invention provides a command and address bus in which the data bus is a transfer system using a main transmission line and a sub-transmission line that are separated in a direct current and connected in an alternating manner through a directional coupler. Has a register between the MC (memory controller) and the memory, and transfers signals to a plurality of memories via the register.
In a preferred example (first example) relating to the transfer of the command and address bus, the MC and the register are connected by a one-stroke wiring without branching. As a result, the data transfer rate is not limited by SSTL for the command and address buses, and the data transfer rate is not limited by SLT for the data buses. For this reason, it is possible to construct a memory system capable of speeding up data transfer as compared with the prior art.
In the preferred example (second example) relating to the transfer of the command and the address bus, a signal is transferred by a main transmission line and a sub-transmission line which are separated in a direct current and connected in an alternating manner through a directional coupler. Is. This makes it possible to increase the data transfer speed of the memory system as compared with the case where the transfer method according to the first example is used.
Further, in a preferred example (third example) relating to the command and address bus transfer, the MC and the first register are connected one-to-one by a plurality of wirings without branching, and the registers after the first register are also connected. Similarly, signals are transferred by being connected one-to-one by a plurality of wirings without branching, and these registers are mounted on a board or module, and signals are transferred to a plurality of memories via the registers. As a result, regarding the command and address bus, the data transfer speed can be increased as compared with the case where the transfer method according to the second example is used. In this case, the data transfer rate of the entire memory system is limited by the data transfer rate of the data bus. In other words, the data transfer speed of the memory system is the same as that of the transfer method according to the second example, and the data transfer speed of the memory system can be increased as compared with the case of using the transfer method of the first example. is there.
In order to achieve another object of the present invention, the data bus is a transfer system using a main transmission line and a sub-transmission line that are separated and connected in a DC manner through a directional coupler. The address bus has a register between the MC and the memory, and is configured to transfer a signal to a plurality of memories via the register, and further to a data signal transfer speed (first data transfer speed) on the data bus. By multiplexing the command and address signal (MUX) in MC, the second data transfer rate in the command and address signal transferred to the register is increased to the same or twice the first data transfer rate. , By demultiplexing (DEMUX) in the register, a third command and address signal transferred from the register to the plurality of memories. The data transfer rate, characterized by configured to half of the first data transfer rate. As a result, the number of command and address bus lines on the board can be minimized and reduced to 1/2 or 1/4. In this case, since the number of output units corresponding to the reduced number of wires is not required in the MC, the number of MC balls and the chip area are reduced, so that the manufacturing cost of the MC can be reduced. Further, in the memory that occupies most of the devices constituting the memory system, the data transfer speed of the command and address signal may be the same as the conventional one, and this has the effect that the cost does not increase.

FIG. 1 is a diagram showing a configuration of a memory bus system according to the first embodiment.
FIG. 2 is a side view (a) and a circuit diagram (b) when there is no empty slot in the memory bus system according to the first embodiment.
FIG. 3 is a side view (a) and a circuit diagram (b) when there is an empty slot in the first embodiment.
FIG. 4 is a diagram showing the configuration of the memory bus system according to the second embodiment.
FIG. 5 is a side view (a) and a circuit diagram (b) when there is no empty slot in the second embodiment.
FIG. 6 is a side view (a) and a circuit diagram (b) when there is an empty slot in the second embodiment.
FIG. 7 is a diagram showing the configuration of the memory bus system according to the third embodiment.
FIG. 8 is a side view (a) and a circuit diagram (b) when there is no empty slot in the third embodiment.
FIG. 9 is a side view (a) and a circuit diagram (b) when there is an empty slot in the third embodiment.
FIG. 10 is a diagram showing the configuration of the memory bus system according to the fourth embodiment.
FIG. 11 is a side view (a) and a circuit diagram (b) when there is no empty slot in the fourth embodiment.
FIG. 12 is a side view (a) and a circuit diagram (b) when there is an empty slot in the fourth embodiment.
FIG. 13 is a side view (a) and a circuit diagram (b) when there is no empty slot in the fifth embodiment.
FIG. 14 is a side view (a) and a circuit diagram (b) when there is an empty slot in the fifth embodiment.
FIG. 15 is a side view (a) and a circuit diagram (b) when there is no empty slot in the sixth embodiment.
FIG. 16 is a side view (a) and a circuit diagram (b) when there is an empty slot in the sixth embodiment.
FIG. 17 is a diagram showing the configuration of the memory bus system according to the seventh embodiment.
FIG. 18 is a diagram illustrating signal multiplexing and demultiplexing.
FIG. 19 is a circuit diagram of signal 2: 1 multiplexing and 1: 2 demultiplexing.
FIG. 20 is a diagram showing the configuration of the memory bus system according to the eighth embodiment.
FIG. 21 is a diagram showing the configuration of the memory bus system according to the ninth embodiment.
FIG. 22 is a circuit diagram of signal 4: 1 multiplexing and 1: 4 demultiplexing.
FIG. 23 is a diagram showing the configuration of the memory bus system according to the ninth embodiment.
FIG. 24 is a diagram showing a memory bus system in the first conventional example.
FIG. 25 shows a memory bus system in the second conventional example.
FIG. 26 shows a memory bus system in the third conventional example.
FIG. 27 is a diagram illustrating a signal transmitted through the directional coupler.
FIG. 28 shows an RTZ signal receiver.

A first embodiment will be described with reference to the block diagram of FIG. Note that FIG. 1 shows components and wirings constituting the memory bus. The board 100 is a board on which components constituting the memory system are mounted, and the MC 1 having a memory control mechanism is mounted on the board 100. Reference numeral 20 denotes a module on which a plurality of memories 10 are mounted. The memory is, for example, a DRAM. The module 20 has terminals such as a power supply and a ground and signal terminals for data signals, commands and address signals, and clock signals. FIG. 1 shows one bus wiring, four modules 20 and one register 2 and four memories 10 on each module. Further, the number of bus wirings, the number of modules 20, the number of registers and memories mounted on each module 20, and the like are not limited thereto. The plurality of memories 10 may be mounted on the front and back of the module 20. This is the same including the following embodiments.
40 is a data bus as a main transmission line extending from MC1, and is separated from the data bus 41 as a sub-transmission line extending from the memory 10 via a directional coupler 70 surrounded by a round dotted line, and is separated in a direct current manner. It is connected to the. 1 in FIG. 1 is one of the directional couplers formed on the board 100, and this directional coupling line is composed of two lines having a finite parallel length, that is, a main coupling line and a sub-coupling line. The board 100 is equipped with a directional coupler that performs the same function for data signals to other memories, but these are not shown for simplicity. The far end of the data bus 40 of the main transmission line is terminated with matching by a terminating resistor (not shown). The data bus 41 serving as a sub-transmission line is connected to the data signal terminal of each module 20 via a connector 50, and the other end is matched and terminated with a resistor (not shown). Reference numeral 30 denotes a command and address bus. The command and address bus 30 is connected from the MC 1 to each module 20 by a one-stroke wiring without branching, and is disposed at the farthest end of the transmission line as viewed from the MC 1 and connected to an appropriate termination voltage Vtt. Matched termination with no resistance.
Although not shown in FIG. 1 as in the conventional example, the clock signal is wired from MC 1 to each module 20. Conventionally, in the registered DIMM, the clock signal is distributed from MC 1 to a device called PLL (not shown) on each module 20, and via that device to a device called register 2 on the module 20 and each memory 10. The clock is distributed. In this case, since the clock signal is a special signal, it may be transmitted by the same method as the command and address bus 30 for each module 20, or may be transmitted by a completely different method. In this embodiment, 2 is referred to as a register (similarly in the following embodiments), but when 30 includes a clock signal, the register 2 has a function equivalent to the above-described PLL.
In this embodiment (similarly in the following embodiments), the transfer method of the command, address signal, and clock signal on the module from the register 2 or PLL to each memory 10 is not limited. If there is no problem in operation, a conventional transfer system as shown by the module 20 in FIG. 24 may be used, or a transfer system in which a single-stroke wiring without branching and its termination are matched and terminated may be used. . Further, if possible, a transfer method in which the data is transmitted from the register 2 or PLL to each memory 10 on a one-to-one basis may be used. That is, in the present invention, the transfer method from the register or PLL to each memory is not limited. This is the same including the following embodiments.
The data bus 40 transfer method corresponds to the aforementioned XTL, and the command and address bus 30 transfer method corresponds to the aforementioned SLT. In this case, the data transfer rate is not limited by SSTL for the command and address bus, and the data transfer rate is not limited by SLT for the data bus. However, the number of terminals of the module or connector is increased by about 20% from the number of terminals of the first conventional example. In other words, the number of terminals of modules and connectors is currently about 1/4 of the command and address signals and terminals such as power supply and ground that also serve as their electrical shields. Since each of these signals must be introduced and derived in the module by changing to SLT, twice as many terminals are required for command and address buses. However, when viewed as a whole, the total number of terminals only increases by about 20%, and this increase is hardly a problem.
Next, in the memory bus system according to the first embodiment, the case where there is no empty slot in the memory module 20 and the case where there is an empty slot will be described with reference to FIGS. 2 and 3, (a) and (b) are a side view and a circuit diagram relating to the command and address bus corresponding to FIG.
FIG. 2 shows a case where there is no empty slot, and FIG. 3 shows a case where there is an empty slot. Elements having the same functions as those in FIG. 1 are denoted by the same reference numerals. In FIG. 2B and FIG. 3B, the module 20 and the connector 50 are indicated by dotted lines in order to improve visibility. The wiring connection is the same as that shown in FIG. 1, but the description will focus on the points not explicitly shown in FIG.
The command and address bus 30 is drawn from MC1 and is terminated with a resistor 61 at the farthest end. MC1 and each register 2 are connected by a signal wiring 30 without branching. In FIG. 3B, the command and address signals between the second and fourth slots, in which devices such as the register 2 and the memory are not mounted, are connected to the empty third slot by a plurality of wirings without branching. A dummy memory module 21 is inserted into the memory card.
As described above, in the first embodiment, a special dummy memory module is required when there is an empty slot, but in the register, the input / output signal can be a conventional NRZ signal. Therefore, it is not necessary to provide an interface exclusively for XTL that handles the RTZ signal, and a conventional register can be used as it is, so that a memory system capable of high-speed data transfer can be constructed at a lower cost. .
A second embodiment will be described with reference to the configuration diagram of FIG. The difference from the first embodiment is that the command and address bus 30 transfer method is XTL in the second embodiment.
The command and address bus 30 serving as the main transmission line and the command and address bus 31 serving as the sub-transmission line are separated in a direct current and connected in an alternating manner via the directional coupler 70. Command and address bus signals are transferred from the MC 1 to each register 2 on the module 20 via the directional coupler 70. The board 100 is equipped with a directional coupler that operates in the same way for commands and address signals to other registers and data signals to other memories, but these are shown in the figure for simplicity. It has not been.
Similarly to the first embodiment, a PLL (not shown) dedicated to the clock signal may be provided on the module 20, but the devices such as the register 2 and the PLL in the second embodiment are input. The XRT RTZ signal is detected and the NRZ signal is restored, and the restored signal is transmitted to each memory. For example, the receiver is realized by the receiver 4 ′ shown in FIG.
The data bus 40 transfer method corresponds to XTL, and the command and address bus 30 transfer method also corresponds to XTL. For this reason, in the second embodiment, the command and address bus are not limited by the data transfer speed of the SLT, so that the data transfer can be performed faster than in the first embodiment. Also, the number of terminals of the module or connector can be made the same as in the first conventional example.
Next, in this embodiment, a case where there is an empty slot will be described with reference to FIGS. 5 and 6 which are a side view (a) and a circuit diagram (b) relating to the command and address bus corresponding to FIG. FIG. 5 shows a case where there is no empty slot, and FIG. 6 shows a case where there is an empty slot.
The command and address bus 30 serving as the main transmission line is drawn from MC1 and terminated with a resistor 61 at the farthest end. Command and address signals are transferred between the MC 1 and each register 2 via the directional coupler 70 and the connector 50. The command and address bus 31 as a sub-transmission line is all matched and terminated with a resistor 62 on the front side of MC1. Here, the front refers to the direction in which the signal flows through the main transmission line. In the vacant third slot of FIG. 6B, the command and address bus as the sub-transmission line has an open end at the connector 50 on the opposite side of the termination resistor 62. However, even if the slot is not vacant, the input portion of the register 2 is not terminated, so it is effectively an open end, and the state does not change. Similarly, since the data bus is an XTL transfer method, even if there is a vacant slot, other slots are not affected.
As described above, in the second embodiment, no special control or parts are required even when there is an empty slot. In addition, as described above, the memory system capable of increasing the data transfer speed of the memory system is cheaper than the first embodiment because the number of terminals of the modules and connectors can be made the same as in the first conventional example. Can be built. Furthermore, in this memory system, the main transmission line on the board and the sub-transmission line on the module are separated from each other by a directional coupler, so that modules can be removed and replaced during system operation. A so-called hot-swap operation that can be performed is possible.
A third embodiment will be described with reference to the block diagram of FIG. In the third embodiment, the command and address bus 30 signals use a one-to-one transfer (Point to Point, hereinafter referred to as P2P) system. 30 is connected from the MC 1 to the first register 2 on the module 20 by a plurality of one-to-one wirings, and the registers 2 are similarly connected by a plurality of one-to-one wirings.
The data bus 40 transfer method corresponds to XTL, while the command and address bus 30 transfer method is P2P as described above. P2P is a transfer method capable of maximizing the data transfer speed among the SSTL, SLT, and XTL described above. This is because signal attenuation occurs even in the XTL method, but signal attenuation hardly occurs in the P2P method. That is, in XTL, a signal transmitted from a main coupling line to a sub-coupling line by a directional coupler means that a signal propagating on the main transmission line loses energy in terms of energy conservation. As a result, the signal attenuates little by little as it passes through a plurality of directional couplers, whereas in P2P, inevitable factors due to the skin resistance of the transmission wiring in high frequency signals and the dielectric loss due to the dielectric constituting the board are excluded. Almost no signal attenuation occurs.
For this reason, in the third embodiment, the data transfer rate of the command and address bus 30 can be increased in principle than the data transfer rate of the data bus 40. However, since the data transfer rate as a memory system is ultimately limited by the data transfer rate of the data bus 40 adopting the XTL transfer method, the same data transfer rate as the memory system in the second embodiment is used. Can only be up to speed. By the way, the number of terminals of the module and the connector is increased by about 20% from the number of terminals of the first conventional example for the same reason as in the first embodiment, but this increase is almost a problem. do not become.
Next, in this embodiment, the case where there is an empty slot will be described with reference to FIGS. 8 and 9 which are a side view (a) and a circuit diagram (b) regarding the command and address bus corresponding to FIG. FIG. 8 shows a case where there is no empty slot, and FIG. 9 shows a case where there is an empty slot.
The command and address bus 30 is drawn from MC1 and connected to the first register 2 at P2P. At this time, the command and address bus 30 is terminated by a resistor 61 in the vicinity of the receiver 4 of the register 2 or in the register. The first register 2 has not only a function of transferring a command and an address signal to a memory as a conventional register but also a function of receiving a signal output from the MC and buffering it to the second register 2. Yes. For the sake of simplicity, the driver from the register to each memory is not shown in the figure. Similarly, the registers subsequent to the second register receive not only the function of transferring the command and address signals to the memory as a conventional register but also the signal output from the previous register and buffer it to the subsequent register. Has the ability to ring.
When there is an empty slot as shown in FIG. 9B, the module on which the memory is mounted needs to be inserted in order from the closest to MC1. In addition, in the register cascaded from the MC to the farthest end, the above-described function of buffering to the subsequent register is controlled so as not to be activated.
As described above, in the third embodiment, when there is an empty slot, the module on which the memory is mounted needs to be inserted in order from the MC1, but the memory is the same as in the second embodiment. It is possible to construct a memory system that can speed up data transfer of the system.
A fourth embodiment will be described with reference to the configuration diagram of FIG. In the fourth embodiment, as in the third embodiment, the command and address bus 30 adopts the P2P method, but the point that the register is mounted on the board 100 instead of the module 20 is different. .
The data bus 40 transfer method corresponds to XTL, while the command and address bus 30 transfer method is P2P as in the third embodiment. Therefore, also in the fourth embodiment, the data transfer speed of the command and address bus 30 can be increased in principle than the data transfer speed of the data bus 40. However, for the same reason as in the third conventional example, it is possible to increase the speed only to the same data transfer speed as that of the memory system in the second embodiment. By the way, in the fourth embodiment, unlike the third embodiment, since the command and address signals need only be introduced in the module and do not need to be derived, the number of terminals in the module and the connector is the same as that in the first embodiment. The number of terminals in the conventional example can be the same.
Next, in this embodiment, a case where there is an empty slot will be described with reference to FIGS. 11 and 12 which are a side view (a) and a circuit diagram (b) relating to the command and address bus corresponding to FIG. FIG. 11 shows a case where there is no empty slot, and FIG. 12 shows a case where there is an empty slot.
The command and address bus 30 is drawn from MC1 and connected to the first register 2 at P2P. At this time, the command and address bus 30 is terminated by a resistor 61 in the vicinity of the receiver 4 of the register 2 or in the register. The first register 2 has not only a function of transferring a command and an address signal to a memory as a conventional register but also a function of receiving a signal output from the MC and buffering it to the second register 2. Yes. Similarly, the registers subsequent to the second register receive not only the function of transferring the command and address signals to the memory as a conventional register but also the signal output from the previous register and buffer it to the subsequent register. Has the ability to ring. When there is an empty slot as shown in FIG. 12 (b), unlike the third embodiment, the module on which the memory is mounted does not need to be inserted in the order from MC1. This is because the registers are connected to P2P on the board 100, not via modules. However, in the register cascaded from the MC to the farthest end, control is performed so that the above-described function of buffering to the subsequent register is not activated. In addition, the register for the empty slot is controlled so that the function of transferring the command and address signal to the memory as a conventional register is not activated.
As described above, in the fourth embodiment, even when there is an empty slot, no special parts are required, and the number of terminals of the module or connector can be made the same as in the first conventional example. Thus, a memory system capable of increasing the data transfer speed of the memory system to the same extent as in the second embodiment can be constructed at low cost.
The fifth embodiment is the same as the first embodiment in that XTL is used for the data bus and SLT is used for the command and address bus, but the command and address bus termination methods are different.
In the fifth embodiment, a case where there is an empty slot will be described with reference to FIGS. 13 and 14 which are a side view (a) and a circuit diagram (b) regarding the command and address bus corresponding to FIG. FIG. 13 shows a case where there is no empty slot, and FIG. 14 shows a case where there is an empty slot.
The command and address bus 30 is drawn from the MC 1 and is terminated in the termination dedicated module 22. At this time, the termination resistor 61 may be mounted in the vicinity of the register 2 on the termination dedicated module 22 or may be mounted at the end of the bus wiring as indicated by the termination dedicated module 22. The wiring of the command and address bus 30 in the termination dedicated module 22 may be the same as that of the normal module 20, but in this case, some wirings are redundant depending on the mounting position of the termination resistor. Does not result in a consistent termination. For this reason, the command and address bus wiring in the termination dedicated module, as shown by the termination dedicated module 22, should be removed from the redundant wiring section connected to the termination resistor. It is advantageous in terms of quality. In the fifth embodiment, since the termination dedicated module 22 is provided, when there is an empty slot, a dummy module as in the first embodiment is not required, but a normal module is not required. The modules are inserted in order from the closest to MC1, and the termination dedicated module 22 needs to be inserted into the slot next to the last slot.
As described above, in the fifth embodiment, the special dummy memory module as in the first embodiment is not required, so that a memory system capable of increasing the data transfer speed as compared with the first embodiment is provided. It can be constructed at a lower cost than the conventional example.
The sixth embodiment is the same as the first embodiment in that XTL is used for the data signal and SLT is used for the command and address signals, but the command and address signal termination methods are different.
In the sixth embodiment, the case where there is an empty slot will be described with reference to FIGS. 15 and 16 which are a side view (a) and a circuit diagram (b) relating to the command and address bus corresponding to FIG. FIG. 15 shows a case where there is no empty slot, and FIG. 16 shows a case where there is an empty slot.
The command and address bus 30 is drawn from MC1 and is terminated with matching by an active resistance element 63 mounted in the register 2 on the last module 20 connected to MC1. The active resistance element 63 is controlled so that only the one inside the resistor 2 farthest from the MC1 is activated and the active resistance elements inside the other registers are not activated. Note that the active resistance elements in the registers that are not activated are shown by dotted lines in FIGS. 15B and 16B. In the sixth embodiment, when there is an empty slot, it is necessary to insert normal modules in order from the MC 1 instead of using the dummy modules as in the first embodiment. is there. Further, in this embodiment, in the last module connected to MC1, a part of wiring beyond the register 2 becomes redundant, so that it is not an ideal matching termination. Therefore, it is possible to further improve the signal quality by providing a termination dedicated module from which the redundant wiring portion is removed.
As described above, in the sixth embodiment, not only the special dummy memory module as in the first embodiment is unnecessary, but also the active resistance element 63 is provided in the register 2. As a result, the termination dedicated module as in the fifth embodiment is not required, so that a memory system capable of high-speed data transfer can be constructed at a lower cost than in the fifth embodiment.
The seventh embodiment will be described with reference to the block diagram of FIG. The seventh embodiment is the same as the first embodiment in that XTL is used for the data bus and SLT is used for the command and address bus, but the command and address bus data transfer speed between the MC and the register is the same. The difference is that it has been doubled. In the conventional DDR memory system, the data transfer rate of the command and address bus is ½ of the transfer rate of the data bus. However, this data transfer rate only needs to be established in the memory. There is no problem even if the data transfer speed of the command and address bus is higher than the conventional one. At this time, as shown in FIG. 18 (a), MC1 has a function of multiplexing (MUX) the command and address signal 30 twice as compared with the conventional one, and the register 2 on each module is shown in FIG. 18 (b). As shown, the multiplexed command and address signal are demultiplexed (DEMUX) to transfer a conventional data transfer rate command and address signal to each memory. In this embodiment, as shown in FIG. 17, the number of wires of the command and address bus 30 is at least ½, that is, the total number of terminals of the module and the connector is compared with the first embodiment as compared with the first embodiment. It is possible to make the number almost the same as the conventional example.
The multiplexing (MUX) and demultiplexing (DEMUX) functions can be realized by using a 2: 1 multiplexer 7 or a 1: 2 demultiplexer 8 as shown in FIG. Further, since the number of output units corresponding to the reduced number of command and address bus lines is not required in the MC, the number of MC balls and the chip area are reduced, so that the manufacturing cost of the MC can be reduced. . Further, at this time, in the memory that occupies most of the devices constituting the memory system, the data transfer speed of the command and address signal may be the same as before, so that there is an effect that the cost does not increase due to this.
As described above, in the seventh embodiment, a memory system capable of increasing the data transfer speed of the memory system to the same extent as in the first embodiment can be constructed at a lower cost.
The eighth embodiment will be described with reference to the block diagram of FIG. The eighth embodiment is the same as the second embodiment in that XTL is used for the data bus and XTL is used for the command and address bus, but the data transfer rate of the command and address bus is 2 The difference is that it has been doubled. That is, the data bus, the command, and the address bus are both set to the same data transfer speed, but since both are the same transfer method, in principle, the signal quality can be made comparable. At this time, the MC 1 has a function of multiplexing the command and address signal 30 twice as much as the conventional one, and the register 2 on each module demultiplexes the multiplexed command and address signal to obtain the conventional data. It has a function of transferring a transfer speed command and an address signal to each memory. The multiplexing and demultiplexing functions can be realized by using a 2: 1 multiplexer 7 or a 1: 2 demultiplexer 8 as shown in FIG. 19, for example. The circuit shown in FIG. 28 for receiving the RTZ signal transferred by XTL and restoring it to the original NRZ signal is also necessary. In this embodiment, as shown in FIG. 20, compared with the second embodiment, the number of wires of the command and address bus 30 is at least 1/2, that is, the total number of terminals of the module and the connector is set to the first conventional example. It is possible to reduce more than the example. Similarly to the seventh embodiment, since the number of output units corresponding to the reduced number of command and address bus lines is not required in the MC, the number of MC balls and the chip area are reduced. The manufacturing cost can be reduced. Further, at this time, in the memory that occupies most of the devices constituting the memory system, the data transfer rate of the command and address signal may be the same as the conventional one, so that there is an effect that the cost increase due to this does not occur.
As described above, in the eighth embodiment, a memory system capable of increasing the data transfer speed of the memory system to the same extent as in the second embodiment can be constructed at a lower cost.
The ninth embodiment will be described with reference to the block diagram of FIG. The ninth embodiment is the same as the third embodiment in that XTL is used for the data bus and P2P is used for the command and address bus. However, the data transfer rate of the command and address bus is twice that of the prior art. The difference is that it is quadrupled. The transfer method called P2P is capable of high-speed transfer compared to XLT, and even when P2P has a data transfer rate four times that of the conventional one, it can ensure signal quality equivalent to XLT that has a data transfer rate twice that of the conventional one. there is a possibility. At this time, the MC 1 has a function of multiplexing the command and address signal 30 twice or four times the conventional one, and the register 2 on each module demultiplexes the multiplexed command and address signal, It has a function of transferring a conventional data transfer speed command and address signal to each memory. The multiplexing and demultiplexing functions are performed by, for example, the 2: 1 multiplexer 7 and the 1: 2 demultiplexer 8 as shown in FIG. 19 described above and the 4: 4 as shown in FIG. This can be realized by using one multiplexer (a) or 1: 4 demultiplexer (b). In this embodiment, as shown in FIG. 21, compared to the third embodiment, the number of wires for the command and address bus 30 can be reduced to ½ or ¼ at a minimum. That is, the total number of terminals of the module and the connector can be made to be approximately equal to or less than that of the first embodiment. Similarly to the eighth embodiment, since the number of output units corresponding to the reduced number of command and address bus lines is not required in the MC, the number of MC balls and the chip area are reduced. The manufacturing cost can be reduced. Further, at this time, in the memory that occupies most of the devices constituting the memory system, the data transfer speed of the command and address signal may be the same as before, so that there is an effect that the cost does not increase due to this.
As described above, in the ninth embodiment, a memory system capable of increasing the data transfer speed of the memory system to the same extent as in the second embodiment can be constructed at a lower cost.
The tenth embodiment will be described with reference to the block diagram of FIG. The tenth embodiment is the same as the fourth embodiment in that XTL is used for the data bus and P2P is used for the command and address bus, but the data transfer rate of the command and address signals is twice that of the conventional example. Or the point which is made 4 times is different. The difference from the ninth embodiment is that the mounting location of the register 2 is the module 20 and the board 100, respectively.
In this embodiment, as shown in FIG. 23, as in the ninth embodiment, the number of wirings of the command and address bus 30 can be reduced to 1/2 or 1/4 at the minimum. Since the number of output units corresponding to the number of command and address bus lines is not required in the MC, the number of MC balls and the chip area are reduced, so that the manufacturing cost of the MC can be reduced. Further, at this time, in the memory that occupies most of the devices constituting the memory system, the data transfer speed of the command and address signal may be the same as before, so that there is an effect that the cost does not increase due to this. On the other hand, the total number of terminals of the module and the connector is the same as that of the first conventional example with respect to the total number of terminals since the command and address bus transfer speed between the register 2 and the memory 10 is the same as the conventional one.
As described above, in the tenth embodiment, a memory system capable of increasing the data transfer speed of the memory system to the same extent as in the second embodiment can be constructed at a lower cost.
In the above embodiment, the case where the directional coupler is configured as a transfer line in the board has been described, but an example in which some or all of the directional couplers are mounted in the form of components can be easily performed. It can be applied.
In the above embodiment, the case where the directional coupler is mounted on the board has been described. However, the present invention can be easily applied to an example in which some or all of the directional couplers are mounted on the module. Further, other embodiments than those shown in the above embodiments can be easily applied to embodiments in which the command and address bus transfer rates are doubled or quadrupled compared to the conventional ones.
Furthermore, for the preferred embodiment with reference to FIG. 18 described above, more generally, for the first data transfer rate in the data signal, the memory controller multiplexes the command and address signals and transfers them to the register. The second data transfer rate in the command and address signal is the same as or n times the first data transfer rate, demultiplexed in the register, and the first command and address signal transferred from the register to the plurality of memories is transferred. It is also possible to set the data transfer rate of 3 to 1 / n of the first data transfer rate. This can be easily configured by using an n: 1 multiplexer and a 1: n demultiplexer in the examples shown in FIGS. Here, n is an integer.
Since the data transfer rate of the buses that control the data transfer rate of the conventional memory system can be increased, a memory system that can increase the data transfer rate compared to the prior art can be realized. In addition, the data transfer speed of the command and address bus between the MC and the register is doubled or quadrupled compared to the conventional one, and the number of wirings is reduced, so that the data transfer speed can be increased compared with the conventional one and the cost is low. Memory system can be obtained.

  The memory system according to the present invention can be applied to a memory system capable of increasing the data transfer speed of the entire system in order to increase the data transfer speed of the command and address bus.

Claims (42)

In a board equipped with a memory module equipped with a plurality of memories and a memory controller for controlling a plurality of the memory modules,
Data signal transfer between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated in a direct current and connected in an alternating manner through a directional coupler. The command and address signals are transferred between the memory controller and the memory module by the first method or the second method connected in a direct current and alternating current manner. A board for transferring to the memory, wherein the directional coupler and the register are mounted on the memory module or the board. In a board equipped with a memory module equipped with a plurality of memories and a memory controller for controlling a plurality of the memory modules,
Data signal transfer between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated in a direct current and connected in an alternating manner through a directional coupler. The command and address signals are transferred between the memory controller and the memory module by the first method or the second method connected in a direct current and alternating current manner. A register for transferring to the memory, wherein the directional coupler is mounted on the board, and the register is mounted on the memory module, and includes an interface for the data signal with the directional coupler. A memory bus system characterized by that. In a memory module mounted on a board having a memory controller,
Data signal transfer between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated in a direct current and connected in an alternating manner through a directional coupler. The command and address signals are transferred between the memory controller and the memory module by the first method or the second method connected in a direct current and alternating current manner. A memory module comprising: a register for transferring to the memory, wherein the directional coupler and the register are mounted on the memory module. In a board equipped with a memory module equipped with a plurality of memories and a memory controller for controlling a plurality of the memory modules,
Data signal transfer between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated in a direct current and connected in an alternating manner through a directional coupler. The command and address signals are transferred between the memory controller and the memory module by the first method or the second method connected in a direct current and alternating current manner. A register for transferring to the memory, the directional coupler and the register being mounted on the board, an interface for the data signal with the directional coupler, and the command and address signal with the register And a memory bus system. The memory module of claim 2,
The memory module is characterized in that the command and address signals are transferred between the memory controller and the register by the second method connected by a plurality of one-stroke wiring without branching. The memory module of claim 3.
The memory module is characterized in that the command and address signals are transferred between the memory controller and the register by the second method connected by a plurality of one-stroke wiring without branching. The memory module of claim 2,
Transferring commands and address signals between the memory controller and the register is performed by the first method. The memory module of claim 3.
Transferring commands and address signals between the memory controller and the register is performed by the first method. The memory module of claim 2,
The command and address signals are transferred between the memory controller and the register in a one-to-one connection between the memory controller and the first register by a plurality of unbranched wirings. Similarly, the memory module is performed by the second method in which the registers are connected one-to-one by a plurality of wirings without branching. The memory module of claim 3.
The command and address signals are transferred between the memory controller and the register in a one-to-one connection between the memory controller and the first register by a plurality of unbranched wirings. Similarly, the memory module is performed by the second method in which the registers are connected one-to-one by a plurality of wirings without branching. The memory module of claim 4.
The command and address signals are transferred between the memory controller and the register in a one-to-one connection between the memory controller and the first register by a plurality of unbranched wirings. Similarly, the memory module is performed by the second method in which the registers are connected one-to-one by a plurality of wirings without branching. The memory module of claim 5.
Plural for maintaining an electrical connection between the memory controller and a termination resistor of the command and address signals to be inserted when there is an empty slot into which the memory module in which a plurality of memories are mounted is not inserted A dummy memory module characterized in that the command and address wirings are internally provided and no device such as the memory is mounted. The memory module of claim 6.
Inserting between the memory controller and a termination resistor of the command and address signal, and termination of the memory controller and the data signal, when there is an empty slot into which the memory module in which a plurality of memories are mounted is not inserted A dummy memory module having a plurality of command and address wirings and data wirings for maintaining an electrical connection between resistors therein, wherein no device such as the memory is mounted. The memory module of claim 5.
When there is an empty slot, a plurality of the memory modules are inserted so as not to be empty in order from the slot close to the memory controller, and inserted into the slot next to the last slot inserted in such a manner. A termination-only memory module, comprising: a plurality of resistors for matching termination of a plurality of commands and address lines written in a single stroke without a branch connecting between the memory controller and the plurality of registers. The memory module of claim 6.
When there is an empty slot, a plurality of the memory modules are inserted so as not to be empty in order from the slot close to the memory controller, and inserted into the slot next to the last slot inserted in such a manner. A plurality of single-stroke commands and address lines for connecting and matching between the memory controller and the plurality of registers; a plurality of resistors for matching termination; and the data wiring as a main transmission line in the first method. And a termination dedicated memory module, comprising: a resistor for matching termination. The memory module of claim 5.
When there are vacant slots, a plurality of the memory modules are inserted in order from the slots close to the memory controller so that there is no vacancy, and a termination resistor is mounted as an active element inside each of the registers on the memory module. The memory module is characterized in that only the active element at the farthest end from the memory controller is activated and the command and address signals are matched and terminated. The memory module of claim 6.
When there are vacant slots, a plurality of the memory modules are inserted in order from the slots close to the memory controller so that there is no vacancy, and a termination resistor is mounted as an active element inside each of the registers on the memory module. Only the active element at the farthest end from the memory controller is activated, the command and address signals are matched and terminated, and a termination resistor for matching termination of the main transmission line of the data signal in the first method is provided. An end-only memory module comprising: The termination-only memory module according to claim 14, 15 or 17,
A termination-only memory module characterized by having no redundant wiring portion after the termination resistor as viewed from the memory controller. The memory module of claim 8,
A termination-only memory module comprising resistors for matching termination of the plurality of main transmission lines for the command and address signals and the plurality of main transmission lines for the data signals. The register according to claim 16 or 17,
A register having a termination resistor mounted therein as an active element, wherein only the active element farthest from the memory controller is activated and the command and address signals are matched and terminated. In each register according to claim 9, 10 or 11,
A plurality of the command and address signals connected in a one-to-one manner with a resistance element mounted inside or near the outside of the register at the signal receiving end are matched and terminated. A second function that has a first function of transferring data to another register connected to the first register, and that does not activate the first function in the register cascaded to the farthest end from the memory controller; And when the register is mounted on the board and there is an empty slot, the function of stopping the transfer function of the command and address signal to the empty slot is provided. register. The memory controller for controlling the memory module according to claim 16 or 17,
A memory controller having a function of controlling the register so that only the active element in the register at the farthest end from the memory controller is activated and the command and address signals are matched and terminated. A memory controller for controlling the memory module according to claim 9, 10 or 11,
23. The second register according to claim 21, wherein the second register is activated for the register cascaded to the farthest end from the memory controller, and the register is mounted on the board and an empty slot is provided. A memory controller having a control function for stopping the transfer function of the command and address signal to the empty slot when present. In a memory bus system having a memory module on which a plurality of memories are mounted and a board on which a memory controller for controlling the memory module is mounted,
Data signal transfer between the memory controller and the memory module is performed by a first method in which a main transmission line and a sub-transmission line are separated in a direct current and connected in an alternating manner through a directional coupler. The command and address signals are transferred between the memory controller and the memory module by the first method or the second method connected in a direct current and alternating current manner. The command transferred to the register by multiplexing the command and the address signal by the memory controller for the first data transfer speed in the data signal. And the second data transfer rate in the address signal is increased to the same or twice the first data transfer rate. The third data transfer rate of the command and address signals transferred from the register to the plurality of memories by demultiplexing in the register is set to ½ of the first data transfer rate. Memory bus system. The memory module according to any one of claims 2 to 19,
With respect to the first data transfer rate in the data signal, the memory controller multiplexes the command and address signal, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer speed of the command and address signals transferred from the register to the plurality of memories is demultiplexed in the register, and the third data transfer speed is the same as or twice the data transfer speed of the first data. A memory module comprising the register having a function of reducing a transfer rate to ½. The command and address signal are multiplexed by the memory controller with respect to the first data transfer speed in the data signal, and the second data transfer speed in the command and address signal transferred to the register is defined as the first data transfer speed. The third data transfer rate of the command and address signal transferred from the register to a plurality of memories by demultiplexing at the same or twice the same speed and demultiplexing in the register is set to ½ of the first data transfer rate A register having a function. 21. The register according to claim 20, wherein a command and an address signal are multiplexed by a memory controller with respect to a first data transfer rate in the data signal, and a second data transfer rate in the command and address signal transferred to the register. Is increased to the same or twice the first data transfer rate, demultiplexed in the register, and the third data transfer rate of the command and address signals transferred from the register to the plurality of memories is changed to the first data transfer rate. A register having a function of reducing the data transfer rate to ½. In claim 7 or 8,
The command and address signal are multiplexed by the memory controller with respect to the first data transfer speed in the data signal, and the second data transfer speed in the command and address signal transferred to the register is defined as the first data transfer speed. The third data transfer rate of the command and address signal transferred from the register to a plurality of memories by demultiplexing at the same or twice the same speed and demultiplexing in the register is set to ½ of the first data transfer rate A register in a memory board having a function. The register of claim 21,
With respect to the first data transfer rate in the data signal, the command and address signal are multiplexed by the memory controller, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of the command and address signal transferred from the register to the plurality of memories is demultiplexed in the register to be the same as or twice the data transfer rate, and the first data transfer A register that has the function of half the speed. With respect to the first data transfer rate in the data signal, the command and address signal are multiplexed by the memory controller, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of the command and address signal transferred from the register to the plurality of memories is demultiplexed in the register to be the same as or twice the data transfer rate, and the first data transfer A memory controller having a function to reduce the speed to 1/2. The memory controller of claim 22,
With respect to the first data transfer rate in the data signal, the command and address signal are multiplexed by the memory controller, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of the command and address signal transferred from the register to the plurality of memories is demultiplexed in the register to be the same as or twice the data transfer rate, and the first data transfer A memory controller having a function to reduce the speed to 1/2. In claim 7 or 8,
With respect to the first data transfer rate in the data signal, the command and address signal are multiplexed by the memory controller, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of the command and address signal transferred from the register to the plurality of memories is demultiplexed in the register to be the same as or twice the data transfer rate, and the first data transfer A memory controller in a memory board on which the register having a function of halving the speed is mounted. The memory controller of claim 23,
With respect to the first data transfer rate in the data signal, the command and address signal are multiplexed by the memory controller, and the second data transfer rate in the command and address signal transferred to the register is set to the first data transfer rate. The third data transfer rate of the command and address signal transferred from the register to the plurality of memories is demultiplexed in the register to be the same as or twice the data transfer rate, and the first data transfer A memory controller having a function of halving the speed. In a memory bus system having a memory module mounted with a plurality of memories and a memory controller connected to the memory of the memory module via a bus, and transferring data signals and commands or addresses via the bus,
A first bus connection path that is DC and DC separated by a main transmission line and a subtransmission line via a directional coupler to transfer a data signal between the memory controller and the memory module; ,
A second connection path connected in a direct and alternating manner to transfer a command or address signal between the memory controller and the memory module;
A memory bus system comprising a register for transferring a command or address signal transferred via the second connection path to the plurality of memories. 35. The memory bus system of claim 34.
A memory bus system comprising a board to which a plurality of the memory modules are connected via a connector, wherein the directional coupler and the register are mounted on the board. 35. The memory bus system according to claim 34, further comprising a board to which a plurality of the memory modules are connected via connectors, wherein the directional coupler and the register are mounted on the memory module. 35. The memory bus system of claim 34.
A memory bus system comprising a board to which a plurality of the memory modules are connected via a connector, the directional coupler being mounted on the board, and the register being mounted on the memory module. A memory module having a plurality of memories, which can be connected to a memory controller by a bus and transfers data signals and commands or address signals between the memory controllers via the bus.
A first bus connection path that is separated in a DC manner and connected in an alternating manner by a main transmission line and a sub-transmission line via a directional coupler to transfer a data signal to and from the memory controller;
A second connection path connected in a direct and alternating manner to transfer a command or address signal to and from the memory controller;
A memory module, comprising: a register for transferring a command or address signal transferred through the second connection path to the plurality of memories. A board connected to a memory module equipped with a plurality of memories via a connector, a bus connected to the memory of the memory module, a data signal transferred to the memory module via the bus, and a command Alternatively, in a memory module connection board having a memory controller that emits an address, a main transmission line and a sub-transmission line are connected via a directional coupler to transfer a data signal between the memory controller and the memory module. A first bus connection path which is separated in a direct current and connected in an alternating manner;
A second connection path connected in a direct and alternating manner to transfer a command or address signal between the memory controller and the memory module;
A board for connecting a memory module, comprising a register for transferring a command or address signal transferred through the second connection path to the plurality of memories. A board connected to a memory module having a plurality of memories and a register for temporarily storing commands and address signals to be transferred to the memory via a connector, and connected to the memory of the memory module And a memory module connection board having a memory controller that issues a data signal and a command or an address transferred to the memory module via the bus,
A first bus connection path that is DC and DC separated by a main transmission line and a subtransmission line via a directional coupler to transfer a data signal between the memory controller and the memory module; ,
A second connection path connected in a direct and alternating manner to transfer a command or address signal between the memory controller and the memory module;
A board for connecting memory modules. In any one of claims 34 to 40,
The second connection path is constituted by a plurality of lines drawn in one stroke without branching. In a memory system having a memory module having a plurality of memories and a memory controller connected to the memory of the memory module via a bus, and transferring a data signal and a command or an address via the bus,
A first bus connection path that is DC and DC separated by a main transmission line and a subtransmission line via a directional coupler to transfer a data signal between the memory controller and the memory module; ,
A second connection path connected in a direct and alternating manner to transfer a command or address signal between the memory controller and the memory module;
A register for transferring a command or address signal transferred via the second connection path to the plurality of memories;
And, for the first data transfer rate in the data signal, the command and address signal transferred to the register is multiplexed (MUX) by the memory controller, and the second in the command and address signal transferred to the register. By making the data transfer rate the same as or n times the first data transfer rate and demultiplexing (DEMUX) in the register, the command and address signals transferred from the register to the plurality of memories 3. A memory system characterized in that the data transfer rate of No. 3 is 1 / n of the first data transfer rate.

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