JPS6482248A - Priority level deciding circuit - Google Patents

Priority level deciding circuit

Info

Publication number
JPS6482248A
JPS6482248A JP62238994A JP23899487A JPS6482248A JP S6482248 A JPS6482248 A JP S6482248A JP 62238994 A JP62238994 A JP 62238994A JP 23899487 A JP23899487 A JP 23899487A JP S6482248 A JPS6482248 A JP S6482248A
Authority
JP
Japan
Prior art keywords
output
priority level
encoder
subtractor
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62238994A
Other languages
Japanese (ja)
Inventor
Kenichi Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62238994A priority Critical patent/JPS6482248A/en
Publication of JPS6482248A publication Critical patent/JPS6482248A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To dynamically change the priority level to improve the efficiency of priority level decision by giving a position, which is obtained by subtracting an arbitrary number from the preceding most preferential position, as the following most preferential position. CONSTITUTION:The n-bit shift output of a right loop shift register 10 having the n-bit width which receives n-number of requests from the external is inputted to a first encoder 20 and is encoded. The output of the encoder 20 is decoded by a decoder 30, and the n-bit output of the decoder 30 is inputted to a left loop shift register 40. The output of the register 40 is inputted to a subtractor 60 through a second encoder 50, and (m) (m<n) is subtracted from the output of the encoder 50 by the subtractor 60. That is, the output of the register 40 is outputted as a priority level deciding output signal of n-number of requests, and the output result of the subtractor 60 is given as an extent of shift of registers 10 and 40, and the position obtained by subtracting an arbitrary number from the preceding most preferential position is given as the following most preferential position. Thus, the priority level is dynamically changed.
JP62238994A 1987-09-25 1987-09-25 Priority level deciding circuit Pending JPS6482248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62238994A JPS6482248A (en) 1987-09-25 1987-09-25 Priority level deciding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62238994A JPS6482248A (en) 1987-09-25 1987-09-25 Priority level deciding circuit

Publications (1)

Publication Number Publication Date
JPS6482248A true JPS6482248A (en) 1989-03-28

Family

ID=17038332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62238994A Pending JPS6482248A (en) 1987-09-25 1987-09-25 Priority level deciding circuit

Country Status (1)

Country Link
JP (1) JPS6482248A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277620A (en) * 2005-03-30 2006-10-12 Canon Inc Controller arbitrating bus access and its method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006277620A (en) * 2005-03-30 2006-10-12 Canon Inc Controller arbitrating bus access and its method

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