JPS6479794A - Memory address controller - Google Patents

Memory address controller

Info

Publication number
JPS6479794A
JPS6479794A JP62236765A JP23676587A JPS6479794A JP S6479794 A JPS6479794 A JP S6479794A JP 62236765 A JP62236765 A JP 62236765A JP 23676587 A JP23676587 A JP 23676587A JP S6479794 A JPS6479794 A JP S6479794A
Authority
JP
Japan
Prior art keywords
data
address
control
display mode
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62236765A
Other languages
Japanese (ja)
Other versions
JP2609629B2 (en
Inventor
Noriya Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62236765A priority Critical patent/JP2609629B2/en
Publication of JPS6479794A publication Critical patent/JPS6479794A/en
Application granted granted Critical
Publication of JP2609629B2 publication Critical patent/JP2609629B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)
  • Image Processing (AREA)
  • Digital Computer Display Output (AREA)
  • Color Television Systems (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE: To attain address control by hardware, to speed up address calculation and to reduce the load of a CPU by providing the memory address controller with two address data generation means for successively specifying respective addresses of a picture memory. CONSTITUTION: The controller executes the address control of a normal display mode, a PIP display mode, an enlarged display mode, and a multi-picture display mode based upon data set up in latch circuits 18, 20, 26, 28 and control data CD1 to CD4 outputted from a control circuit 29. The controller for executing the address control is provided with counters 12, 14 for generating the horizontal address data of the picture memory 11, counters 13, 15 for generating the vertical address data of the memory 11, data subtracting circuits 17, 19, count value selecting circuits 21, 22, shift circuits 23, 24 for changing the inclinations of selected outputs, and data adders 25, 27 and respective control functions can be driven only by setting up data from a CPU 16.
JP62236765A 1987-09-21 1987-09-21 Memory address controller Expired - Lifetime JP2609629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62236765A JP2609629B2 (en) 1987-09-21 1987-09-21 Memory address controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62236765A JP2609629B2 (en) 1987-09-21 1987-09-21 Memory address controller

Publications (2)

Publication Number Publication Date
JPS6479794A true JPS6479794A (en) 1989-03-24
JP2609629B2 JP2609629B2 (en) 1997-05-14

Family

ID=17005460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62236765A Expired - Lifetime JP2609629B2 (en) 1987-09-21 1987-09-21 Memory address controller

Country Status (1)

Country Link
JP (1) JP2609629B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225909A (en) * 2013-06-21 2013-10-31 Mega Chips Corp Image processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013225909A (en) * 2013-06-21 2013-10-31 Mega Chips Corp Image processing system

Also Published As

Publication number Publication date
JP2609629B2 (en) 1997-05-14

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