JPS6478592A - Color picture display circuit - Google Patents

Color picture display circuit

Info

Publication number
JPS6478592A
JPS6478592A JP23645187A JP23645187A JPS6478592A JP S6478592 A JPS6478592 A JP S6478592A JP 23645187 A JP23645187 A JP 23645187A JP 23645187 A JP23645187 A JP 23645187A JP S6478592 A JPS6478592 A JP S6478592A
Authority
JP
Japan
Prior art keywords
color
signal
voltage
color signal
clamped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23645187A
Other languages
Japanese (ja)
Inventor
Takahiro Sagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23645187A priority Critical patent/JPS6478592A/en
Publication of JPS6478592A publication Critical patent/JPS6478592A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To correct a point different in a brightness characteristic according to a color to an impressed voltage and to reproduce a correct hue by individually setting the pedestal level of an R color signal, G and B color signals. CONSTITUTION:A video signal is separated to three primary colors and inputted to an A/D converter 12 through a capacitor as the R color signal 15, the G color signal 16 and a chrominance signal 17. A clamp signal 18 goes to 1 in the timing of a back porch after passing through a capacitor to turn on the switching transistor of a pedestal clamp circuit 11. Accordingly, the black level of an R' color signal 19 is clamped to 0 voltage, and the black level of a G' color signal 20 and B' color signal 21 is clamped to a voltage V1. Since the G', B' color signals 20, 21 are raised higher by the voltage V1 than the R' color signal 19, the difference voltage V1 of a leading voltage is corrected to substantially equalize the brightness characteristics of the R, G, B color signals.
JP23645187A 1987-09-21 1987-09-21 Color picture display circuit Pending JPS6478592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23645187A JPS6478592A (en) 1987-09-21 1987-09-21 Color picture display circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23645187A JPS6478592A (en) 1987-09-21 1987-09-21 Color picture display circuit

Publications (1)

Publication Number Publication Date
JPS6478592A true JPS6478592A (en) 1989-03-24

Family

ID=17000942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23645187A Pending JPS6478592A (en) 1987-09-21 1987-09-21 Color picture display circuit

Country Status (1)

Country Link
JP (1) JPS6478592A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657619B1 (en) 1999-06-25 2003-12-02 Nec Lcd Technologies, Ltd. Clamping circuit for liquid crystal display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657619B1 (en) 1999-06-25 2003-12-02 Nec Lcd Technologies, Ltd. Clamping circuit for liquid crystal display device

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