JPS6473447A - System for controlling low order device - Google Patents

System for controlling low order device

Info

Publication number
JPS6473447A
JPS6473447A JP22976287A JP22976287A JPS6473447A JP S6473447 A JPS6473447 A JP S6473447A JP 22976287 A JP22976287 A JP 22976287A JP 22976287 A JP22976287 A JP 22976287A JP S6473447 A JPS6473447 A JP S6473447A
Authority
JP
Japan
Prior art keywords
low
order
central processor
order central
interrupting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22976287A
Other languages
Japanese (ja)
Inventor
Shinji Ineshima
Masahisa Kageyama
Yasushi Oi
Shinichi Yokomizo
Junko Takeshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22976287A priority Critical patent/JPS6473447A/en
Publication of JPS6473447A publication Critical patent/JPS6473447A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To speed up an interrupting processing without imposing a big burden on a low-order central processor by providing a signal line for transmitting an interrupting signal from a low-order device to the low-order central processor to a bus adapter part between the low-order device and the bus adapter part. CONSTITUTION:The signal line 7 for transmitting the interrupting signal transmitted from the low-order device 6 to the low-order central processor 5 to the bus adapter part 3 between the low-order device 6 and the bus adapter part 3. Consequently, the interrupting signal from the low-order device 6 is appropriately processed by the command of the high-order central processor 1 and the like according to whether the high-order central processor 1 or the low-order central processor 5 has instructed of starting even if the low-order central processor 5 does not judge the device which has instructed of starting. Thus, the interrupting processing can be executed without imposing the big burden on the low-order central processor 5.
JP22976287A 1987-09-16 1987-09-16 System for controlling low order device Pending JPS6473447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22976287A JPS6473447A (en) 1987-09-16 1987-09-16 System for controlling low order device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22976287A JPS6473447A (en) 1987-09-16 1987-09-16 System for controlling low order device

Publications (1)

Publication Number Publication Date
JPS6473447A true JPS6473447A (en) 1989-03-17

Family

ID=16897276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22976287A Pending JPS6473447A (en) 1987-09-16 1987-09-16 System for controlling low order device

Country Status (1)

Country Link
JP (1) JPS6473447A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112005A (en) * 1990-03-28 1992-05-12 Aisin Seiki Kabushiki Kaisha Seat belt retractor
JP2011213079A (en) * 2010-04-02 2011-10-27 Roland Dg Corp Computer program for manufacturing products by using a plurality of devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112005A (en) * 1990-03-28 1992-05-12 Aisin Seiki Kabushiki Kaisha Seat belt retractor
JP2011213079A (en) * 2010-04-02 2011-10-27 Roland Dg Corp Computer program for manufacturing products by using a plurality of devices

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