JPS6464431A - Input and output signal supervising circuit - Google Patents

Abstract

PURPOSE:To reduce jitter to be added to a memory circuit and to decrease the number of bits necessary for a memory by reading the data of the memory circuit with a clock to suppress the jitter in an input signal. CONSTITUTION:A jitter suppressing circuit 2 suppresses the jitter in an input signal 1 and outputs a data clock to a variable length shift register 3. On the other hand, an input signal receives conversion in a composing circuit 6 and after that, it is written to a memory circuit 5. These written data are successively read with the clock to suppress the jitter and outputted to a bit error detecting circuit 4. The data written to the register 3 receives the delay of an arbitrary time and it is outputted so that the delay time of the data to be inputted from the register 3 to the detecting circuit 4 by the control of the detecting circuit 4 and the delay time of the data to be inputted from the memory circuit 5 can be equal. The detecting circuit 4 compares the two data with bit-by-bit and an error is detected.