JPS6451739A - Sub signal processing circuit - Google Patents

Sub signal processing circuit

Info

Publication number
JPS6451739A
JPS6451739A JP62209088A JP20908887A JPS6451739A JP S6451739 A JPS6451739 A JP S6451739A JP 62209088 A JP62209088 A JP 62209088A JP 20908887 A JP20908887 A JP 20908887A JP S6451739 A JPS6451739 A JP S6451739A
Authority
JP
Japan
Prior art keywords
circuit
clock
signal
output
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209088A
Other languages
Japanese (ja)
Inventor
Shigeru Taguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62209088A priority Critical patent/JPS6451739A/en
Publication of JPS6451739A publication Critical patent/JPS6451739A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To reduce the number of components by switching an output of a clock extraction circuit in other direction to supply the signal to a multiplex conversion circuit if no clock is detected from the output of a unidirectional clock extraction circuit at a fault thereby transferring the sub signal to a low order. CONSTITUTION:A sub signal including a monitor control signal and an ordering signal is given to on input terminal 21, separated by a multiplex inversion circuit 1 and inputted to a monitor control signal processing circuit 10 and an ordering line interface 3. Moreover, the monitor control signal and the ordering signal from the processing circuit 10 and the interface 3 are multiplexed again by a multiplex conversion circuit 4 and outputted from an output terminal 22. The clock operating conversion circuits 1, 4 is extracted by a clock extraction circuit 2. When no clock is extracted at abnormity, a changeover circuit 5 switches the clock of the opposite clock extraction circuit 12 and supplies an output.
JP62209088A 1987-08-21 1987-08-21 Sub signal processing circuit Pending JPS6451739A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209088A JPS6451739A (en) 1987-08-21 1987-08-21 Sub signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209088A JPS6451739A (en) 1987-08-21 1987-08-21 Sub signal processing circuit

Publications (1)

Publication Number Publication Date
JPS6451739A true JPS6451739A (en) 1989-02-28

Family

ID=16567077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209088A Pending JPS6451739A (en) 1987-08-21 1987-08-21 Sub signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6451739A (en)

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