JPS6448512A - Sample rate converter - Google Patents

Sample rate converter

Info

Publication number
JPS6448512A
JPS6448512A JP20547287A JP20547287A JPS6448512A JP S6448512 A JPS6448512 A JP S6448512A JP 20547287 A JP20547287 A JP 20547287A JP 20547287 A JP20547287 A JP 20547287A JP S6448512 A JPS6448512 A JP S6448512A
Authority
JP
Japan
Prior art keywords
switch
systems
sample
outputs
sampling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20547287A
Other languages
Japanese (ja)
Inventor
Isao Otsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20547287A priority Critical patent/JPS6448512A/en
Publication of JPS6448512A publication Critical patent/JPS6448512A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the circuit scale small in size by providing two sampling systems comprising plural data latch groups and a switch, latching a digital signal in the two sampling systems by two sampling phases and selecting a proper output by a switch among the outputs and giving the result. CONSTITUTION:A 1st clock generator 17 having three outputs with a proper delay of series of data latch group, a 2nd clock generator 18 having a single phase clock and a signal switch 19 are provided to form two sample systems having a different sample phase. The control signal to switch properly the output of the two sample systems is formed to switch the outputs of the two sample systems properly thereby converting the sample rate. Thus, a buffer memory, a write address counter and a readout address counter or the like having been required for various device configuration are not needed and the circuit scale is reduced.
JP20547287A 1987-08-18 1987-08-18 Sample rate converter Pending JPS6448512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20547287A JPS6448512A (en) 1987-08-18 1987-08-18 Sample rate converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20547287A JPS6448512A (en) 1987-08-18 1987-08-18 Sample rate converter

Publications (1)

Publication Number Publication Date
JPS6448512A true JPS6448512A (en) 1989-02-23

Family

ID=16507425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20547287A Pending JPS6448512A (en) 1987-08-18 1987-08-18 Sample rate converter

Country Status (1)

Country Link
JP (1) JPS6448512A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01311787A (en) * 1988-06-10 1989-12-15 Sony Corp Rate converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01311787A (en) * 1988-06-10 1989-12-15 Sony Corp Rate converter

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