JPS6445692A - Ic module and manufacture therof - Google Patents

Ic module and manufacture therof

Info

Publication number
JPS6445692A
JPS6445692A JP62203728A JP20372887A JPS6445692A JP S6445692 A JPS6445692 A JP S6445692A JP 62203728 A JP62203728 A JP 62203728A JP 20372887 A JP20372887 A JP 20372887A JP S6445692 A JPS6445692 A JP S6445692A
Authority
JP
Japan
Prior art keywords
module substrate
frame component
chip
opening
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62203728A
Other languages
Japanese (ja)
Inventor
Yutaka Okuaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP62203728A priority Critical patent/JPS6445692A/en
Publication of JPS6445692A publication Critical patent/JPS6445692A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

PURPOSE: To devise shape thinning and cost reduction of IC module by providing a frame component at an opening formed on a module substrate to make it a single plate, and by fixing the module substrate and an IC chip by soldering the frame. CONSTITUTION: Interior of an opening 22 formed on an insulating module substrate 21 having wiring part 20 has an integrated frame component 23 made of thermoplastic resin and fixed to the module substrate 21 at outer sides 23-1 adhered to a lateral side of the opening 22. Namely, contained in the opening surrounded by inner sides 23-2 of frame component 23 is IC chip 24, its lateral sides are fixed to the frame component 23 with soldered part 23-3 formed by heating to inner sides 23-2 of the frame component 23, and the module substrate 21, frame component 23 and IC chip 24 have formed a plane nearly even. And wiring part 20 on the module substrate 21 and electrode part 25 formed on the IC chip 24 have electrically been connected with metal thin wires 26. Accordingly, thickness of IC modules can be made thinner than those of the conventional ones.
JP62203728A 1987-08-17 1987-08-17 Ic module and manufacture therof Pending JPS6445692A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62203728A JPS6445692A (en) 1987-08-17 1987-08-17 Ic module and manufacture therof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62203728A JPS6445692A (en) 1987-08-17 1987-08-17 Ic module and manufacture therof

Publications (1)

Publication Number Publication Date
JPS6445692A true JPS6445692A (en) 1989-02-20

Family

ID=16478868

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62203728A Pending JPS6445692A (en) 1987-08-17 1987-08-17 Ic module and manufacture therof

Country Status (1)

Country Link
JP (1) JPS6445692A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10193848A (en) * 1996-12-27 1998-07-28 Rohm Co Ltd Circuit chip-mounted card and circuit chip module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10193848A (en) * 1996-12-27 1998-07-28 Rohm Co Ltd Circuit chip-mounted card and circuit chip module

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