JPS6437625A - Branch instruction control system - Google Patents
Branch instruction control systemInfo
- Publication number
- JPS6437625A JPS6437625A JP19485287A JP19485287A JPS6437625A JP S6437625 A JPS6437625 A JP S6437625A JP 19485287 A JP19485287 A JP 19485287A JP 19485287 A JP19485287 A JP 19485287A JP S6437625 A JPS6437625 A JP S6437625A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- succeeding
- memory
- stored
- cancel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Advance Control (AREA)
Abstract
PURPOSE:To continue processing without refetching a succeeding instruction stored in an instruction buffer by suppressing the cancel of the succeeding instruction only by one cycle when a test instruction and a branch instruction are continuously generated. CONSTITUTION:A leading microinstruction for executing a machine word instruction is read out from a rapid memory without fail and the succeeding instruction is stored in a medium speed memory 7. An address stored in an address register 10 is converted to obtain an address for the memory 7. When the rapid memory 6 is accessed, data can be found out in the succeeding cycle, but in case of the medium speed memory 7, two cycles are required. When a test instruction and a branch instruction are continuously generated and branching operation is failed, a control device 2 suppresses a cancel signal to be sent to a pipeline canceling circuit 9 by a cancel suppressing signal and executes processing by forecasting that the succeeding instruction is stored in the medium speed memory 7.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19485287A JPH0740226B2 (en) | 1987-08-04 | 1987-08-04 | Branch instruction control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19485287A JPH0740226B2 (en) | 1987-08-04 | 1987-08-04 | Branch instruction control method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6437625A true JPS6437625A (en) | 1989-02-08 |
JPH0740226B2 JPH0740226B2 (en) | 1995-05-01 |
Family
ID=16331353
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19485287A Expired - Fee Related JPH0740226B2 (en) | 1987-08-04 | 1987-08-04 | Branch instruction control method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0740226B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015036855A (en) * | 2013-08-12 | 2015-02-23 | 富士通株式会社 | Arithmetic processing device and arithmetic processing device control method |
-
1987
- 1987-08-04 JP JP19485287A patent/JPH0740226B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015036855A (en) * | 2013-08-12 | 2015-02-23 | 富士通株式会社 | Arithmetic processing device and arithmetic processing device control method |
Also Published As
Publication number | Publication date |
---|---|
JPH0740226B2 (en) | 1995-05-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |