JPS6435636A - Evaluating system for test program for information processor - Google Patents

Evaluating system for test program for information processor

Info

Publication number
JPS6435636A
JPS6435636A JP62190510A JP19051087A JPS6435636A JP S6435636 A JPS6435636 A JP S6435636A JP 62190510 A JP62190510 A JP 62190510A JP 19051087 A JP19051087 A JP 19051087A JP S6435636 A JPS6435636 A JP S6435636A
Authority
JP
Japan
Prior art keywords
test
simulator
instruction
executed
test program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62190510A
Other languages
Japanese (ja)
Inventor
Kitsuya Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62190510A priority Critical patent/JPS6435636A/en
Publication of JPS6435636A publication Critical patent/JPS6435636A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To easily evaluate a processing when an abnormality of a test program is detected, by discriminating a test object instruction contained in the test program, and changing the test object instruction by an SW simulator, as if it is a different instruction. CONSTITUTION:When a test program 1 is executed by a usual execution mode on an SW simulator 2, the usual execution contents 3i of a test (i) advance to the next test, when the SW simulator executes an operation as expected, and advance to the next test, after having executed an error processing if the simulator does not execute the operation as expected. By executing the program 1 by an abnormality evaluation execution mode on the simulator 2, and by executing a TEST - START instruction in the abnormality evaluation execution contents 4 of the test (i), the simulator 2 executes it as an instruction of R1=R2+R3 to be executed subsequently. In such a way, when the simulator 2 executes the operation as expected, the contents of the register R1 remain '0', therefore, the error processing is always executed.
JP62190510A 1987-07-31 1987-07-31 Evaluating system for test program for information processor Pending JPS6435636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62190510A JPS6435636A (en) 1987-07-31 1987-07-31 Evaluating system for test program for information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190510A JPS6435636A (en) 1987-07-31 1987-07-31 Evaluating system for test program for information processor

Publications (1)

Publication Number Publication Date
JPS6435636A true JPS6435636A (en) 1989-02-06

Family

ID=16259290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190510A Pending JPS6435636A (en) 1987-07-31 1987-07-31 Evaluating system for test program for information processor

Country Status (1)

Country Link
JP (1) JPS6435636A (en)

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