JPS6428856A - Multilayered integrated circuit - Google Patents

Multilayered integrated circuit

Info

Publication number
JPS6428856A
JPS6428856A JP62182307A JP18230787A JPS6428856A JP S6428856 A JPS6428856 A JP S6428856A JP 62182307 A JP62182307 A JP 62182307A JP 18230787 A JP18230787 A JP 18230787A JP S6428856 A JPS6428856 A JP S6428856A
Authority
JP
Japan
Prior art keywords
chip
integrated circuit
layer
large scale
side layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62182307A
Other languages
Japanese (ja)
Inventor
Ryosuke Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62182307A priority Critical patent/JPS6428856A/en
Publication of JPS6428856A publication Critical patent/JPS6428856A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To form a large scale integrated circuit with high reliability, by stacking, on an LSI chip of lower side layer, an LSI chip whose area is smaller than that of the LSI chip of lower side layer, and connecting, through wires, the LSI chip of the upper side layer and that of the lower side layer. CONSTITUTION:A multilayer integrated circuit is formed, by stacking at least two or more layers of large scale integrated circuit chips 10-12. The area of the chip 11 of upper layer stacked on the chip 10 of lower layer is larger than the area of the chip 12 of upper layer stacked on the chip 11 of lower layer. The signal transmission and reception between the chip 10 and the chip 11 and between the chip 11 and the chip 12 is performed via a wire 15a. Thereby, a large scale integrated circuit with high reliability can be obtained.
JP62182307A 1987-07-23 1987-07-23 Multilayered integrated circuit Pending JPS6428856A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62182307A JPS6428856A (en) 1987-07-23 1987-07-23 Multilayered integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62182307A JPS6428856A (en) 1987-07-23 1987-07-23 Multilayered integrated circuit

Publications (1)

Publication Number Publication Date
JPS6428856A true JPS6428856A (en) 1989-01-31

Family

ID=16116003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62182307A Pending JPS6428856A (en) 1987-07-23 1987-07-23 Multilayered integrated circuit

Country Status (1)

Country Link
JP (1) JPS6428856A (en)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
US5381047A (en) * 1992-05-27 1995-01-10 Kanno; Kazumasa Semiconductor integrated circuit having multiple silicon chips
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5600183A (en) * 1994-11-15 1997-02-04 Hughes Electronics Multi-layer film adhesive for electrically isolating and grounding an integrated circuit chip to a printed circuit substrate
US5801448A (en) * 1996-05-20 1998-09-01 Micron Technology, Inc. Conductive lines on the back side of wafers and dice for semiconductor interconnects
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5923091A (en) * 1997-02-21 1999-07-13 Mitsubishi Denki Kabushiki Kaisha Bonded semiconductor integrated circuit device
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6476500B2 (en) * 2000-07-25 2002-11-05 Nec Corporation Semiconductor device
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
US5381047A (en) * 1992-05-27 1995-01-10 Kanno; Kazumasa Semiconductor integrated circuit having multiple silicon chips
US5291061A (en) * 1993-04-06 1994-03-01 Micron Semiconductor, Inc. Multi-chip stacked devices
USRE40061E1 (en) 1993-04-06 2008-02-12 Micron Technology, Inc. Multi-chip stacked devices
US5600183A (en) * 1994-11-15 1997-02-04 Hughes Electronics Multi-layer film adhesive for electrically isolating and grounding an integrated circuit chip to a printed circuit substrate
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US6165815A (en) * 1996-02-20 2000-12-26 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US6337227B1 (en) 1996-02-20 2002-01-08 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5917242A (en) * 1996-05-20 1999-06-29 Micron Technology, Inc. Combination of semiconductor interconnect
US5817530A (en) * 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5801448A (en) * 1996-05-20 1998-09-01 Micron Technology, Inc. Conductive lines on the back side of wafers and dice for semiconductor interconnects
US6989285B2 (en) 1996-05-20 2006-01-24 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
US5923091A (en) * 1997-02-21 1999-07-13 Mitsubishi Denki Kabushiki Kaisha Bonded semiconductor integrated circuit device
US6261865B1 (en) 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6673650B2 (en) 1998-10-06 2004-01-06 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6458625B2 (en) 1998-10-06 2002-10-01 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6762078B2 (en) 1999-05-20 2004-07-13 Amkor Technology, Inc. Semiconductor package having semiconductor chip within central aperture of substrate
US6798049B1 (en) 1999-08-24 2004-09-28 Amkor Technology Inc. Semiconductor package and method for fabricating the same
US6642610B2 (en) 1999-12-20 2003-11-04 Amkor Technology, Inc. Wire bonding method and semiconductor package manufactured using the same
US6803254B2 (en) 1999-12-20 2004-10-12 Amkor Technology, Inc. Wire bonding method for a semiconductor package
US6476500B2 (en) * 2000-07-25 2002-11-05 Nec Corporation Semiconductor device
US6552416B1 (en) 2000-09-08 2003-04-22 Amkor Technology, Inc. Multiple die lead frame package with enhanced die-to-die interconnect routing using internal lead trace wiring
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6946323B1 (en) 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US6919631B1 (en) 2001-12-07 2005-07-19 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US6737750B1 (en) 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
US7154171B1 (en) 2002-02-22 2006-12-26 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
US6879047B1 (en) 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor

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