JPS6412339A - Forth machine - Google Patents

Forth machine

Info

Publication number
JPS6412339A
JPS6412339A JP16691187A JP16691187A JPS6412339A JP S6412339 A JPS6412339 A JP S6412339A JP 16691187 A JP16691187 A JP 16691187A JP 16691187 A JP16691187 A JP 16691187A JP S6412339 A JPS6412339 A JP S6412339A
Authority
JP
Japan
Prior art keywords
host computer
word
microinstruction
forth
machine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16691187A
Other languages
Japanese (ja)
Inventor
Nobuhito Matsushiro
Ikuo Oya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP16691187A priority Critical patent/JPS6412339A/en
Publication of JPS6412339A publication Critical patent/JPS6412339A/en
Pending legal-status Critical Current

Links

Landscapes

  • Devices For Executing Special Programs (AREA)

Abstract

PURPOSE:To realize the execution of a word and a link processing between the words and to eliminate link overhead between the words, by providing an interpretive pointer stack and a microinstruction mask. CONSTITUTION:A FORTH machine 2 is backend machine for a host computer 1, and it is constituted so that the dictionary of a FORTH word can be formed in a WCS12 and it can be made access from the host computer 1. The address of the word to be executed is supplied from the host computer 1, and an execution result is delivered to the host computer 1. A microinstruction read out from the WCS12 to a microinstruction register 13 by a sequencer 11 supplies a control signal to every part passing a decoder 14. The interpretive pointer stack 16 is used for the designation of a word address.
JP16691187A 1987-07-06 1987-07-06 Forth machine Pending JPS6412339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16691187A JPS6412339A (en) 1987-07-06 1987-07-06 Forth machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16691187A JPS6412339A (en) 1987-07-06 1987-07-06 Forth machine

Publications (1)

Publication Number Publication Date
JPS6412339A true JPS6412339A (en) 1989-01-17

Family

ID=15839927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16691187A Pending JPS6412339A (en) 1987-07-06 1987-07-06 Forth machine

Country Status (1)

Country Link
JP (1) JPS6412339A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009527815A (en) * 2006-02-16 2009-07-30 ブイエヌエス ポートフォリオ リミテッド ライアビリティ カンパニー Computer system with increased operating efficiency
US7913069B2 (en) 2006-02-16 2011-03-22 Vns Portfolio Llc Processor and method for executing a program loop within an instruction word

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217438A (en) * 1984-03-02 1985-10-31 テキサス　インスツルメンツ　インコ−ポレイテツド Data processing apparatus and method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217438A (en) * 1984-03-02 1985-10-31 テキサス　インスツルメンツ　インコ−ポレイテツド Data processing apparatus and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009527815A (en) * 2006-02-16 2009-07-30 ブイエヌエス ポートフォリオ リミテッド ライアビリティ カンパニー Computer system with increased operating efficiency
US7913069B2 (en) 2006-02-16 2011-03-22 Vns Portfolio Llc Processor and method for executing a program loop within an instruction word

Similar Documents

Publication Publication Date Title
JPS6436336A (en) Calculator system
DE3687724D1 (en) DIGITAL PROCESSOR CONTROL.
DE3072001D1 (en) Diagnostic circuitry in a data processor
JPS55123736A (en) Interrupt control system
JPS6412339A (en) Forth machine
DE69033122D1 (en) Arrangement and method for translating virtual addresses of misaligned double words
JPS6488861A (en) Data processor
JPS6446134A (en) Data processor
JPS6472237A (en) Address calculation system
JPS57113109A (en) Numeric control system
ES8403639A1 (en) Extended control word decoding device.
JPS5657111A (en) Sequence controller
JPS6478360A (en) Information processor
JPS51118335A (en) Partly writing system
Robinson et al. A small versatile parallel-structured processor
JPS6455602A (en) Instruction processing circuit for programmable controller
JPS5654510A (en) Data transferring method of sequencer
JPS57191758A (en) System for storing test program in main storage
TW327213B (en) A multiprocessor computer apparatus
JPS57100700A (en) Data flow computer
JPS573156A (en) Central processing device
JPS6459552A (en) Ipl retry processing system
JPS5764848A (en) Processor of pipeline control data
JPS5667453A (en) Information processor with data generation part
JPS54122039A (en) Electronic computer