JPS6396940A - Macro logic array - Google Patents

Abstract

PURPOSE:To obtain a macro logic array of high integration density by a method wherein a refractory-metal wiring part is used after it has been formed inside an insulating film under an active layer so that various logic circuits can be realized by changing only the level of metal wiring parts at a first layer and a second layer. CONSTITUTION:FET unit arrays 28, 27 and a basic cell array 29 for a gate array are arranged on an SOI substrate. A basic cell group 1 contains 1 pieces of CMOS gate array cells. A gate 6 and a source drain 4 for an n FET and a gate 7 and a source drain 5 for a p FET are contained; a rectangular pattern 50 composed of a refractory metal is buried in an insulating film. A basic cell group 2 for a NOR array to be used for CMOS programmable logic- arrays contains m pieces of FET's and is composed of an n FET array, where a source electrode 8 and a gate electrode 11 are used in common, and a p FET array, where a gate electrode 12 is used in common. Because the channel width of the cell group 2 is narrower than that of the cell group 1, and the group 2 contains the similar refractory-metal buried layer 50, it is possible to form a connecting hole independently. In addition, there is a cell group 3 which has n pieces of n FET arrays and p FET arrays whose channel width, arrangement and connection are the same as those of the group 2. With this arrangement, it is possible to obtain various logic arrays of high integration-density by changing only the level of wiring parts.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mask slice substrate, and particularly to a CMOS type macro logic array that does not integrate a programmable logic array and a gate array.

[Conventional technology]

Conventionally, C is a combination of a programmable logic array (hereinafter abbreviated as PLA) and a gate array (hereinafter abbreviated as GA).
MOS type macro logic array (hereinafter abbreviated as MLA)
As shown in FIG. 8, the first . From a plurality of unit blocks 63 consisting of second MOS FET unit columns 78 and 77 and a column (hereinafter abbreviated as GA basic cell) 79 consisting of unit cells (hereinafter referred to as GA cells) for producing a GA with 0MO8 configuration. It has a GA block 64. The contents of the first MOS FET unit row 78 are shown in FIG. 9. FIG. 9 is a MOS FET layout diagram of the manufactured first MOS FET unit row 78, and FIG. 10 is an equivalent circuit diagram of FIG. 9. It is. In the figure, 51 is a basic cell group for GA, which includes nMOS FET
, a GA cell with 0 MO8 configuration consisting of 9 MOSFETs is e
<'e is 2 or more) is ready. 56 is nMOS
Polycrystalline silicon gate electrode 57 for FET is pM.

Polycrystalline silicon gate electrode for S FET, 54 is n
The source or drain electrode of the MOs FET, 55 is the source or drain electrode of the 9MO9FET.

52 is NO for producing PLA composed of CMO3lil
This is a basic cell group for the R array, and the cells are a column of nMOS FETs having a commonly connected source electrode 58, a commonly connected polycrystalline silicon gate electrode 61, and a column of 9MO8FETs having a commonly connected gate electrode 62. consisting of m n-channel and p-channel MOSs, respectively.
FET is ready. However, GA basic cell group 5
The channel width is narrower than that of MOS FET 1. 53 is another NOR array basic cell group, nM, which has the same channel width as the basic cell group 52, and is arranged and connected in the same way.

It consists of an S FET row and 9 MOSFET rows, each with n MOS FETs prepared.

In the first MOS FET unit column 8, one GA basic cell group 51 and one NOR array leather basic cell group 53 are arranged in a direction perpendicular to the drain current.

11 and 12 show the MOS FET arrangement diagram and its equivalent circuit diagram of a unit block 63 manufactured by arranging a plurality of these unit columns in the drain current direction. At this time, the first MOS FET unit column 78 The second MOS FET unit row 77 is moved so as to be line symmetrical with respect to the direction perpendicular to the drain current direction, and the first MOS FE
T unit rows 78 are alternately arranged in the drain current direction. Also, the source or drain electrodes of the closest MOSFETs of the same conductivity type are connected. Although the GA basic cell row 79 has the same arrangement of MOS FETs as the GA basic cell group 51, apart from the number, the GA block 64 is configured with the same consideration as the unit block 63 described above. do.

The first point mentioned above. Second MOS FET unit row 78.
A desired circuit was fabricated by applying first and second layer metal wiring to an MLA in which 77 and GA basic cell rows 79 were laid out as shown in FIG.

[Problem that the invention seeks to solve]

In the conventional MLA described above, the intended circuit is constructed by wiring between cells using the first layer and second layer metal wiring. For example, if the combinational circuit whose equivalent circuit is shown in FIG. 13 is realized using the conventional method, the layout of the wiring within the basic cell 52 will be as shown in FIG. 14. This uses the basic cell 52 for NOR array and input signals A, B.
.

Output signal f for C and D, = B + C, f2 = A + C
This is an example of creating a combinational circuit that outputs . In this example, a circuit is fabricated using only four columns of basic cell group 2.

In the figure, 85.86 is the first layer metal wiring, 87.88
is the second layer metal wiring, and 72 is pM.

S FET 75 is an nMOS FET. Further, when a PLA AND plane NOR array is fabricated using the basic cell group, 88.89 is a current power supply line, 85 is an input line, and 86.87 is a product term line.

Further, 89 is a contact hole for connecting the first layer metal wiring and the MOS FET, 90 is a through hole for connecting the first layer metal and the second layer metal, and 91 is a contact hole and a through hole formed at the same time. means a hole made by In this case, in order to maintain the mask slicability of the MLA, the first layer metal wiring must be arranged so that the contact holes and through holes to the electrodes of each MOSFET are not obstructed by the first layer metal wiring. There is a need.

Therefore, since the wiring region 92 is provided between each MOSFET, the area required for manufacturing the MLA increases.

The purpose of the present invention is to form and use high melting point metal wiring in the insulating film located under the active layer, so that various logic circuits can be formed by changing only the first and second layer metal wiring levels. The objective is to provide a high-density MLA that can be realized using

[Means for solving problems]

The macro logic array of the present invention is an SOI in which a rectangular high melting point metal layer is embedded in an insulating layer underlying an active layer.
A macro logic array formed by forming semiconductor elements on a substrate, the macro logic array being provided directly above the high melting point metal layer of the active layer, having a drain current aligned with the long side direction of the high melting point metal layer, and having a gate electrode. 1. The device size is smaller than the planar shape of the high melting point metal layer. Second conductivity type MI
The first MI in which the S FET is arranged in the drain current direction
A first basic cell group in which one S FET pair (! is an arbitrary integer) is arranged in a straight line in a direction perpendicular to the drain current direction, and a second M S FET pair having the same configuration as the first MIS FET pair.
m IS FET pairs (m is any integer) are arranged in a straight line in the direction perpendicular to the drain current direction, and the first conductivity type MIS
All the gate electrodes of the FETs are connected to each other, all the electrodes located on the opposite side of the second conductivity type MIS FET when viewed from the gate electrode are connected to each other, and further the second conductivity type M
A second basic cell group in which all the gate electrodes of IS FETs are connected to each other, and a third MIS FE having the same configuration as the second basic cell group and having n pieces (n is an arbitrary integer).
A MOS F is formed by arranging a third basic cell group consisting of T pairs in a line in a direction perpendicular to the drain current direction.
A first block having a unit block in which a plurality of ET unit rows are arranged in the drain current direction so as to be line symmetrical to each other, and further having one or more of the unit blocks sequentially arranged in a direction perpendicular to the drain current direction; , a fourth basic cell group having the same structure as the first basic cell group is connected to the MOSFE
After arranging the same number of T unit rows and second blocks arranged in the drain current direction in a direction perpendicular to the drain current direction, each electrode of these MIS FETs is finally connected to the high melting point metal layer and the A/wiring. By connecting them, a predetermined logic circuit is formed.

〔Example〕

The present invention will be explained using examples.

FIG. 1 shows a first insulator layer laid out on an SOI substrate having an active layer on an insulating layer. Second MOS FET unit row 28.27
This is a layout diagram of a GA basic cell column 29 made up of GA cells. Figure 2 shows the M of the first MO8FET unit row that was fabricated.
The OS FET layout diagram, FIG. 3, is an equivalent circuit diagram of FIG. 2. In the figure, 1 is a basic cell group for GA (first basic cell group), and one GA cell (l is 2 or more) with a CMOS configuration consisting of an nMOSFET and 9 MOSFETs is prepared. 6 is a polycrystalline silicon gate electrode for nMOSFET, 7 is a polycrystalline silicon gate electrode for 9MOSFET, and 4 is nM.

S FET source or drain electrode, 5 is 9MO
This is the source or drain electrode of the SFET. Also, 5
0 is a rectangular pattern of a high melting point metal layer embedded in an insulating layer.

2 is a basic cell group (second basic cell group) for a NOR array for producing a C0M5 elliptical PLA, and the cell has a commonly connected source electrode 8 and a commonly connected polycrystalline silicon gate electrode. nMOSFET array with 11 and 9 MOSF with commonly connected gate electrode 12
It consists of a row of ETs, each with m n-channel and p-channel MOS FETs. However, the channel width is narrower than that of the MOS FET in basic cell group 1 for GA, and 50 is a rectangular pattern made of a high-melting point metal layer embedded in an insulating layer, which is independent of the MOS FET so that it can be used later as wiring. It is arranged so that a contact hole can be formed in the area. 3 is an nMOS FET array and pMOS with the same channel width and the same arrangement and connection as the other NOR array basic cell group 2 (third basic cell group).
Consists of a FET array, each with n MOS FETs
is ready.

Within the first MOS FET unit column 8, one GA basic cell group 1 and one NOR array basic cell group 2.3 are arranged in a direction perpendicular to the drain current. 4 and 5 show the MOS FET arrangement diagram and its equivalent circuit diagram of the unit block 13 manufactured by arranging a plurality of these unit columns in the direction of the drain current.
A second MOS in which the FET unit row 28 is moved so as to be line symmetrical with respect to the direction perpendicular to the drain DC direction.
FET unit unit row upper 7 1st MOS FET unit row 2
8 are arranged alternately in the drain current direction. Further, the source or drain electrodes of the closest MOSFETs of the same conductivity type are connected.

Although the GA basic cell row 29 has the same arrangement of MOS FETs as the GA basic cell group 1, apart from the number, the GA block 14 is configured with the same consideration as the unit block 13 described above. do.

The following is an example of fabricating an arbitrary circuit using the master slice substrate in which the second MOS FET unit column 7 and the GA basic cell column 29 are laid out as shown in FIG. 1. .

FIG. 7 is an equivalent circuit diagram of one embodiment of the present invention.
Using basic cell 2 for R array, input signals A, B, C, D
For output signal f1=B+D.

An example of creating a combinational circuit that outputs f2=A+C will be shown. FIG. 6 is a layout diagram showing an embodiment of the present invention. In this example, a circuit is fabricated using only four columns of basic cell group 2.

In the figure, 45, 46, 48 are the first layer metal wiring, 4
7 is the second layer metal wiring, 22 is pM.

S FET 25 is an nMOS FET. Also, using the basic unit cell 2 for NOR array, AND of PLA
When a planar NOR array is fabricated, 48 is a current power line,
45 is an input line, and 46.50 is a product term line. 41 is the first
A contact hole 39 for connecting a metal wiring layer to a MOS FET or a high melting point metal layer means a hole created by simultaneously forming a contact hole and a through hole. Similar metal wiring is performed in basic cell group 3 for NOR array, allowing any NOR circuit to be created.
In the present invention, as shown in FIG. 6, a rectangular pattern made of a high-melting point metal layer buried in an insulating film can be used as a part of the product term line, which is conventionally required as shown in FIG. The MLA can have master slicing properties without providing the wiring area 92 between the MOS FETs. Therefore, the area required to fabricate the MLA is reduced and the degree of integration of the entire circuit is increased.

In this embodiment, the gate electrodes of the nMOS FET and pMOS FET in the MOR array basic cell group 2.3 are fabricated separately, but there is no problem even if commonly connected polycrystalline silicon gate electrodes are used.

〔Effect of the invention〕

As explained above, the present invention uses an SOI substrate having an insulating layer in which a rectangular high-melting point metal layer is embedded.
Since the wiring area can be reduced, MOS FET
The gap between the holes can be reduced compared to the conventional method, and a highly integrated macro logic array can be manufactured.

[Brief explanation of the drawing]

1 to 7 are diagrams for explaining one embodiment of the present invention, in which FIG. 1 is a layout diagram of a basic cell array for GA, and FIGS. 2 and 3 are diagrams of a first MOS FET unit, respectively. row MOS
The FET layout diagram and equivalent circuit diagram, FIGS. 4 and 5 respectively show the MOS FET layout diagram and equivalent circuit diagram of a unit block, and FIGS. The figure shows the layout of the basic cell row for GA, FIGS. 9 and 10 respectively show the MOS FET layout and equivalent circuit diagram of the first MOS FET unit row, and FIGS. 11 and 12 show the MOS of the unit block, respectively. FET
A layout diagram and an equivalent circuit diagram, and FIGS. 13 and 14 are a layout diagram and an equivalent circuit diagram, respectively, showing a conventional example. 1.51...GA basic cell group, 2.3.52゜53
...Basic cell group for NOR array, 4, 5, 54.55
...Source electrode or drain electrode, 6°7.56.5
7... Gate electrode, 8, 9, 10, 58.59.60
...source electrode or drain electrode, 11.12,61
．． 62...Gate electrode, 13,63...Unit block, 14.64...GA block, 21-23.71
~73...9 MOSFET, 24~26.74~76
-nMOSFET, 27.77...second MOS
FET unit row, 28°78--first MOS FE
T unit column, 30.80...Input line to NOR array,
31.32, 81°82...product term line, 33.83...
・Power line, 34.84...GND line, 38.88...
・Power line, 39.91...Contact hole and through hole, 40.89--Contact hole, 45,4
6,85.86...1st layer metal wiring, 47.87.
...Second layer metal wiring, 48...First layer metal wiring,
50... High melting point metal layer, 90... Through hole, 9
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Claims (1)

[Claims] A macro logic array in which semiconductor elements are formed on an SOI substrate in which a rectangular high melting point metal layer is embedded in an insulating layer serving as a base of an active layer, the semiconductor element being formed directly above the high melting point metal layer of the active layer. The first and second conductivity type MISFETs are arranged in the direction of the drain current, and the drain current is made to match the long side direction of the high melting point metal layer, and the device size excluding the gate electrode is smaller than the planar shape of the high melting point metal layer. a first basic cell group in which l first MISFET pairs (l is an arbitrary integer) arranged in a straight line in a direction perpendicular to the drain current direction; and a second basic cell group having the same configuration as the first MISFET pair. m MISFET pairs (m is any integer) are arranged in a straight line in the direction perpendicular to the drain current direction, and the first conductivity type MI
All the gate electrodes of the SFETs are connected to each other, all the electrodes located on the opposite side of the second conductivity type MISFET when viewed from the gate electrode are connected to each other, and further the second conductivity type MISFET is connected to each other.
A second basic cell group in which all gate electrodes of the ETs are connected to each other, and a third MISFET pair having the same configuration as the second basic cell group and n (n is any integer) third MISFETs. It has a unit block in which a plurality of MOSFET unit rows each having a third basic cell group arranged in a line in a direction perpendicular to the drain current direction are arranged in line symmetry with each other in the drain current direction; A first block in which more than one unit block is sequentially arranged in a direction perpendicular to the drain current direction, and a fourth basic cell group having the same structure as the first basic cell group in the same number as the MOSFET unit rows. After arranging the second blocks arranged in the drain current direction in the direction perpendicular to the drain current direction, finally these M blocks are arranged in the direction perpendicular to the drain current direction.
A macro logic array characterized in that a predetermined logic circuit is formed by connecting each electrode of an ISFET to the high melting point metal layer through an Al wiring.