JPS6389951A - Cache memory device - Google Patents

Abstract

PURPOSE:To prevent the delay of accessing from being generated, by making a cache memory into a bank, estimating the mis-caching of the bank to which a CPU is accessing, and switching the bank when the mis-caching is generated. CONSTITUTION:The CPU10, when the mis-caching of a cache memory bank 12a being generated, interrupts the accessing, and outputs control signals CMa and CCb of H levels respectively to two-way buffers 13b and 14b. Also, it outputs control signals CMb and CCa of L levels respectively to two-way buffers 13b and 14a. Therefore, the data bus DBb of a memory bank 12b is separated from a main member 11, and is connected to the CPU10 through the buffer 14b. Meanwhile, the data bus DBa of the memory bank 12a is separated from the CPU10, and is connected to the main memory 11 through the buffer 13a, and the CPU10 accesses to the memory bank 12b. Similarly, by estimating the mis-caching of the bank memory 12b, it is switched to the memory bank 12a if the mis-caching is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a cache memory device for speeding up memory access in a CPU application device.

2. Description of the Related Art As shown in FIG. 3, in a conventional cache memory device, in a normal operating state, a control signal CC from the CPU 1 to the buffer 2a is at a high level, and a control signal CC from the CPU 1 to the buffer 2a is at a high level. The sofa 2bVc control signal CH is at a low level, the bidirectional buffer 2a is enabled, and the bidirectional buffer 2b is disabled.

Therefore, the cache memory 3 was followed by M.

The data bus DB is bidirectional;
The CPU
1 accesses the cache memory 3 via the bidirectional buffer 2a.

On the other hand, when a cache miss occurs, the CPUs 1 & t interrupt access to the cache memory 3 and set the zero control signal CH to the bidirectional buffer 2b at a high level.
Bidirectional)<Control signal CC' for Tufa 2a
5' OV He/l/K S;';r.

Therefore, data bus DB from cache memory 3
is separated from CPU 1 and becomes bidirectional buffer 2b.
is connected to the main memory 4 via the memory transfer control circuit 5.
exchanges necessary data in main memory 4 with unnecessary data in base cache memory 3.

When the data exchange is completed, the CPU i sets the control signal CC for the bidirectional buffer 2a at a high level and the control signal CH for the bidirectional buffer 2b at a low level, and resumes accessing the cache memory 3.

Problems to be Solved by the Invention However, in such a configuration, when a cache miss occurs, the CPU is forced to stop execution in order to exchange necessary data in the main memory 4 with unnecessary data in the cache memory 3. There is a problem in that the access has to be interrupted, resulting in access delay.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a cache memory device that does not cause access delay even if a cache miss occurs.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention divides the cache memory into banks, predicts a cache miss in the bank being accessed by the CPU, and updates the bank when a cache miss occurs. It is characterized by being able to switch between.

Operation According to the above configuration, the CPU can shift the access to another bank even if a cache miss occurs in the currently accessed bank, so that no access delay occurs.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
1 is a block diagram showing an embodiment of the cache memory device according to the present invention, and FIG. 2 is a more detailed block diagram of the cache miss prediction control circuit of FIG. 1.

16 in FIG. 1, this cache memory device has a CP
Ul0, main memory 11, cache memory banks 12a and 12b for shortening the access time for CPUl0 to main memory 11, and unnecessary data of main memory 11 and cache memory banks 13a and 13b when a cache miss occurs. bidirectional buffers 13a and 13b that temporarily store data, and the CPU 15 and cache memory bank 1 in a normal state where no cache miss occurs.
bidirectional buffers 14a and 14b that temporarily store data between the CPU 2a and 12b, and the cache memory bank 12g or 12 that is accessed by the CPUl0K.
A cache miss occurrence is predicted for b, and based on the result, unnecessary data in the other unaccessed cache memory bank 12b or 12a and the main memory 11 are predicted.
It is generally composed of a cache memory prediction control circuit 15 that exchanges necessary data within the cache memory.

As shown in FIG. 2, the cache memory prediction control circuit 15 stores a branch prediction table 15a in which the address of the latest branch instruction and the address of the branch destination when branching due to a past branch instruction is stored, and a branch prediction table 15a stored in the main memory 11. The cache address table 15b stores an address range indicating which data is stored in the cache memory banks 12a, 12b, and the data in the branch prediction table 15a and the data in the cache address table 15b are compared 6.
A comparator 15c compares and outputs a predicted branch address, and a main memory 11 according to the predicted branch address from the comparator 15c.
The memory transfer control circuit 15d transfers the data to the cache memory banks 12a and 12b.

The operation of the embodiment according to the above configuration will be described with reference to the case where the CPU 10 is accessing the cache memory bank 12a.

In this case, the CPU 10 sends the low level control signals CM a and ccb to the bidirectional buffer 13a, respectively.
and 14b, and high-level control signals CMb and CCa are used for bidirectional buffers 13b and 14a, respectively. Therefore, data bus DBa of cache memory bank 12a is separated from main memory 11 and is bidirectional. CPU10 via buffer 14a
On the other hand, data bus DBb of cache memory bank 12b is cut from CPU10 and connected to main memory IIK via bidirectional buffer 13b.

In the above operation, the branch prediction table 15a of Cache Miss Prediction Control Circuit [5] contains the latest information of the address to which a branch was executed when a branch instruction was executed in the past and the address where the branch instruction was located, as described above. recorded. Therefore, since the cache miss prediction control circuit 15 has a high probability of branching in the same direction the next time the same branch instruction is executed, the cache miss prediction control circuit 15 selects the branch destination of the branch instruction from the branch prediction table 1.
It is predicted that the branch will be taken to the branch destination recorded in 5a.

That is, the comparator 15e compares the branch instruction address of the branch prediction table 15a with the cache address table 15b.
By comparing the address ranges of , it is detected whether the branch instruction is stored in the cache memory bank 12a. If a branch instruction is stored in the cache memory bank 12a, for the branch instruction with the smallest address among them, the corresponding branch destination address is compared with the address range of the cache address table 15b.

The branch destination address is in the cache address table 15b
If it is not within the address range of comparator 1, a cache miss will occur if a branch occurs due to a branch instruction.
5e outputs the branch destination address to the memory transfer control circuit 15d.

On the other hand, if the branch destination address is within the address range of the cache address table 15b, it is predicted that a cache miss will not occur even if a branch occurs due to a branch instruction, and a similar procedure is performed for the next branch instruction with the lowest address. Make a comparison.

If it is predicted that there is no cache miss for all the branch instructions to be compared, or if the branch instructions to be compared do not exist within the address range of the cache address table 15b, the cache memory bank 12
The address next to the final address of a is output to the memory transfer control circuit 15d.

Based on the address from the comparator 15e, the memory transfer control circuit 15d outputs data from the main memory 11 to the currently unused cache memory bank 12b.

9 When a cache miss occurs to the cache memory bank 12a, the page CPU 10 interrupts access, outputs high-level control signals CMa and ccb to the bidirectional buffers 13a and 14b, and outputs low-level control signals CMb and CCa. The signals are output to bidirectional buffers 13b and 14a, respectively.

Therefore, data bus DBb of cache memory bank 12b is separated from main memory 11 and connected to CPU 10 via bidirectional buffer 14b, while data bus DBa of cache memory bank 12a is connected to CPU 10 via bidirectional buffer 14b.
It is separated from CPU 10 and connected to main memory 11 via bidirectional buffer 13a, and CPU 10 accesses cache memory bank 12b.

Similarly, a cache miss for cache memory bank 12b is predicted, and when a cache miss occurs, the cache memory bank is switched to cache memory bank 12a.

As explained above, in the above embodiment, the Schmis prediction control circuit 15 predicts the occurrence of a cache miss and switches between the cache memory banks 12a and 12b, so that the execution of the CPU10 is not interrupted. .

In the above embodiment, the case where the cache memory is divided into two banks has been described, but the cache memory may be divided into any number of banks.

Furthermore, as the predicted probability of a cache miss becomes smaller, the access delay of CPU10 due to the occurrence of a cache miss can be further reduced.
The miss prediction control circuit 15 is an example, and is not limited thereto.

As described in detail, in the present invention, the cache memory is organized into banks, and the bank is switched when a cache miss occurs in the bank being accessed by the CPU. , C
Even if a cache miss occurs in the currently accessed bank, the PU can access other banks, so no page delay occurs during access.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a cache memory device according to the present invention, FIG. 2 is a more detailed block diagram of the cache-miss prediction control circuit of FIG. 1, and FIG. 3 is a conventional example. FIG. 10. CPU, 11...Main memory, 12a, 12
b...Cache memory bank, 13a, 13b-1
4a. 14b... Bidirectional buffer, 15... Cache miss prediction control circuit, 15a... Branch prediction table, 15
b...cache address table, 15'c...
Comparator 15d...Memo IJk sending control circuit. Name of agent: Patent attorney Toshio Nakao (1st person)
figure

Claims (1)

[Claims] Cache memory banked into multiple numbers and CPU
means for predicting a cache miss for a bank that is being accessed by the CPU, and exchanging data in the main memory with data in a bank that has not been accessed by the CPU when a cache miss is predicted, and when a cache miss has occurred. A cache memory device characterized in that banks can be switched depending on the case.