JPS6386079A - Three-dimensional shadow image forming processing device - Google Patents

Abstract

PURPOSE:To attain a highly speedy three-dimensional shadow image forming processing by executing a three-dimensional vector operation and a matrix operation with 3-4 floating point arithmetic units in parallel and in a pipeline way. CONSTITUTION:Object shape data and a processing parameter used for image forming processing are stored into data memories DBM#1-#4. By floating point arithmetic units FPU#1-#3 and an arithmetic unit FAPU to combine a floating point computing element and an arithmetic and logic computing element in parallel, the three-dimensional vector operation and the matrix operation are executed in parallel and in a pipeline way. The prepared image data are written through a data collector DC to a display memory.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a processing device that generates a three-dimensional shadow image based on numerically expressed shape data of a three-dimensional object. The present invention relates to the configuration of a processor unit in a device that takes

(Prior art) In recent years, technology has been developed to create a three-dimensional shadow image of a three-dimensional object observed from an arbitrary position through numerical calculations using a computer based on shape data of a three-dimensional object expressed numerically. is attracting attention. This has come to be used as an effective means for designing and simulating products in various industries and industries, and as an effective means for creating images for TV broadcasts and movies.

However, creating a shadow image from the shape data of an object requires a huge amount of numerical calculation processing, resulting in problems such as excessive processing time and the need to use a large, high-speed computer. This type of problem is a major factor in reducing work efficiency and increasing equipment costs when designing the products and creating videos.

With the recent development of hardware technology centered on computers, three-dimensional shadow image generation devices that can perform this type of processing at high speed have been developed. In particular, devices that generate shadow images at high speed based on simple processing methods are rapidly being put into practical use and are becoming available at low prices.

For example, workstations used in the fields of CAD and CAM are capable of generating and displaying shadow images as well as inputting data.

Many conventional devices employ an image generation processing method called a depth buffer method or a canline method.

These methods require a relatively small amount of processing and can generate images at high speed, but they have drawbacks such as limited object shapes and inability to express optical phenomena such as reflection and refraction. There is.

As a more realistic and precise shadow image generation method, there is a processing method called ray tracing method. According to this method, it is possible to generate an image that does not have the drawbacks of the above methods, but it searches for the point where a virtual ray emitted from each pixel of the image to be created intersects with the object, and calculates the brightness of the pixel. The amount of calculation required is an order of magnitude larger than that of the above method.

Conventionally, dedicated devices have been researched and developed for the purpose of executing the above-mentioned ray tracing method at high speed. Broadly speaking, the configuration of this type of device can be divided into a configuration in which a large number of microprocessors are connected in parallel, and a configuration in which a LSI dedicated to floating point calculations is used to enable high-speed calculations. However, in the former device, the capacity of each processor is small, so it is necessary to use many processors to speed up processing.
There is a problem that the scale of the device increases. Also.

In the latter device, it is possible to execute calculations at high speed using a floating point calculation LSI. However, for this purpose, it is also necessary to perform processing such as setting object shape data used for calculations and determining calculation results at high speed, but it is necessary to combine the floating-point arithmetic unit with a processor that performs this type of processing. There was a problem in that it was insufficient and did not necessarily enable high-speed calculation as a whole.

(Objective of the Invention) The present invention adopts a multiprocessor configuration in which processing units are connected in parallel in order to enable high-speed processing such as ray tracing processing that can generate realistic and precise shadow images at high speed. In the dimensional image generation processing device, each processing unit has a configuration in which three floating point arithmetic units are connected in parallel, one floating point arithmetic unit and one arithmetic logic unit are connected in parallel, and each A large-capacity data memory is connected to each computing unit, and data is transferred from the memory to each computing unit at high speed.The purpose of this is to solve the three-dimensional vector computation that appears in the above-mentioned shadow image generation process. 3D shadow image generation processing is performed at high speed by executing matrix operations and matrix operations in parallel by the three or four floating point arithmetic units, and by executing processing such as judgment of the operation results by the arithmetic logic unit. It's about doing.

(Structure and operation of the invention) FIG. 1 shows an example of the structure of a three-dimensional shadow image generation apparatus that has a multiprocessor structure in which a plurality of processing units are connected in parallel. The configuration of the multiprocessor device is known as a configuration method that can perform a huge amount of processing in parallel without using a particularly high-speed device, and for example, the conventional device described above has a similar configuration. There is.

In FIG. 1, PU is a processor unit,
These processing units are connected to the system bus 10 and perform processing independently.

Further, DC is a data collector for collecting image data created by each processor unit PU, DM is a display memory for storing the collected image data and displaying it on a display, and CRT is for displaying images. The display device MP is a main control unit that controls the entire device.

Generally, in order to operate an apparatus configured as described above, first, object shape data used to generate one image and necessary processing programs are loaded from the main control section MP to each processor unit PU.

Next, each processor unit PU creates an image according to the loaded program and data, and displays the image on the display by transferring the image data to the display memory DM via the data collector DC. Each processor unit PU is responsible for creating a portion of the screen, and simultaneously executes image generation.

In order to perform image generation at high speed in a device configured in this way, there is a method of increasing the number of processor units;
There are ways to improve the processing power of individual processor units. However, in the former case, the scale of the device becomes enormous and its control becomes difficult, so it is not realistic to increase the number of processor units unnecessarily. The latter method requires only a small scale of the entire device, and is a more practical method in these days when various LSIs are becoming more sophisticated.

FIG. 2 shows an example of the configuration of a processor unit PU according to an embodiment of the present invention, which is applied to the three-dimensional shadow image generation apparatus having the multiprocessor configuration shown in FIG.

In the figure, IF is an interface unit with the system bus 10, DB M51 to #4 are data memories that store object shape data and processing parameters used in image generation processing, and F P tll to tt3 are floating point arithmetic units, FAPU is an arithmetic unit that combines a floating point arithmetic unit and an arithmetic logic unit in parallel, and 20 is a DBM #1 to I4 and F
A high-speed data bus connects PUjl to tt3 and FAPU, DC is a data collector for collecting image data created by arithmetic units and writing it to the display memory DM shown in Figure 1, and WCS is a data collector that connects each arithmetic unit, memory, and logic circuit. A program memory storing instructions for controlling S
EQ is a sequencer that retrieves instructions stored in the program memory WC8, and ADG is an address generator that generates a physical address of the DBM from a memory addressing instruction among the instructions retrieved by SEQ.

For the processor unit in FIG. 2, the first
From the main control unit MP shown in the figure, a processing program is stored in the program memory WC8 via the system bus 10 and the bus interface unit IF, and processing parameters such as three-dimensional object shape data and observation position necessary for image generation are stored in the data memory DBM. are loaded respectively.

Thereafter, the sequencer SEQ sequentially retrieves instructions from a predetermined location in the program memory WC8, controls each section according to the instructions, and executes processing.

FIG. 3 shows the arithmetic unit in FIG. 2, that is, floating point arithmetic units FPU#1 to #3 and an arithmetic unit FAP in which a floating point arithmetic unit and an arithmetic logic arithmetic unit are connected in parallel.
A specific example of the configuration of U is shown.

In FIG. 3, FPP#1 to tI4 are floating point arithmetic units, ALU is an arithmetic logic unit, MPX is a data multiplexer that selects one of a large number of data, and REGA1 to #4.
is a data register that stores calculation data, and LUT is a reference table that stores parameters for quickly calculating functions such as square roots and trigonometric functions.

As shown in Figure 3, three floating point calculation units FPP#
The output of the data register and the output of the adjacent floating point arithmetic unit are connected to each of the input terminals #1 to #3 in a cross-over manner via a data multiplexer MPX.

That is, the output of FPP#1 is sent to FPP#2 and #3,
Output of PP#2 to FPP#1 and #3, FPP#3
The outputs of the FPPs #2 and #1 are connected in a cross-cross manner so that their outputs can be input to FPP #2 and #1, respectively.

In addition, the FPP14 and the arithmetic logic unit ALU are connected in parallel, and the above three floating point units FPP#1 to
The output of #3 is connected to the input terminal via the data multiplexer MPX, and the output of the set of arithmetic units is connected to the FP
Data multiplexer MPX is connected to the input terminals of P#1 to 13.
connected via.

Since the calculation unit is configured in this way and each calculation unit operates independently, for example, if floating point calculation units FPP #1 to #4 are used, four types of floating point calculations can be performed in parallel. , it is possible to efficiently perform pipeline operations using cross-connections. Such an operation is suitable for efficiently performing coordinate transformation processing, etc., which often appear in three-dimensional image generation processing. For example, (x'y' z″r ] = [x y Z W] [
T] (1) is a point on homogeneous coordinates (X, Y, Z, W
) from the 4-by-4 transformation matrix [THC, the point (x', y
', z', w').

FIG. 4 shows the processing steps when this is executed by the arithmetic unit shown in FIG. 3. However, the coordinate values (X, Y
, Z, W) and the element Tl1(l y
j = 1 to 4) is the data register REG of each arithmetic unit in advance.
It is assumed that the numbers are stored in #1 to #4.

To calculate equation (1), 16 multiplications and 12 additions are required, but according to the arithmetic unit shown in Fig. 3, this can be done in 12 steps as shown in Fig. 4. . Therefore, compared to a general-purpose computer that performs sequential processing, it is possible to calculate less than half the step (1) equation. That is, even if the computation time required per step is the same, the computation speed can be more than twice that of a general-purpose computer.

Here, FIG. 4 is a diagram showing the calculation process of homogeneous coordinate transformation processing by the calculation unit of FIG. 3, in which a indicates the contents of the data register of the calculation unit, and b indicates the executed calculation step.

Next, the ray tracing method, which is a typical three-dimensional shadow image generation processing method, will be briefly explained. The ray tracing method is known, and the outline of its processing is shown in FIGS. 5 and 6.

First, in FIG. 5, an observation viewpoint V and a virtual screen S are determined.

Next, a vector R (this is called a ray vector) passing through the viewpoint v2 and one point P on the virtual screen S is determined.

Next, as shown in Figures 5 and 6, this vector is
Check whether it intersects with the dimensional object O, and if so, find the intersection Q. If there is an intersection Q for multiple objects,
It is checked whether the vector R' from the intersection Q closest to the viewpoint to the light gL intersects with the object, and if it does not intersect, the brightness of the intersection Q is calculated using the reflectance of the object.

The above process is repeated for all points on the virtual screen S.

The processing of the ray tracing method described above includes many three-dimensional vector calculations and the like. In particular, the process of determining the intersection between the ray vector R and object 0 and calculating the intersection point Q requires the most calculations, as it needs to be repeated a number of times proportional to the number of objects and the number of pixels of the screen to be created. do. The operation when this type of processing is performed by the arithmetic unit shown in FIG. 3 will be described.

The ray vector R is expressed by the following equation, using t as a parameter and the position vector 2 of the viewpoint V.

First, assume that the object O is a plane expressed by the following equation.

a fist X+b*Y+c fist Z+d=o
(3) From equations (2) and (3), the intersection Q between the ray and the object is given by tq that satisfies the following equation.

However, (Ux, Uy+ Uz), (Vxy V
y+Vz) are unit vector U and viewpoint vP, respectively
represents the element of the position vector V of .

Similar to FIG. 4, the calculation section of FIG. 3 can calculate the denominator and numerator of equation (4) in three steps each. However, since the division in equation (4) cannot be calculated directly with a floating-point arithmetic unit, the reciprocal of the denominator is calculated using the reference table LUT of the floating-point arithmetic unit PPP#4 in Figure 3, and this result and the numerator are It is calculated by finding the product of . Although reciprocal calculation requires several steps.

Nevertheless, equation (4) can be calculated in about 12 steps.

Since it is difficult to represent a curved object using only the plane expressed by equation (4), in order to express a variety of object shapes, objects are often expressed by a combination of quadratic curved surfaces expressed by the following equation. It is being done.

The m-th (11,)==l, 2.3) is the coefficient matrix element of the surface equation. The quadratic surface and light (
It can be calculated by substituting the ray vector equation 1) into equation (5) and finding a variable tq that satisfies the following equation.

A tq''=28tq +C= O (6) However, the coefficients A, B, and C of equation (6) are given by the following equation.

(m12*Uy*Vx+m23 ning Uz*Vy+m131
1Ux*Vz)C= m 11*Vx” + m22 umbrella Vy” + m33*Vz” +
(9) 2 meetings (m12*Vx bit Vy+m23
*Vy*Vz+m31 reference Vz*Vx)-2 From the above, the condition for the ray vector R to intersect with the quadratic curved object is that the quadratic equation (6) regarding tq has a real root. That is, if the following equation holds, an intersection exists.

D=B”−AIC≧O(10) Although the detailed calculation process is omitted, if the calculation parameters are set in the register REG of the calculation unit in FIG.
Using P#1 to I3, 8 steps to calculate A from equation (7), 9 steps each to calculate B and C from equations (8) and (9), a total of 26 steps to calculate quadratic equation (6) The coefficients A, B, and C of can be calculated. From the result, formula (10) can be expressed as 2
Since step calculation is possible, the intersection between the object represented by the quadratic surface and the needle line vector can be determined in 28 steps.

Therefore, in this case as well, calculations can be performed in less than half the steps compared to a sequential processing type general-purpose computer.

In addition, processing of 1 or more is performed using the floating point arithmetic unit FPP# in Figure 3.
1 to I3, so while this operation is being performed, the arithmetic logic unit ALU is configured to take out the data necessary for the above operation from the data memory and store it in the data register of each operation unit. If operated, it can be operated so that the execution time of instructions such as loading data from memory to registers can be ignored.

Therefore, the actual processing time can be reduced to a fraction of that of a general-purpose computer or the like.

The above is the main operation when three-dimensional shadow image generation processing using the ray tracing method is performed by the processor units shown in Figs. 2 and 3, but it also applies when applying other three-dimensional image generation processing methods. , and the coordinate transformation shown in equation (1), this type of processing can be executed at high speed.

The typical operations of the arithmetic unit shown in FIG. 3 have been described above, but these operations were performed after the data used for the arithmetic operation was stored in the data register.

Generally, the target is a scene containing a large number of objects, so as shown in FIG. 2, it is necessary to provide a large-capacity data memory for storing three-dimensional shape data necessary for calculation.

Therefore, it is necessary to take out the data necessary for the calculation from this type of data memory and transfer it to the data register of the calculation unit shown in FIG. 3 at high speed.

In order to solve this problem, data memory D in FIG.
A high-speed data bus 20 connecting the BM and each arithmetic unit is configured so that data can be transferred in parallel between the data memories DBM51 to #4 and the arithmetic units.

On the other hand, a memory address is assigned to the data memory, and by specifying a corresponding data storage area using this address, data can be written or read from the corresponding area. In the processing program for operating this type of device, from the point of view of the elegance of program creation,
Preferably, areas within the data memory are specified by relative displacement address values. Therefore, it is necessary to convert this into a physical address in the data memory.

FIG. 7 shows an embodiment of the address generator ADG in FIG. 2, in which the program memory W of the processor unit
It has a function of decoding the address command of the data memory DBM included in the processing program stored in the C8 and converting it into a physical address of the data memory DBM.

In the figure, WO2 and SEQ are the program memory and program sequencer shown in Figure 2, respectively, the instruction register is a register that stores instructions to be executed, the base address register is a register that stores a base address value, and the index register is a register that stores the base address value. A register that stores the relative address value from the address, an attribute register that stores parameter values that specify the conditions for address generation (designation of 1-dimensional access or 2-dimensional access, designation of access unit, etc.), and SUM that stores the addition The circuit, MUX, is a data multiplexer.

In addition, the two-dimensional address generation circuit handles the two-dimensional address of (x+y) when two-dimensional access is specified in the attribute register.
This is a circuit that converts a relative address specified by a dimension into a one-dimensional address, and a byte address generation circuit is a circuit that generates a byte address based on the address unit specified by the attribute register.

With this configuration, the program memory WC
The relative displacement address value DA in the instruction extracted from 8 is converted to the physical byte address value AA of the data memory as follows.

That is, when one-dimensional access is specified by the attribute register, AA=(IR+DA)*n+BR(11).

However, R is the relative address value in the index register, the base address value in the BR base register, and n is an integer to the power of 2 that indicates the address unit. For example, n = 4 indicates access in units of 4 bytes. .

Also, in the case of two-dimensional access specification.

AA=[(IR(x)+DA(x))+(IR(y)+
A physical byte address of the data memory is generated by DA(y))11Nl*n+BR(12).

Here, IR(x) and IR(y) are the relative address value in the X direction and the relative address value in the y direction indicated by the index register. For example, if the index register is 3
When it is 2 bits, the upper 16 bits are the y address and the lower 1
Define 6 bits like the X address.

Similarly, DA(x) and 0A(y) are the relative displacement address value in the X direction of the relative displacement address in the instruction register and the
This is the direction relative displacement address value.

Further, N is a positive integer that determines the size in the X direction, and generally an integer that is a power of 2 is selected.

As described above, the base address register, attribute register, and index register have the base address BR, access type, address unit n, N,
By storing the relative address IR and the relative displacement address IR in advance, the command can then be executed at the relative displacement address D in the processing program.
By simply representing A, it is possible to generate the physical address of the data memory according to the conditions.

Furthermore, since the present address generator can be constructed using only a simple logic circuit, the address calculation described above can be executed at high speed. For example, it becomes possible to perform address calculation in about 173 to 176 times compared to the case where this is performed using a general-purpose arithmetic and logic unit.

Note that data expressed in a table format and two-dimensional image data are converted into X by the two-dimensional address calculation described above.

Since it can be accessed by simply specifying the position in the y direction, it is extremely effective for high-speed access to these data.

(Effects of the Invention) As described above, according to the present invention, three-dimensional vector operations, matrix operations, etc., which are included in a large amount in three-dimensional shadow image generation processing, can be performed in parallel or in parallel using three or four floating-point arithmetic units. It can be executed in a pipeline, and furthermore, among the data such as the object shape stored in the data memory, it is generated at high speed by a memory address generator for data used in calculations, and the corresponding data is transferred via a high-speed data bus. can be supplied to the arithmetic unit, so that image generation processing can be performed without reducing the usage efficiency of the floating point arithmetic unit.

Therefore, in addition to greatly speeding up the process of generating realistic three-dimensional shadow images using the ray tracing method, which can simulate optical properties such as reflection and refraction, it is also possible to use other simple methods. Image generation processing can also be performed faster.

As a result, it is possible to significantly reduce the number of processing units required to obtain the desired processing capacity in devices with multiprocessor configurations, which has the advantage of making the device more compact and easier to control. There is also.

In addition, the processor unit of the present invention does not use any special elements, and general general-purpose LSIs can be used for elements such as floating-point arithmetic units and arithmetic and logic units. Even if the performance of various LSIs becomes higher, these elements can be applied to achieve even higher performance without significantly changing the configuration of the present invention. Alternatively, using recent more advanced LSI technology, part or all of the arithmetic unit, address generator, etc. of the processor unit may be made into an LSI, resulting in a more compact and highly functional device.

[Brief explanation of the drawing]

FIG. 1 is a general configuration diagram of a three-dimensional shadow image generation device having a multiprocessor configuration, FIG. 2 is an example of the configuration of a processor unit according to the present invention, and FIG. 3 is a detailed configuration example of the calculation section in FIG. 2. , Fig. 4 is a diagram showing the calculation process of homogeneous coordinate transformation processing by the calculation unit of the ft53 diagram, and Figs. 5 and 6 are explanatory diagrams of the ray tracing method, which is a typical three-dimensional shadow image generation processing method. FIG. 7, which is a diagram showing an overview of the processing, is an example of the configuration of an address generator for converting a data memory address instruction in a processing program into a physical address. 10... System bus, 20... High speed data bus,
PU: Processor unit, DC: Data collector, MP: Main control unit, D
M...display memory, CRT...display device, IF...interface section, DBM...data memory, FPU...floating point arithmetic unit, FAPU
...Arithmetic unit, WC8...Program memory, SEQ...Sequencer. ADG: address generator, PPP: floating point arithmetic unit, ALU: arithmetic logic unit, M PX: data multiplexer, REG
...Data register, LUT...Reference table, ■,...Viewpoint, S...Virtual screen, Q...Intersection,
L...Light source. Patent applicant: Nippon Telegraph and Telephone Corporation Figure 1 Figure 4 a Contents of data register of arithmetic unit Execution calculation steps Figure 5 () Figure 6

Claims (3)

[Claims] (1) In a processor unit of a three-dimensional shadow image generation processing device having a multiprocessor configuration, a set of three floating point arithmetic units and a set of one floating point arithmetic unit and an arithmetic logic unit connected in parallel are used. The inputs and outputs of the three floating point arithmetic units adjacent to each other are connected in a cross-crossing manner, and each output of the three floating point arithmetic units is connected to the arithmetic logic unit with the floating point arithmetic unit. Connect the input terminals of the set in which the arithmetic unit is connected in parallel, and the output of the set in which the floating point arithmetic unit and the arithmetic logic unit are connected in parallel to the input terminals of the three floating point arithmetic units. A three-dimensional shadow image generation processing device characterized in that floating-point product-sum operations, matrix operations, etc. are executed in parallel. (2) In the three-dimensional shadow image generation processing device, a data memory is provided corresponding to each of the sets in which three floating point arithmetic units and one floating point arithmetic unit and arithmetic logic unit are connected in parallel, and each of the above A high-speed data transfer bus that allows data to be exchanged independently between the arithmetic unit and the data memory allows data such as three-dimensional objects stored in the data memory and the calculation results of each of the arithmetic units to be transferred all at once. A three-dimensional shadow image generation processing device according to claim (1), characterized in that the three-dimensional shadow image generation processing device can be sent and received. (3) In the three-dimensional shadow image generation processing device, when generating the physical address of the data memory that stores the data necessary for image generation processing, the base address, relative address, one-dimensional or two-dimensional type, and access unit are specified. It has a register that stores each instruction parameter, and after adding the relative displacement address in the processing instruction and the relative address stored in the above register, adds the product of the access unit indicated by the above parameter and the above base address. A three-dimensional shadow image generation processing device, characterized in that the physical address of the data memory is generated and the processing command is executed at high speed.