JPS6372292A - Line/packet integration and exchange system - Google Patents

Abstract

PURPOSE:To enhance profitability as a switchboard by switching a line exchange signal and a packet exchange signal in a time slot of the same format. CONSTITUTION:A central exchange module consists of time switches 201, 211, packet buffers 202, 212, bus circuits 204, 214, a channel match logic 205, a spatial switch 206, and time switches 203, 213. When a time slot including a header and a signal written with a destination peripheral exchange module number and the distinguishment between line exchange and packet exchange reaches the central exchange module, a line exchange signal is given to the time switch 201 and the packet exchange signal is given to the packet buffer 202. The contents of the packet buffer 202 are divided by destinations and the arrived time slot is subjected to buffering. The same destination of each buffer is multiplexed by the bus circuits 204, 210 and placed on an idle time slot through a transmission line.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an integrated switching system for circuit switching and packet switching, and particularly provides an integrated circuit/packet switching system suitable for geographically distributed deployment. .

[Conventional technology]

A well-known example of integrated packet exchange is JP-A No. 59
There are "Hybrid Switching System" in Japanese Patent Publication No. 23658, "Line/Packet Integrated Switching System" in Japanese Patent Application Laid-Open No. 127844/1984, and so on. The former is a hybrid system in which the subscriber interface is integrated, and the line switching section and packet switching section are separated inside the exchange. As shown in FIG. 3, the latter is a system in which a plurality of distributed communication nodes are connected in a loop, and most of the communication nodes are exchange modules 30 having subscriber interfaces or trunk line interfaces, and other control Nodes with functions and maintenance/operation functions (control module 31, maintenance/operation module 32) are also connected. Each replacement module 3
0, both the circuit switching signal and the packet switching signal are packetized for each destination switching module, and the switching operation is performed via the loop 33.

[Problem that the invention seeks to solve]

The above-mentioned "hybrid switching system" requires a single-line signal switch and a packet switch, so it requires a large amount of hardware and is not economical.

Also, there is no concept of 1 distribution, and there is no problem with processing performance under heavy loads.

In terms of reliability, it is inferior to decentralized exchange systems.

On the other hand, the ``line/packet integrated switching system'' uses loops effectively to realize an integrated switching system that is easily distributed. However, since all exchange modules access the loop, the loop must operate at a high speed that can handle the total throughput of each module in order to not reduce the overall throughput. Therefore, expensive devices such as high-speed elements are required at the interface between each exchange module and the loop. In addition, since control is concentrated in one place, there is an additional condition that the control system must have sufficiently high performance. Therefore, it cannot necessarily be said that it is economical.

An object of the present invention is to construct a line/packet integrated distributed switching system that is more economical and has higher throughput. Specifically, it is a distributed switching system in a star configuration with a central switching module that is commonly accessed by all switching modules, and each peripheral switching module is configured so that the central switching module does not become a bottleneck for call processing. The objective is to construct a line/packet integrated distributed switching system that can process calls independently.

[Means for solving problems]

In order to achieve the above object, a plurality of peripheral switching modules each having an interface circuit for transmitting and receiving circuit switching signals and packet switching signals to and from subscriber lines or trunk lines;
A line/packet integrated switching system was constructed, consisting of one or more central switching modules connected in a star format to each of the plurality of peripheral switching modules via transmission lines.

The peripheral switching module has the function of determining the destination route by performing selective numerical analysis of the circuit switching signal input from the subscriber line or trunk line and header analysis of the packet switching signal. A frame with a time period is provided, and the frame is divided into a plurality of time slots, the number of which is determined according to a certain rule based on the number of peripheral exchange modules and the number of subscriber lines or intermediate NB lines possessed by the peripheral exchange module, A function of transmitting a header containing a circuit switching signal or a packet switching signal and a destination peripheral switching module number to the time slot and sending it to the transmission path, and a state of always remembering the idle state of the subscriber line or trunk line. It has a management function, a function to determine whether the subscriber line or trunk line is blocked when requested, and a function to transmit and receive the determination results between multiple peripheral switching modules. Has buffer memory.

The central exchange module manages multiple time switches that are connected to each peripheral exchange module via transmission lines, space switches that connect these time switches, and link blockage management for the incoming highways of the space switches. A first state management memory that performs frame-by-frame management, a second state management memory that performs link vacancy management for each frame corresponding to the outgoing highway of the space switch, and first and second state management memories. Referring to this, the channel match logic generates write or read addresses for each of the plurality of time switches and switches the positions of the time slots so that the plurality of time slots having the same destination are not switched at the same time.

Furthermore, in order to handle packet-switched signals, we devised the following two configurations.

The first method is to provide a packet buffer corresponding to the destination peripheral exchange module for each input side peripheral exchange module in the central exchange module, and connect each destination with a bus circuit for switching. In this case, the channel match logic described above is used only for circuit switched signals.

A second method uses the channel match logic also for packet switched signals. As will be described in detail later, in the case of packet-switched signals, all time slots are
There may be cases where it is not possible to replace within the frame. Therefore, a buffer memory is provided for each input-side peripheral exchange module to accommodate time slots that cannot be exchanged. However, in order to process circuit-switched signals with priority, a field is provided at the beginning of the frame, and the number of time slots in which circuit-switched signals are carried is communicated from each input-side peripheral switching module to the channel match logic unit. Ensure that the time slots marked with are processed without using a buffer.

[Effect]

For circuit-switched signals by the above configuration.

Perform the following call settings.

When a certain peripheral exchange module receives a call request from a subscriber, the peripheral exchange module analyzes the dialed digits,
Know the destination route. Next, select any peripheral exchange module belonging to the destination route and send a call signal. This calling signal is
This is one time slot, which includes the number of the selected peripheral exchange module as the header and the destination, and the call number, selected number, signal speed, and used time slot number are written as the ∆ number. When the time slot is sent over the transmission line to the central switching module, the central switching module reads the header and switches the time slot to the transmission line connected to the destination peripheral switching module. When the destination peripheral switching module receives this time slot, it determines whether the subscriber line or trunk line is busy and then sends a response signal back to the originating peripheral switching module. This response signal is also a time slot having almost the same structure as the calling signal. The number of time slots is
As will be described in detail later using an example, the setting is such that there are free time slots as long as the line is free, so
If the line is free, a response signal will always be returned. vice versa,
If a response signal is not returned after a certain period of time, it is assumed that the line could not be captured, and a calling signal is sent again to other peripheral switching modules belonging to the same route. When a response signal is returned (at that point, the call setup is complete. After that, the call signal is sent every frame using the same time slot that has already been communicated to the destination peripheral exchange module. do.

On the other hand, for packet switched signals, the above-mentioned call setup is not performed, and the peripheral switching module sends the signal to the central switching module in a time slot, regardless of whether the outgoing line is free. Therefore, if the outgoing line is blocked, it is necessary to buffer it within the central switching module.

In the first configuration, for each input side peripheral exchange module,
A buffer corresponding to the destination peripheral exchange module is prepared and packet exchange signals are distributed during buffering. Therefore, thereafter, the same destination buffers for each incoming peripheral exchange module are multiplexed by the bus circuit and sent to the destination peripheral exchange module.

In the second method, packet-switched signals are treated in the same way as circuit-switched signals. However, unlike circuit-switched signals, free circuits are not acquired in advance, so time slots with the same destination may be concentrated. For circuit-switched signals, time slots are swapped using the channel match logic described above to prevent time slots for the same destination at the same time from colliding, but for packet-switched signals, time slots for the same destination are concentrated without limit in number. Therefore, it may not be possible to replace all time slots within a frame without colliding. In the case of packet-switched signals, a certain amount of delay is allowed, so the time slots that cannot be replaced are returned to the buffer and processed in the first frame cycle.Packet calls are burst communications, so the same time slot is sent every frame in a row. The probability that the destination time slots will be concentrated is low, so the process progresses as this process is repeated several times.

In the manner described above, line/packet integrated switching becomes possible. Note that the central switching module, which is a common part, only performs autonomous switching based on the header of each time slot, and does not need to have a call processing device (central processor).

〔Example〕

The present invention will be explained in detail below. FIG. 4 shows the basic configuration of the switching system of the present invention, centered around a central switching module (CM) 401, and connected to peripheral switching modules (FM) via transmission lines 411, 412, etc. end Module)
In Figure 6, where 402-409 are connected, S M (
Peripheral exchange modules 402 to 405, denoted as Subscriber Modules, have subscriber line interfaces and are T M (Trunk Modules).
Peripheral exchange modules 406 to 409 marked with have trunk line interfaces. For example, a signal arriving from the subscriber line 410 is appended with a destination address (destination peripheral exchange module number) in the peripheral exchange module 402, passes through the inter-module transmission path 411, and is sent to the central exchange module 402.
Sent to 1. The central exchange module 401 refers to the address written in the header and, for example, if the destination is the peripheral exchange module 408, the inter-module transmission line 4
Switching to 12. Peripheral exchange module 408 removes the header and sends the signal to trunk line 413. The same applies to communication from the trunk line side to the subscriber line side. Since normal communication is bidirectional, the peripheral switching module (SM) of the subscriber line interface may e.g.
403 and 405, they are installed in pairs in pairs. It should be noted that the peripheral exchange modules (TM) of the trunk line interface do not need to be installed in a distributed manner, so they are placed close to the central exchange module.

The number of peripheral replacement modules and the ratio of SM and resistance can be freely determined depending on the circumferential shape. Of course, if only the TM is installed, it will function as a relay exchange.

Next, with reference to FIG. 5, the handling of circuit switched signals will be explained in detail.

The peripheral exchange module 402 includes a time switch 501° link interface 502. It is composed of a control system 503 and a state management memory 500. Signals from subscribers are inputted from the subscriber line, which are time-division multiplexed via a line concentrator (not shown). The time switch 501 rearranges the time-division multiplexed signals by destination module according to instructions from the control system 503. The link interface 502 adds a header such as a destination address to this, puts it on a time slot together with a signal going to the same destination, and sends it out to the central switching module 401 .

The central exchange module 401 has a link interface 5
04.514, time switch 505.515, channel match logic 511. It consists of a space switch 5061 and time switches 507 and 517. The time slot received from the peripheral exchange module 402 is sent to the link interface 50.
Step 4 reads the header. Channel match logic 511 is
From the header information of each time slot arriving from each peripheral exchange module, each time switch so
Generates a read or write address for s, sis. This operation can be performed only by wired logic. The time switches 505 and 515 swap time slots based on addresses generated by channel matching logic, and in order to swap time slots within one frame without completely colliding,
That is, in order to achieve non-blocking, the outgoing link is operated at twice the speed of the incoming link. Kukansui J7chi506
The 0 time switch 507.517 switches each time slot according to the destination address written in its header and sends it to the time switch 507.517 connected to the destination peripheral exchange module.
．． The operating speed doubled in step 515 is restored to the original speed, and the time slot is sent to the transmission line connecting to each peripheral exchange module.

Peripheral exchange module 404 connects link interface 5
09, a time switch 510, a control system 508, and a state management memory 518. The time slots arriving from the central switching module 401 are sent to the link interface 509.
The header is removed at
It is written to 0 and the signal is time-division multiplexed again and sent out to the trunk.

The flow of circuit switching signals has been explained using FIG. 5, and now the operation at the time of call setup will be described. As shown in Figure 8,
When a subscriber line side peripheral switching module (hereinafter abbreviated as SM) detects a call, it analyzes selected numbers and determines the route.

Therefore, you must have all the necessary data on your own. Once the destination route is determined, generally multiple trunk-side peripheral exchange modules (hereinafter abbreviated as TM) are installed for each route.
There are so choose any one from them. Various selection algorithms are conceivable, but since the peripheral exchange modules on the originating side do not communicate with each other, it is desirable to use an algorithm in which each originating side peripheral exchange module selects a different terminating side peripheral exchange module.
If there are many communications from M to a specific route, that SM can always select a specific TM, and other SMs may not select that TM, depending on the circumference. After selecting a TM, a calling signal is sent to that TM. This may be sent using another signal line, but in this embodiment, the time slot of the communication path is used. The information part of the call signal includes:
Write the call number, selection digit, signal speed, and time slot number used, and the TM will then receive it. It is possible to recognize which time slot (if one time slot includes a plurality of calls), which number, and which bit of information corresponds to that call. (In order to reduce the header overhead, 1. A method in which multiple calls going to the same route are placed in one time slot is a common method as a type of group switching.) The TM that received the calling signal Control system 50 shown in the diagram
8 refers to the state management memory 518, determines whether the lines it accommodates is empty or busy, and if there is a free line, captures one of the lines, rewrites the line state management memory 518, and responds. send the signal back.

A response signal is sent from the originating TM paired with this receiving TM, and received by the SM paired with the originating SM. The call number and the used time slot number are written in the response signal. When the response signal is received by the SM, the call setup is complete. According to this method, the peripheral switching module only manages the state of the line it accommodates, determines whether it is blocked, and notifies it, and can seize the line and start communication without the intervention of the central switching module. You can secure the time slot you want to use. As will be described in detail later, such a call setup sequence is not used for packet switched signals. In the case of packet-switched signals, it is possible to accumulate them, so it is not necessarily necessary to capture the line;
This is because it may be better to accumulate a certain amount of data and send it all at once in bursts for better line efficiency.

FIG. 6 shows the frame structure of the inter-module transmission path. Here, one frame is 125 μs, and the frame is divided into one time slot. however.

At the beginning of the frame, a field 600 for recording the number of time slots for circuit-switched signals in that frame.
is provided. Each time slot consists of a header 601 and an information section 602.

FIG. 7 shows the configuration of the time slot in more detail. Header 601 is divided into five areas. The respective contents are an empty/busy indication 701, a line/packet/call control information indicator 702, a destination address 703, a calling address 704, and a call number 705.

Next, the number of time slots and the length of the information section when handling circuit switched signals will be explained. As a prerequisite, the maximum C
Assume that there are n peripheral exchange modules accommodating lines, that the header in a time slot is h bytes, and the information part is i bytes. The number of time slots in this one frame t
Make sure that the following conditions are met. In other words, the most inefficient state is that only one audio line (i.e., one byte) of information is sent to (n-1) destinations other than a certain destination peripheral exchange module, and the remaining (
c-(n-1)) Even if the information of the circuit is all sent centrally to one destination peripheral switching module, there should be no shortage of time slots. Expressed as a formula, j.

This means that the following must be met.

On the other hand, there is overhead due to headers. can be expressed as follows.

t・(h + j) 0= (2) The larger the number of time slots t, the larger the overhead, so from the above equations (1) and (2), the optimal I1 of t and 1
Find 1μ.

By determining the number of time slots in this way, a peripheral exchange module can always secure time slots for communicating with that peripheral exchange module as long as the line is free, and resource management in the peripheral exchange module can be This can only be done in the blocked state.

Next, the channel match logic in the above-mentioned replacement unit will be explained in more detail.

FIG. 9 shows a block diagram of the channel match logic.

Link interface 504.514 and time switch 5
05.515 and space switch 506 are the same as those described in FIG.

Channel match logic 511 connects address multiplexers 901 .
Primary link management memory 902. Secondary link management memory 9
03 and an address calculation unit 904. Note that the "primary link" referred to here is the ingress link of the space switch 506, and the "secondary link" is the egress link of the space switch 506. The headers are read by the link interfaces 504 and 514 and multiplexed by the address multiplexer 901. Among the contents of the header, the originating address (SA) is the read address of the primary link management memory 902, and the destination address (DA) is the read address of the secondary link management memory 903. The primary link management memory 902 stores the vacancy status of each time slot of the primary link corresponding to the peripheral exchange module, and the secondary link management memory 903 stores the vacancy status of each time slot l- of the secondary link corresponding to the peripheral exchange module. The status is written.

In order to create a non-block communication path, the space switch operates at twice the speed, so the number of time slots is twice the number of time slots input in one frame cycle. If you look at a certain point in a frame, you can see which time slot of each of the primary link and secondary link is vacant in that frame. This will be explained in more detail with reference to FIG. The figure shows the incoming time slot destined for the 5th outgoing peripheral switching module from the i-th incoming peripheral switching module.

(In the figure, 1 is occupied and 0 is empty) ■Outgoing address〃j,
Primary link management memory, 2 at destination address 〃j, respectively
Read the contents of the next link management memory. ■OR the two to find the common vacant area, ■1 of the frame
The empty space near the beginning of the number is the address at which this time slot should be written to the time switch. ■The position used is
Rewrite 0 to 1 and feed back to the primary link management memory and secondary link management memory.

The time slots that arrived in this way are randomly written to each of the nine time switches based on the above write address, and the primary link management memory and secondary link management memory are rewritten, and the After processing, if the data is sent to the space switch 506 by sequential read, no time slot collision will occur during switching at the space switch 506.

In the above description, the time switch has a write surface and a read surface, which are used alternately, so that it has a so-called double buffer configuration. Further, although the explanation has been made using random write and sequence 9 cell read, the same function can be obtained by sequential write and random read.

The space switch 506 may be of any configuration as long as it can autonomously switch according to the destination address in the header of each time slot.

An example is shown in FIG. Here, selectors 1111 to 1113 are provided for each destination, and the switching address generation circuit 1
It has a simple configuration in which a switching address is generated based on header information in 121 to 1123 and switching is performed.

In order to match the timing, a retiming circuit 1101
~1103 is provided.

As can be seen from the above description, the central switching module can be constructed entirely of wired logic and is a passive module that does not require a control processor.

Next, the flow of packet exchange signals will be explained. As already mentioned, in the case of packet-switched signals, call setup as shown in FIG. 9 is not performed, and therefore, line acquisition is not performed. Packet-switched signals are sent using all time slots not used for circuit-switched signals. This is done in order to use the line efficiently and to be able to adequately handle burst communication where a large amount of data is sent at once although the holding time is short. However, this requires a buffer memory in both the peripheral exchange module and the central exchange module.

FIG. 2 shows an embodiment of the High Packet Integrated Channel. This figure is a block diagram of the central switching module. Time switch 201.211, bucket buffer 202.
212, bus circuit 204.214 channel match logic 2
05, a space switch 206, and a time switch (speed conversion buffer) 203.213. As explained in FIG. 7, when a time slot containing a header and a signal in which the destination peripheral switching module number and the circuit switching/packet switching distinction are written, reaches the central switching module from the transmission path #1, for example, the circuit The exchange signal is distributed to the time switch 201, and the packet exchange signal is distributed to the bucket buffer 202. Switching of circuit-switched signals has already been described. The inside of the packet buffer 202 is divided by destination, and the arrived time slots are buffered here by being divided by destination. Similar distribution is performed for each transmission path, and then buffers with the same destination are transferred to the bus circuit 204.
．． 210, respectively. The multiplexed signal is placed on the outgoing transmission line in an empty time slot on which no circuit switching signal is carried. In this embodiment, the circuit switching signal and the packet switching signal are separate in the switching part, but the logical configuration is relatively simple, and the multiplexed packet switching signal can be efficiently sent to the output transmission path. .

Next, a second embodiment will be explained with reference to FIG. Like FIG. 2, FIG. 1 is a block diagram of a central exchange module. Instead of bucket buffers 202, 212 and bus circuits 204, 214 in FIG. 2, first bucket buffers 102, 112. and second bucket buffer 1.0
4.114 is placed. The feature of this configuration is that the time slot carrying the packet switching signal is also switched by the time switch 101, 111 and the space switch 106 in the same way as the circuit switching signal.

However, since priority is given to single-circuit switching signals, packet switching signals may require waiting, and therefore the first bucket buffer 1.02.112 is provided6.
In order to switch packet-switched signals in the same way as circuit-switched signals, channel match logic must be applicable to packet-switched signals as well. For circuit-switched signals, the number of time slots with the same destination channel unit was limited by the number of lines, but for packet-switched signals, an unlimited number of time slots can be sent as long as the time slots are free. Therefore, even if the channel matching logic described above is used to prevent time slots for the same destination at the same time from colliding, there will be cases where the time slots cannot be replaced. A second bucket buffer 104.114 is provided to accommodate this non-replaceable overflow time slot. As mentioned above, the channel match logic 105 is informed at the beginning of the frame how many time slots carrying circuit-switched signals are in the frame, so it prioritizes circuit-switched signals and only transmits packet-switched signals. You can make it overflow. From the second bucket buffer 104.114, it is immediately returned to near the beginning of the first bucket buffer, and this is repeated until a successful channel match is achieved.

According to this embodiment, it is possible to realize a configuration in which the switch section is also line/packet integrated, and there is no need to provide a packet buffer for each destination.

It has been explained that the line/packet integrated central switching module can be realized by the above two embodiments.

FIG. 12 shows an example of the system configuration. This configuration example is.

By having multiple central exchange modules, it is possible to distribute the load and risk. Since the central switching module is a passive module without a call processing processor, such decentralization is easily achieved.

Since the configuration is such that the same peripheral exchange module can be reached through either central exchange module, even if one fails, the other one will continue to operate, so there will be no problem as long as there is no overload.

〔Effect of the invention〕

According to the present invention, it is a star-shaped distributed switching system in which a central switching module is placed at the center and peripheral switching modules are distributed, and is a line/packet integrated distributed switching system that can handle line switching and packet switching in an integrated manner. An exchange system can be constructed. especially.

Since the central exchange module does not have a call processing function and can basically be configured with wired logic, the processing capacity will not be reduced due to processing equipment bottlenecks. Additionally, the central switching module itself can be easily decentralized.

According to the present invention, since circuit switching signals and packet switching signals are switched in time slots of the same format, the economical efficiency of the switching system is improved. Multiple speeds and high-speed broadband services can be uniformly provided to subscribers. Since circuit-switched signals are switched with priority,
The delay time is fixed and the absolute delay time is also small.

[Brief explanation of the drawing]

Figure 1 shows the first circuit/packet integrated central switching module.
2 is a block diagram showing the second embodiment, FIG. 3 is a block diagram showing a conventional example, and FIG. 4 is a block diagram showing an example of the configuration of a distributed layer switching system. FIG. 5 is a block diagram showing details of FIG. 4, FIG. 6 is an explanatory diagram of a frame configuration, and FIG. 7 is an explanatory diagram of a time slot configuration. FIG. 8 is an explanatory diagram of the call control sequence, FIG. 9 is a block diagram showing a part of FIG. 5 in detail, FIG. 10 is an explanatory diagram of the operation of FIG. 9, and FIG. 11 is a part of FIG. 5. FIG. 12 is a block diagram showing an example of the system configuration. In the figure, 401-m-central exchange module, 402
~409-m-peripheral exchange module, 500-m-state management memory, 501,507-1-time switch, 50
2,504-m-link interface, 503-m-
Control circuit, 505-m--temporal switch, 506--space switch, 511-m-channel match logic, 901
-11 address multiplexer, 902---Primary link management memory, 903---Secondary link management memory, 904-m
-Address calculation section, -1,\-

Claims (1)

[Claims] 1. Circuit switching information and packet switching information from a subscriber line or trunk line are divided into fixed-length blocks, and each block is exchanged in units of information chunks with a header containing a destination address added. The communication path of the line/packet integrated switch that carries out the process has an input highway and an output highway consisting of time slots that carry multiple pieces of information, and has a primary and secondary time switch, a space switch, and each primary time switch. and each incoming highway is connected in multiple ways to the primary time switch and the buffer memory group, and each outgoing highway is connected to the secondary time switch and the buffer memory group. A line/packet integrated switching system characterized by dual connection with a buffer memory compatible with output highways. 2. Circuit/packet integration in which circuit switching information and packet switching information from subscriber lines or trunk lines are divided into fixed-length blocks, and each block is exchanged in units of information chunks with a header containing a destination address added. In the communication path of the exchange, it has an input highway and an output highway configured by time slots carrying a plurality of information blocks, primary and secondary time switches, first and second buffer memories, and a space switch, A first buffer memory and a primary time switch are connected in series corresponding to each input highway, and the time slot on the input highway is the first time slot.
A connection is provided to bypass the first buffer memory so that the primary time switch can be reached with or without passing through the buffer memory of the primary time switch, and a second buffer memory is further connected in parallel to the primary time switch. A line/packet integrated switching system characterized in that the second buffer memory is connected to the first buffer memory so that the contents thereof can be transferred in units of time slots.