JPS6367650A - Monitoring system for software processing - Google Patents

Abstract

PURPOSE:To form an entire constitution just with a single IC element by using an OR gate and an AND gate to monitor the soft processing normalness and therefore incorporating a monitor circuit of a software processing system into a gate array. CONSTITUTION:When the software processing has the normal working, an output fixing signal applied onto a signal line 100 from a power supply unit is set at level '0' when the power supply of a device is applied. Thus the output signal delivered onto a signal line 106 from a counter 3 is initialized at level '0'. While a counter reset instruction is not normally carried out when the software processing has the abnormal working. Thus the counter reset signal is set at level '1' on a signal line 105 and a resetting action is impossible with the counter 3. Then the counter 3 is continuously counted up by the clock on a signal line 102 and the signal output is set at '1' on the line 106. The normalness of the software processing is monitored in response to the level'0/1' on the line 106.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing device, and particularly to a method for monitoring the normality of software processing.

(Prior art) Conventionally, in such a system, the hardware side has a counter that is incremented by 10 and is reset by a counter reset circuit, and the software side has a counter reset circuit provided in the processing routine within a certain period. Ta. Therefore, an abnormality in the no-aware processing was detected due to this K. Further, whether or not the software processing is being performed normally is confirmed by checking that the counter does not overflow when the counter reset circuit is executed.

Conventionally, the step clock of the counter has been composed of a multivibrator element, a resistor element for timing adjustment, and a capacitor.

(Problems to be Solved by the Invention) In the conventional abnormality detection method described above, even if a gate array is attempted to be used, it is not easy to implement a clock generation circuit for incrementing the counter into an integrated circuit element. There were seven drawbacks.

It is an object of the present invention to eliminate the above-mentioned drawbacks by incorporating a clock generation circuit for kakunta step reversal using an OR gate and an AND gate into an integrated circuit element, thereby making it possible to easily detect abnormalities in software processing. It is an object of the present invention to provide a monitoring method for software processing configured in the following manner.

(Means for Solving the Problems) The software processing monitoring system according to the present invention includes a counter, a clock generation circuit, and a counter reset circuit.

The counter is initially set when the power is turned on, and is used to notify an abnormality in the software processing when the content reaches a certain value.

The clock generation circuit generates a clock when the power is turned on, and increments a counter using the clock.

The counter reset circuit is for initializing the υ counter with a guarantee signal indicating that software processing is being performed normally.

(Example) Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit connection diagram showing the configuration of an embodiment for realizing a software processing monitoring method according to the invention. 1st
In the figure, 1 is a clock generation circuit, 2 is a counter reset circuit, 3 is a counter, 10 is a NAND gate, 11
-1.11-n are AND gates, 12 are NAN
This is the D gate.

FIG. 2 is a time chart showing the operation of the clock generation circuit of the device shown in FIG. m1.

In the clock generation circuit 1, the input is connected to the first input terminal of the NAND gate 10, and the output of the NAND gate 10 is connected to A via the AND gates ]1-1 to 1]-(n-1).
It is connected to the input terminal of the ND gate 11-n, and the output terminal of the AND gate 11-n becomes the output terminal of the clock generation circuit 1. This output terminal is also connected to the input terminal of the HAND gate 12, and the output terminal of the NAND gate 12 is N
It is connected to the second input terminal of AND gate 10.

Next, the operation of the apparatus shown in FIG. 1 will be explained.

Clock generation circuit 1 is activated by an external trigger on signal line 100. As shown in the time chart of FIG. 2, the external trigger on the signal line 100 triggers the NAND gate IOK.
When it is input, the time '1' is
After a delay of no, the output of the AND gate 11-n is connected to the signal line 1.
It becomes level 11 on 02. As a result, the output of the NAND gate 12 becomes %Q level on the signal line 103,
This is fed back to the NAND gate 10. Therefore, A.N.
D gate 1]-n output is on signal line]02 with delay time T
After DoO, it changes from %1 level to %OI level. Therefore, the time during which the AND gate 11-n maintains the %IN level is the sum TDI of the time TD0 and the delay time TDo of the NAND gate 12. While the external trigger 7111β11 level on the signal line 100 continues in this manner, a clock signal with a pulse width of time TD1 is periodically outputted from the AND gate 11-n onto the signal line 102. .

Next, when the external trigger on the signal axoa reaches the %0 level, the output of the AND gate 1l-n becomes % on the signal line 102.
QI level), no clock signal is generated. The output confirmation signal of the power supply unit is normally used as the external trigger signal on the signal line 00.

When the count value is incremented to a specified value by the clock signal from the AND gate 11-n onto the signal line 102, a counter output signal is output from the counter 3 onto the signal line 200 as % 1 lebel. Furthermore, when a %OR level signal is input to the reset terminal, all counts are cleared.

The counter reset circuit '2 receives an external trigger signal on the signal line 100, a counter reset circuit installed in the software processing routine, and a signal K? When the signals output on f#104 respectively reach the %0# level, the signal 41
When the OR output on 05 reaches the %ONOR level, the counter is reset in a strong=lI manner.

A clock signal is periodically output from the clock generation circuit 1 onto the signal line 102. The period 2X'I'DI of the clock signal on the signal line 102 and the period TCR in which the counter reset circuit provided in the software processing routine is executed are set so that they meet the conditions of 2xTD, )'l'OR. ing.

Now, if the software processing is operating normally, the output confirmation signal from the power supply unit to the signal line 00 will be at the 10# level when the device is powered on, so the output confirmation signal from the counter 3 to the signal line 106 will be at the 10# level. The output signal is initially set to the turtle 0# level. Thereafter, the counter 3 is incremented by the clock signal. Even if the counter is stepped, the counter reset circuit provided by the software processing routine is executed normally.
The counter reset signal on the signal line 105 is output at the %Ol level. Therefore, the counter is forcibly reset and outputted as the counter output output βOI level on the signal line 06.

Conversely, if the software processing is operating abnormally, the counter reset circuit will not be executed normally, and the counter cannot be reset unless the counter reset signal on the signal line 105 reaches the %11 level. Therefore, the counter continues to be incremented by the clock on the signal line 102,
The signal output on signal line 06 appears as %I.

As explained above, the normality of software processing is monitored according to the 10/II level on the signal line 106.

(Effects of the Invention) As explained above, the present invention can perform software processing by using an OR gate and an AND gate without using a multivibrator element and timing circuit components such as resistors and capacitors. By monitoring the normality, a software processing type monitoring circuit can be incorporated into the gate array, and the entire gate array can be constructed with one integrated circuit element.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the software processing monitoring method according to the present invention. FIG. 2 is a time chart showing the operation of the clock generation circuit of FIG. 1. ]...Clock generation circuit 2...Counter reset circuit 311...Counter 10.12 fist...NAND gate 1 ]-1~l 1-n @a @AND gate 10
0~106...Signal line

Claims (1)

[Claims] A counter that is initially set when the power is turned on and notifies an abnormality in software processing when the contents reach a certain value, and a clock that is generated when the power is turned on, and the counter is incremented by the clock. and a counter reset circuit for initializing the counter with a guarantee signal indicating that the software processing is being performed normally. method.