JPS6367643A - Generation of parity - Google Patents

Abstract

PURPOSE:To contrive to improve the precision of data by producing a parity based on the bit of a part obtained by dividing the bit number of data into N parts. CONSTITUTION:The bit number L of data D is divided into N parts Di (D1-DN) and Di-Ds is added after deleting an optional part Ds out of the part Di. This binary addition value is referred to as X and multiplied by (n) and this arithmetic result nX is added with the part Ds. Thus a parity p=Ds+nX (n: integer) is obtained. Here the number of bits of the member of nX are set equal to those of the part Ds. Thus the number of bits of a parity code is cut down to less than 1/2 number of bits of the genuine data excluding the parity code. Then the data length is reduced together with reduction of redundancy and therefore the precision of data is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity generation method used for detecting errors in digital data, and particularly to improving data accuracy.

[Conventional technology]

Conventionally, when switching channels on devices such as TVs and VTRs by remote control, a code indicating a specific function such as channel switching is transmitted from an encoder using a carrier medium such as infrared rays, and the transmitted code is transmitted to the device side. A method is adopted in which the signal is received and decoded by a decoder.

In such remote control, digital data representing a specific function is made into one word by adding a parity code for detecting errors in the data to a true data code.

For example, code A representing data consisting of 8 bits,
When sending code B, as shown in FIG.
B is applied to the upper and lower bits of 4 bits each, and the inverted code τ of code A and the inverted code d of code B are added as parity codes to make l word 16 bits, and on the decoding side, each code A , B and each inversion code τ, ■ are used to detect errors in data.

[Problem that the invention seeks to solve]

By the way, in such a parity check, the number of bits of the code representing true data is equal to the number of bits representing the code for parity check, so the data length is long at 16 bits in the example shown in Figure 8. , the power loss required for transmission per word is large, and the amount of data stored in the storage means is also large.

In addition, in this case, the accuracy of the data of codes A and H is low because one word is made up of two redundancies due to the addition of inverted codes A and B, and the transmission and reception speed of unit data is low. There are drawbacks.

Therefore, this invention shortens the data length and
The purpose is to provide a parity generation method that improves data accuracy.

[Means for solving problems]

The parity generation method of this invention is as shown in FIG.
Divide the number of bits of data with any number of bits into N,
Part Di obtained by division (=D1, D2
...DN) any part in Ds, part Di
If the binary addition value of the part excluding part Ds (S=1.2...N) is X, then the parity p is p = Ds + n X (where n is an integer)...
(1) and the number of bits of parity p for each part Di
The content is set equal to the number of bits.

[For production]

The parity generation method of this invention is as shown in FIG.
Data D is divided into bits LGN, and the parts obtained by this N division are Di("Dl.

D2...DN), part D is set in step S2.
Add Di-Ds after removing any part DS in part Di from i, and let the binary addition value be X, and this 2
The base addition value X is multiplied by 3, and the calculation result nX and an arbitrary par) Ds are added to obtain the parity p shown in equation (1). The number of bits in the term nX is set equal to the number of bits in part DS.

Therefore, according to such a parity generation method, each part D i (=D1, D2...DN)
The number m of bits that data D has decreases in proportion to N, and becomes less than 1/2 of the number of bits of data D.

Then, by setting the number of bits of the term nX equal to the number of bits of par) Ds, the number of bits of parity p becomes equal to the number of bits m of each part Di, and the number of bits of parity code becomes equal to the number of bits of parity code The data length is reduced to 1/2 or less of the bit p of the other true data, and data accuracy is improved by reducing redundancy.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the parity generation method of the present invention.

This parity generation method is realized by installing a parity calculation program and storage means 4 for storing the calculation results in the parity calculation means 2. FIG.
It is assumed that data D having an arbitrary number of bits is added to .

As shown in FIG. 2, the parity calculation means 2 divides the number of bits of data D into N in step S1, and
Di (=D+, D
2...DN), part D is set in step S2.
After removing any part DS in part Di from i, add Di-Ds, and let the binary addition value be X,
The X is stored in the storage means 4.

Next, in step S3, the added value X is multiplied by three, and the calculation result nX is stored in the storage means 4 again. Here, n is, for example, ax15+3. aX16+5, ax15+5. a
X16+7. ax15+9゜ax16+10. aX16
+11. Take a straight line such as ax16+13, where a is an integer.

Next, the calculation result nX stored in the storage means 4 and an arbitrary part DS are added to obtain the parity p shown in equation (1). Then, the number of bits in the term nX is made equal to the number of bits in part DS.

Therefore, according to such a parity generation method, the number m of bits that each par) Di (=D+, D2 . . . DN) has becomes smaller in proportion to N.

For example, if N=2.3...K, then the number m of bits of each part Di corresponding to N is m=L/2. L/3
...L/, and the number of bits is less than 1/2 compared to the number of bits of data D.

Then, by making the number of bits of the term nX equal to the number of bits of part Ds, the number of bits of parity p becomes equal to the number of bits of part Ds.
The number of bits of the parity code is equal to the number of bits of i, the number of bits of the parity code is less than 1/2 of the number of bits of the true data, and the data length representing one word is the number of bits of the true data when N=2. The maximum value is the sum of 1/2 the number of bits, and the number of bits decreases in proportion to N.

For example, set the number of bits of data A and B to 8 bits, N=2
In this case, the parity p is p=4, and as shown in FIG. 3, when one word is composed of data codes A and B and parity code P, the number of bits in one word is 12.
This has a bit structure, which reduces the number of bits by 4 bits compared to the example shown in FIG. 8, and also improves the level of data by reducing redundancy.

FIG. 4 shows a remote control encoder that is a specific embodiment of the parity generation method of the present invention.

As shown in FIG. 4, this encoder is installed in a remote control controller for aH such as a TV or VTR that is to be remotely controlled, and key matrix 1
0 corresponds to the keyboard on the operation panel of the controller.

The encoder unit 12 is composed of a one-chip IC, and generates a code output corresponding to the key input from the key matrix 10. In this encoder unit 12, the input detection circuit 120 detects the key force input from the key matrix 10. In this case, the input detection circuit 120 provides the key scan signal from the oscillator 121 to the key matrix 10 to detect the key force data and the slide switch. detects data input as an electrical signal and generates a data input signal.

This data input signal is applied to the pattern signal generation circuit 122 together with the clock pulse CLK from the oscillator 121, and the pattern signal generation circuit 122 generates a pattern signal corresponding to the data input signal in synchronization with the clock pulse CLK as shown in FIG. The data is read from the memory 10 installed as the storage means 4 shown in FIG. The pattern signal read out from the memory 40 includes, for example, a start code ST, ID code lower bits IDL (for example, 4 bits) representing an identification code set for each device, and ID code upper bits, as shown in A of FIG. IDM (for example, 4 bits), a data code lower bit DATAL (for example, 4 bits) representing a function code P representing the function of the equipment, and a device code Q for specifying the equipment, and a data code upper bit DATAM (for example, 4 bits).

The modulation circuit 123 is composed of, for example, a pulse width modulation circuit, modulates the transmission pulse read out from the memory 40, and sends the modulated output to the parity calculation circuit 20 as the parity calculation means 2 shown in FIG. Add.

The parity arithmetic circuit 20 generates data D having arbitrary pins 1-BL added from the modulation circuit 123 (al ID code lower bit IDL and ID code upper bit IDM (b) data code lower bit D A T A L and data The upper bits of the code DATAM are taken in, and by the calculation of formula (11), as shown in Figure 5, 8, for (al, (b)), 10
Code parity IDP, data code DATA L
, D AT A P is generated corresponding to D AT A M.

The generation of each parity IDP and DATAP can be performed by converting 2(1) into the following calculation method. For example, in the data of fal, (bl, if the upper bits of the 4 bits are M and the lower bits are L, then 1. By each of the following equations (2) to (8), M + L = A +
...(2) A1 +M -Az ・
...(3) A2 10M=to3 ...(4)
A3+M=A4 ・ ・ ・ ・(5) A4
+M “A5 ・ ・ ・ ・(6
)A5+M=A6 ・ ・ ・ ・(7)A
6+M=P (8) Parity P is obtained.

Table 1 shows the data code lower bit DATA L
, represents an example of a data code upper focus DATAM and a parity code.

(Margins below this page) Table 1 As is clear from Table 1, unless 3 or more bit errors occur at the same time due to the 4-bit parity P for 8-bit data, the data will not match. It can be seen that since this does not occur, the accuracy of the data is dramatically improved.

Then, as shown in A of FIG. 5, the code representing the parity P obtained for each (al, (bl) is written as the ID code parity IDP in the rear part of the ID code upper bit IDM.
Furthermore, one word of data is constructed by placing the data code parity DATAP at the rear of the data code upper bit DATA. In this case, one word consists of 24 bits following a start bit ST, and B in FIG. 5 shows a specific data pulse. In this embodiment, "ro 101j as IDL, rloolJ as IDM, rolooJ as IDP, ro 100 as device code Q" are stored in the memory 40 as fixed data, and are read out every time one word of data is formed. These fixed data are stored in the memory 40 as identification data corresponding to the device, for example, when the IC is manufactured.

By the way, a logic "1" in the data means a pulse whose low (L) level interval is T and a high ()■) level interval is 2T, and a logic "0" means a pulse whose low (L) level interval is T and the high ()■) level interval is 2T, as shown in FIG. As shown in D in Figure 6, both the L level section and the I] level section are T.
The pulse, start bit ST and end bit END are given as pulses having an L level section 2T, as shown in FIG. However, T represents the unit time given by the clock pulse CLK. As is clear from such a pulse width relationship, by reducing the number of parity bits, the number of bits per word decreases, so the memory 80 of the memory 40 is reduced and its storage area is narrowed. , power loss is suppressed by the reduction in the number of bits, resulting in power savings.

One word of data following the start bit ST consisting of such a combination of pulses is applied to the timing circuit 124, divided into words according to the timing signal read out from the memory 40, and remotely controlled. The signal is output as a signal and applied from the encoder unit 12 to the base of the transistor 4 installed in the output stage.

The transistor 14 performs a switching operation by a pulse representing one word of data, and when the transistor 14 is conductive, current flows through the infrared light emitting diode 16. As a result, the light emitting diode 16 can transmit one word of data to the decoder on the device side by intermittent infrared light emission, and 18 indicates the transmitted infrared light.

Figure 7 shows a device installed on the side of the device that is subject to remote control.
A decoder is shown that receives the transmitted infrared rays 18 and decodes the data code.

This decoder is composed of a receiving circuit unit 22 and a decoder unit 24, each of which is composed of a single IC.

A light receiving diode 26 as a light receiving element that receives the infrared rays 18 sent out from the encoder is installed at the input section of the receiving circuit unit 22. When the light-receiving diode 26 receives infrared light a18, its internal resistance decreases and a light-receiving current flows through the resistor 28. This light-receiving current causes a voltage drop representing data in the resistor 28, and this voltage drop becomes intermittent in correspondence with the sent pulse data, resulting in a pulse voltage.

This pulse voltage is applied to the receiving circuit unit 2 as an input signal.
After being amplified by an input stage amplifier 220 installed at the front stage of the signal generator 2, the signal is detected by a detection circuit 221. After this detection output is waveformed through the waveform shaping circuit 222,
It is applied from the receiving circuit unit 22 to the decoder unit 24.

Receiving circuit unit 2 added to decoder unit 24
The output signal No. 2 is applied to the demodulation circuit 242, and the carrier signal is read out from the memory 243 and subjected to demodulation processing corresponding to the modulation processing in the encoder unit 12.

Then, the data code, which is the demodulated signal, is applied to a parity check circuit 244 as an error detection means to detect errors in the data code.

This data code error detection is performed by storing all the data codes sent out in advance in the memory 243 and their parities P, and after comparing and determining both each data code and the parity P, it is determined that there are no errors. If so, only that data code is applied to the decoding circuit 245.

The decoding circuit 245 decodes the data code to read control data representing a specific remote operation from the memo IJ 243, and outputs the read control data to the output circuit 246.
Add to. Therefore, the output circuit 246 distributes signals representing control data to the output terminals 01, 02, . . .
The signal is output from ON to the control microcomputer on the main circuit side of the JA device, and the necessary remote control is realized according to the remote control data from the encoder.

Since the number of bits including the parity P of this sent data is small and the data length is short, it is possible to narrow down the memory 243 storage area and reduce power loss on the decoder side as well. The recognition accuracy of the data obtained is improved, and quick and reliable remote control is obtained.

Although the embodiments have been explained using remote control of devices such as TVs and VTRs, the parity generation method of the present invention can be used to detect errors in various data, and is suitable for remote control. It is not limited.

〔Effect of the invention〕

As explained above, according to the present invention, parity is formed based on the bits of the part obtained by dividing the number of data bits into N, so the number of parity bits is reduced. The number of bits of data is reduced, the degree of redundancy is reduced, and the accuracy of data is improved. Moreover, the data length is shortened, and the amount of data in the recording/tα means is reduced and the storage area is narrowed.
Furthermore, by reducing the data length, power consumption is reduced.
Effects such as longer battery life when powered by batteries can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the parity generation method of the present invention, FIG. 2 is a flowchart showing the parity generation method in the block diagram shown in FIG. 1, and FIG. 3 is a diagram showing the data structure of one word. , FIG. 4 is a block diagram showing an encoder which is a specific embodiment of the parity generation method of the present invention, FIG. 5 is a diagram showing a one-word data code sent from the encoder of FIG. 4, and FIG. is a diagram showing the logic pulses of the data code shown in FIG. 5, FIG. 7 is a block diagram showing a decoder that decodes the data code sent from the encoder shown in FIG. 4, and FIG. 8 is a diagram showing the conventional parity code. FIG. 2... Parity calculation means, 4... Storage means. Figure 1

Claims (1)

[Claims] Divide the number of bits of data having an arbitrary number of bits into N,
Part Di obtained by division (=D_1.D_2・
... D_N) any part in Ds (S=1, 2...
・N), part 2 excluding part Ds from part Di
If the base addition value is X, find the parity p from p=Ds+nX (where n is an integer), and calculate the number of bits of the parity p for each part Di
A parity generation method characterized in that the parity is set equal to the number of bits.