JPS6365254B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit used to extract each information bit of information sent by packet transmission, and in particular to a clock pulse generation circuit that automatically adjusts the phase of each information bit of packet transmission information. The present invention relates to a clock pulse generation circuit that generates synchronized clock pulses.

Packet transmission improves transmission accuracy and transmission efficiency by transmitting various types of information in blocks. For example, in character information transmission television systems, it is used to transmit character signals (including graphics). . In this case, the text information transmission television system multiplexes text signals onto multiple lines during the vertical retrace period of the television signal and performs packet transmission, and on the receiving side, the text is sent by packet transmission. In this system, the character signals that are received are sequentially written into a memory, and the contents of this memory are read out in synchronization with the horizontal and vertical deflection cycles to be displayed on a television receiver. and,
This text information is, for example, multiplexed on the 20th and 22nd lines, and the color television signal on which this text information is multiplexed has the configuration shown in FIG. 1, for example. That is, it is determined that, for example, a 296-bit character signal CS is sent following the horizontal synchronizing signal HS and color burst signal CB.
This character signal CS is the running reference signal RI.
and information data ID, and is a running reference signal.
RI is 2.86MHz as shown in the enlarged diagram in Figure 2.
It is composed of 16-bit pulses, and the information data ID is a signal expressed by the non-return-to-zero method (NRZ) with a bit rate of 5.73 MHz synchronized with the pulse period of the running reference signal RI.

Therefore, when receiving a character signal CS configured as described above, a clock pulse generation circuit is provided inside the character information receiver to generate a clock pulse whose phase and rate match each bit of the received character signal CS. Each information bit of the information data ID is extracted by sampling the received character signal CS using a clock pulse. In this case, the clock pulse generation circuit is an oscillation circuit that maintains oscillation for approximately one horizontal scanning period by using the 2.86 MHz running reference signal RI extracted from the received character signal CS as an input signal and performing pull-in oscillation. is used to match the phase and rate of the clock pulses generated thereby to each bit of the received character signal CS.

However, the clock pulse generation circuit with the above configuration uses an oscillation circuit that continues to oscillate by being drawn in by the running reference signal RI sent only at the beginning of the character signal CS. The problem is that the generated clock pulses become unstable over time.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a clock pulse generation circuit that stably and accurately generates clock pulses synchronized with a running reference signal located at the beginning of a packet-transmitted signal. Hereinafter, a clock pulse generation circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of a clock pulse generation circuit according to the present invention. In the same figure, 1
is an amplifier circuit that amplifies the television signal A supplied from a tuner (not shown) and supplies it to the character signal sampling circuit 2 and the synchronous separation circuit 3. The synchronization separation circuit 3 extracts the vertical synchronization signal VS and the horizontal synchronization signal HS included in the television signal supplied from the amplifier circuit 1 using a generally known method and supplies them to the character signal sampling control circuit 4. . The character signal extraction control circuit 4 counts the horizontal synchronization signal HS based on the vertical synchronization signal VS supplied from the synchronization separation circuit 3 to extract, for example, the 20th and 22nd lines in which the character signal is multiplexed. A sampling control signal B is supplied to the character signal sampling circuit 2. Therefore, the character signal sampling circuit 2
is a character signal by extracting the output signal of the amplifier circuit 1 only during the generation period of the sampling control signal B.
CS is taken out. Reference numeral 5 denotes an AND gate which receives the horizontal synchronization signal HS and sampling control signal B, and reference numeral 6 designates a first mono-multivibrator circuit that is triggered by the output of the AND gate 5. A time constant is determined so as to generate an output signal C having a time width including up to the end of the run-in reference signal RI included in the signal CS. Reference numeral 7 denotes an AND gate which receives the output signal C and the character signal CS, and extracts the running reference signal RI in the character signal CS.
Reference numeral 8 denotes a second mono multivibrator circuit that is triggered only once by the first rise of the running reference signal RI generated from the AND gate 7, and the period from the trigger time to the end of generation of the running reference signal RI. A time constant is determined so that the output signal D is generated at the time. 9 is a character signal
A voltage controlled oscillator that generates a synchronized clock pulse CP with a bit rate that is 1/2 of the bit rate of CS; 10 is a frequency dividing circuit that divides the frequency of the clock pulse CP generated from the voltage controlled oscillator 9 by two;
11 is a phase for generating a pulse-like signal corresponding to the phase difference between the running reference signal RI of the character signal CS supplied to the input terminal IN ₁ and the output signal E of the frequency dividing circuit ₁₀ supplied to the input terminal IN 2. It is a comparison circuit, and the fourth
As shown in Figures a and b, if the running reference signal RI of the character signal CS supplied to the input terminal IN ₁ leads the output signal E in phase, the leading output terminal
From OUT ₁ , an output signal F whose phase difference portion is "L" is generated as shown in Figure 4 c, and the output signal G from the delayed output terminal OUT ₂ is in the "H" state as shown in Figure 4 d. Continue. In contrast, Fig. 5 a, b
Character signal CS supplied to input terminal IN ₁ as shown in
If the run-in reference signal RI is delayed with respect to the input signal E supplied to the input terminal IN ₂ , the output signal F generated from the leading output terminal OUT ₁ is as shown in Fig. 5c.
As shown in , the “H” state continues and the delayed output terminal
The output signal G generated from OUT ₂ is an output signal G whose phase difference portion is "L" as shown in FIG. 5d. 12 is a differential amplifier circuit,
It has a well-known circuit configuration consisting of an operational amplifier 15 which receives the output signals F and G of the phase comparator 11 as positive and negative inputs via resistors 13 and 14, respectively, and a feedback resistor 16 and a resistor 17.
18 is a level shift circuit that level-shifts the output signal H of the differential amplifier circuit 12 and sends it out as an output signal I; 19 is an output signal I of the level shift circuit 18;
20 is a sample hold circuit that samples and holds the output signal J of the low pass filter 19 at the falling edge of the output signal D of the second mono multi-circuit 8. This hold output signal K is then supplied to the voltage controlled oscillation circuit 9 as a control signal.

In the clock pulse generation circuit configured in this way, when a television signal A is supplied from a tuner circuit (not shown), the amplifier circuit 1 amplifies the television signal A and sends it to the character signal sampling circuit 2 and the sync separation circuit. Supply to 3. Then, the synchronization separation circuit 3 separates the vertical synchronization signal VS and horizontal synchronization signal HS contained in the television signal and sends them out. On the other hand, the character signal extraction control circuit 4 counts the horizontal synchronization signals HS based on the vertical synchronization signal VS supplied from the synchronization separation circuit 3, so that the character signal CS is multiplexed into the 20th,
The 22nd line is discriminated, and a sampling control circuit B is generated which becomes "H" only during the period of the 20th and 22nd lines, and is supplied to the character signal sampling circuit 2. Therefore,
The character signal sampling circuit 2 opens the gate only during the generation period of the sampling control signal B to extract the character signal CS shown in FIG. 6a.

On the other hand, the AND gate 5 determines whether the horizontal synchronization signal HS generated from the synchronization separation circuit 3 and the sampling control signal B match, and determines whether the character signal CS shown in FIG. The first mono-multivibrator circuit 6 is triggered by taking out the rising portion of the horizontal synchronizing signal HS located at . Therefore, this first monomultivibrator circuit 6 receives a horizontal synchronizing signal as shown in FIG. 6b.
Generates an output signal C that rises from the trailing edge of HS. As described above, this first mono multivibrator circuit 6 generates a running reference signal RI whose output signal C is included in the character signal CS.
The time constant is determined to be within the range of time points t ₁ to _{t 4} that sufficiently includes the generation period of the information data ID and does not reach the generation period of the information data ID. The output signal C of the first mono-multivibrator circuit 6 created in this way is used as a gate control signal by the AND gate 7.
, the running reference signal RI included in the character signal CS is extracted, and the second multivibrator circuit 8 is triggered only once at the leading edge of the first signal, and the output signal D is changed to the sixth This occurs as shown in Figure c. In this case, the generation period of the output signal D generated from the second multivibrator circuit 8 is a period from time t ₂ to time t ₃ within the generation period of the run-in reference signal RI.

On the other hand, the voltage controlled oscillator 9 oscillates a clock pulse CS used for sampling the information data ID included in the character signal CS. In this case, in order to sample the information data ID, a frequency twice as high as that of the running reference signal RI is required, and therefore the voltage controlled oscillator 9 has a frequency of 5.73 M
This means that it is oscillating at Hz. Then, the output signal of the voltage controlled oscillator 9 is frequency-divided by two in a frequency dividing circuit 10 for phase comparison to become an output signal E.

The output signal E of the frequency dividing circuit 10 generated in this manner is compared in phase with the run-in reference signal RI of the character signal CS supplied from the character signal sampling circuit 2 in the phase comparator 11. As explained above using FIGS.
When RI is in the leading phase, the pulse-like output signal F shown in _FIG .
The output signal G generated from OUT ₂ continues to be in the "H" state as shown in FIG. 4d. The output signals F and G of the phase comparator 11 generated in this way are outputted to the differential amplifier circuit 12 by the difference between the two signals as shown in FIG.
The output signal H is generated in the form of a positive pulse as shown in FIG. This output signal H is level-shifted in the level shift circuit 18 so that the voltage controlled oscillator 9 oscillates a signal with a frequency twice that of the running reference signal RI when the output signal is at zero level. The output signal I level-shifted in this manner is supplied to a low-pass filter 19, where it is converted into a direct current and output as an output signal J.
Therefore, as shown in FIG. 4f, this output signal J is equal to the output signal H generated from the differential amplifier circuit 12.
That is, the level corresponding to the phase difference between the running reference signal RI shown in FIG. 4a and the output signal E of the frequency dividing circuit 10 (FIG. 4b) that divides the output signal of the voltage controlled oscillator 9 by two. It becomes a change.

On the other hand, by inputting the output signal D generated from the second mono-multivibrator circuit 8 as a hold control signal, the sample and hold circuit 20 controls the output of the low-pass filter 19 during the "H" period of this output signal D. A phase lock loop is constructed by passing the signal J as it is and supplying the output signal K to the voltage controlled oscillator 9 as an oscillation frequency control signal. Therefore, the voltage controlled oscillator 9
In order to increase the oscillation frequency in response to the rise in the level of the output signal K, the phase of the output signal E of the frequency dividing circuit 10 is sequentially advanced as shown in FIG. 4B to match the running reference signal RI. For this reason, the pulse width of the output signal H generated from the differential amplifier circuit 12 becomes progressively narrower, and a zero level output continues to be generated when the phases match. Also,
The output signal J obtained by extracting the output signal H of the differential amplifier circuit 12 via the level shift circuit 18 and the low-pass filter 19 also fluctuated in accordance with the pulse width change of the output signal H, as shown in FIG. After that, as the phases of the two are matched, the shift level in the level shift circuit 18, that is, when the output signal H continues to be at zero level, the voltage controlled oscillator 9 oscillates a signal with a frequency twice that of the running reference signal RI. The control voltage required for

In this way, phase matching processing is performed by the phase lock loop, and the phases of the two coincide,
When the running reference signal RI approaches the end point, the output signal D output from the second mono multivibrator circuit 8 changes from "H" to "L" at time _t3 , as shown in FIG. 6c. Invert. In this way, when the output signal D as a hold control signal becomes "L", the sample and hold circuit 20
holds the output signal K shown in Fig. 6d at time _t3 , and the output level at this hold time is
By holding _VH and continuing to control the voltage controlled oscillator 9, the phase lock loop is brought into a locked state. Therefore, the trailing edge of the output signal D as a hold control signal may be used as long as it is the point at which the phase lock loop is stabilized and phase matching is completed, but in order to stabilize the control operation, the running reference signal It is a good idea to place it near the posterior edge of the RI.

By performing such an operation every time the running reference signal RI is supplied, the phase of the clock pulse CP is matched to the running reference signal RI.
If the run-in reference signal RI lags behind the output signal E of the frequency dividing circuit 10 as shown in _FIGS . As shown in FIG. 5c, the "H" state continues, and the output signal G generated from the delayed output terminal _OUT2 becomes a signal having a negative polarity pulse width corresponding to the phase difference, as shown in FIG. 5d. Therefore, the differential amplifier circuit 12 which receives both output signals F and G as input
The output signal H of is generated as a negative polarity signal, contrary to the case of FIG. 4e, and this negative polarity output signal H
After passing through the level shift circuit 18, the signal is converted into a direct current in the low-pass filter 19, and the phase of the voltage controlled oscillation circuit 9 is controlled in the delay direction to perform phase matching. When the phase alignment is completed, the output signal D as a hold control signal is inverted to "L" level near the end of the run-in reference signal RI, so that the frequency control signal for the voltage controlled oscillator 9 at that point in time is The phase lock loop is held by holding the output signal K to continue generating the phased clock pulse CP.

In the above embodiment, only the case where the hold control signal to be supplied to the sample and hold circuit is generated by the second mono multivibrator circuit which is triggered only once at the first rising edge of the running reference signal RI. Although described above, the present invention is not limited to this, and can be applied over a period including the start of supply of the run-in reference signal RI, after the time when the phase lock loop is stabilized, and until the run-in reference signal ends. It is fine as long as it is generated. Further, in the above embodiment, the case where the low-pass filter is provided after the level shift circuit 18 has been described, but it may be placed at any position as long as it is between the phase comparator and the sample hold circuit. Output end OUT ₁
A low-pass filter may be interposed between the output terminal OUT 2 and the resistor 13 and between the output terminal OUT ₂ and the resistor 14, respectively. Further, the voltage controlled oscillator 9 is connected to the differential amplifier circuit 1.
In the case where a clock pulse of a desired frequency is oscillated by the zero level output of No. 2, the level shift circuit 18 can be omitted. Furthermore, if the frequency of the generated clock pulse CP can be the same as the running reference signal, the frequency divider 10 can be removed.

As explained above, the clock pulse generation circuit according to the present invention has an extremely simple configuration, but can stably and accurately generate clock pulses synchronized with the run-in reference signal located at the beginning of information sent by packet transmission. It has excellent effects that can be generated.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram showing a television signal in which packet-transmitted character signals are multiplexed, FIG. 2 is an enlarged waveform diagram of the character signal shown in FIG. 1, and FIG. 3 is a diagram of a clock pulse generation circuit according to the present invention. The circuit diagrams illustrating one embodiment, FIGS. 4 a to f, FIGS. 5 a to d, and FIGS. 6 a to d are operation waveform diagrams of each part of the circuit diagram shown in FIG. 3. 1...Amplification circuit, 2...Character signal sampling circuit,
3... Synchronous separation circuit, 4... Character signal extraction control circuit, 5, 7... AND gate, 6, 8... First and second mono multivibrator circuit, 9... Voltage controlled oscillator, 10... Minutes cycle circuit, 11... phase comparison circuit, 12... differential amplifier circuit, 18... level shift circuit, 19... low pass filter, 20
...sample hold circuit.

Claims (1)

[Claims] 1 Compare the phase of the running reference signal located at the beginning of the information sent by packet transmission and the output signal of the voltage controlled oscillator provided for clock pulse generation, and divide the phase difference into lead and lag. A phase comparator generated from the first and second output terminals, a differential amplifier circuit that receives the output signals generated from the first and second output terminals of the phase comparator and outputs a phase difference component; a low-pass filter that converts the output of the dynamic amplifier circuit into direct current and generates a phase difference signal;
During the supply period of the hold control signal, which is generated during a period not exceeding the generation period of the run-in reference signal from the start of generation of the run-in reference signal, the phase difference signal is supplied to the voltage controlled oscillator, and the hold control signal is supplied to the voltage controlled oscillator. A clock pulse generator comprising: an air lock loop; and a sample and hold circuit that holds the phase difference signal at the trailing edge of the hold control signal and supplies it to the voltage controlled oscillator. circuit.