JPS6364798B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a raster scan type character display device having a display memory.

A character display device using a CRT (cathode ray tube) as the display section is often used in computer terminal devices, and an example of its configuration is shown in FIG. In this figure, 1 is a bus leading to the CPU (central processing unit), 2 is a display memory, 3 is a timing generation circuit, 4 is an address receiver and decoder, 5 is a data bus receiver and driver, 6 is a video signal generator, and 7 8 is a multiplexer, 8 is a CRT display, thick lines indicate data or address signal lines, and thin lines indicate control signal lines. to memory 2 via bus 1 and receiver 5
Character attribute information such as the code and underline of characters to be displayed is stored from the CPU, and the storage location is specified by an address signal sent from the CPU via the bus 1, receiver 4, and multiplexer 7 path. The timing generation circuit 3 generates a synchronization signal necessary for display on the CRT 8 and an address signal for the display memory 2, and the contents of the display memory 2, that is, character codes, etc., accessed by the address signal are input to the video signal generation section 6. , where it becomes a video signal showing patterns such as characters and is input to the CRT8,
Patterns such as letters are displayed on the screen. The timing generation circuit 3 also outputs data to the display memory 2.
The multiplexer 7 controls access from the CPU, and switches the address signal from the receiver 4 to the memory 2 and the address signal from the timing generation circuit 3 to the memory 2.

One of the main uses of such display devices is screen editing. In other words, inserting another line between certain lines on the character screen displayed on the CRT8 screen.
Delete a line, delete characters in a line,
The character screen is changed to a desired one by inserting other characters between certain characters in the line, and the screen is stored in memory or given to a printer to make a hard copy. As can be seen from the above explanation, such screen editing is often performed on a line basis. The present invention attempts to simplify this line editing management.

In the conventional method, there is a one-to-one correspondence between the display memory and the screen. Figure 2 illustrates this pattern.
2A is the memory content of display memory 2, 8A is the CRT
The display surface of the display 8 is shown. As shown in this figure, the memory 2 is filled with character groups in the first line, second line, etc. of the display surface in order. ADD is the address of the memory 2, M is the number of characters for one line, and N is the number of characters for one column. 41 ₁₆ , 42 ₁₆ ... indicate hexadecimal character codes. In such a display device, the screen is formed by sequentially reading out the memory 2 and arranging the read data sequentially on the display surface, so for example, to change the lines, it is necessary to change the stored contents of the corresponding part of the memory 2. For example, to swap the first and second rows of the display surface 8A, address 0 to memory 2
It is necessary to exchange the memory contents of M-1 and the memory contents of addresses M to 2M-1, and this exchange is
The CPU reads the contents of addresses 0 to 2M-1 of memory 2, writes the contents of 0 to M-1 to M to 2M-1, and writes the contents of M to 2M-1 to 0 to M-1, etc. This has the disadvantage that it requires processing, which puts a heavy burden on the CPU and slows down the display response speed.

The present invention does not require replacing memory contents.
It is intended to make it possible to easily change the CRT display contents, and its features include a display memory that stores a character code group and multiple display address points, and a display address that can be written to the memory. means for changing the point, means for generating an address in the display memory in which said address point is stored during blanking of each horizontal scan of the cathode ray tube of the display; During the display period following blanking, a counter performs counting starting from the address point to sequentially generate addresses in the display memory, and the character codes of the display memory sequentially read out by the output of the counter are sent to the cathode ray tube. and means for converting it into a video signal to be added. Next, this will be explained in detail with reference to examples.

3 and 4 show an embodiment of the invention.
The difference from FIG. 1 and FIG. 2 is that a counter 9 is provided and a display address pointer AP for each row is provided in the display memory 2. That is, in the present invention, a part of the display memory 2 is used as an address pointer, and in this part, the start addresses ADR ₁ , ADR ₂ , . . . of the storage area that accommodates the character code group of each line are stored.
Write... The writing order is the display order on the display surface 8A. In this example, pointer AP of display memory 2
Character code groups 41 ₁₆ to 4M ₁₆ are displayed on the first line with a slight interval from the storage area, and character code groups 51 16 to _{4M 16} are displayed on the second line after a slight interval.
It is assumed that 5M ₁₆ is further stored with a group of character codes displayed on the Nth line at intervals,
In such a case, the start addresses ADR ₁ , ADR ₂ . . . ADR _N of each row are written in the pointer AP section in row order. This memory 2 is written by a CPU (not shown),
Although the contents are variable, as will be explained below, line shuffling, scrolling up and down, etc. can be performed by leaving the character code storage area of the memory 2 unchanged and modifying only the address pointer AP.

To explain the operation, it is assumed that data has been written to the display memory 2 via the CPU bus ₁ etc. as shown in FIG. An address signal for accessing the first address ADD 0 of the address pointer to the memory 2 through the multiplexer is sent during the horizontal blanking period of the CRT. Memory 2 receives this and writes the first row address.
Outputs ADR ₁ , which passes through line l ₂ to counter 9
loaded into. Although not shown, a clock is input to the counter 9, and when ADR ₁ is loaded, a count value incremented by 1 is output every time a clock is input thereafter.
This goes through the multiplexer to memory 2,
Address of the memory ADR ₁ , ADR ₁ +1, ADR ₁
+2... are accessed sequentially (here, ADR ₁ +
There are some not shown, such as 2, but they are simply extensions.) The resulting character code is 41 ₁₆ ,
42 ₁₆ , 43 ₁₆ . . . are read out and input to the video signal generator 6 to output character pattern signals corresponding to these character codes. The timing at which the character pattern signal is input to the CRT 8 is of course synchronized with the start of horizontal scanning following horizontal blanking, and the signal corresponding to the end of one line is set at the end of one horizontal scanning. Also, since one character is drawn using multiple horizontal scanning lines, the same process is repeated multiple times. Of course, the first scan is the first horizontal line segment of the character pattern, the second
In the second scanning, the signal generating section 6 outputs a character pattern signal so that the second horizontal line segment . . . is drawn, and the details thereof are as known.

When entering the second line display, the timing generation circuit 3 issues a signal to access the address ADD 1 of the address pointer portion of the memory 2 again during the horizontal blanking period. This causes ADR ₂ to be read and loaded into counter 9. After that, the counter will be sequentially incremented by 1, so the character code 51 will be stored from memory 2.
₁₆ , 52 ₁₆ , 53 ₁₆ ... are read out and the display screen 8A
is displayed on the second line. The same applies below.

Since this display is structured as described above, it is easy to perform line swapping, etc. For example, the first
To swap rows with the second row, use the address pointer
AP's ADD 0 with ADR ₂ and ADD 1 with ADR ₁
All you have to do is write . In the conventional system shown in FIGS. 1 and 2, the character codes are written into the memory 2 in the display order, and the character codes are simply read out and displayed in order. It is necessary to completely replace the line character code group. All of this is done according to instructions from the CPU, and if the CPU has not saved the memory contents, it reads the first line character code group and stores it in the buffer, then reads the second line character code group and stores the first line character code in the memory. Operations such as writing to the row character code group storage location and further writing the first row character code group in the buffer to the second row character code group storage location of the memory are required, which is complicated.

This display allows you to easily scroll. For example, move the character group b ₁ , b ₂ ... b _n of the second line to the first line of the display screen, and move the character group a ₁ , a ₂ ... of the first line.
...a _n is deleted and the second line is blank, address pointer AP ADD 0
All you have to do is write ADR ₂ and write the address of the storage area where one line's entire text is filled with blank code to ADD 1. It is easy to scroll up or down all lines on the display screen 8A, for example, ADD 0 to N-2 of address pointer AP ADR ₂
If you write ~ADR _N , the whole thing will scroll up one line and go to address pointer ADD 1~N-1.
If you write ADR ₁ to _{ADR N-1} , the entire screen will scroll down by one line. To scroll to the left or right, write the address ADR ₁ to ADR _N to the address pointer +
1 or -1 etc. is sufficient.

As explained above, according to the present invention, the operation of changing raster scan type character display line by line can be executed extremely easily and quickly without putting a burden on the CPU, and is extremely effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the outline of a conventional display device, FIG. 2 is an explanatory diagram of the contents stored in its memory, and FIGS. 3 and 4 show an embodiment of the present invention. FIG. 2 is a block diagram and an explanatory diagram similar to that of FIG. In the drawing, 41, _16, etc. are character codes, AP is an address pointer, 2 is a display memory, 1 to 5, 7 are means for reading and writing to memory, 8 is a CRT, 3 is a means for generating an address, 9 is a counter, 6 is a video signal generator.

Claims (1)

[Claims] 1 a display memory for storing a character code group and a plurality of display address points; means for writing to said memory to change the display address points; Means for generating an address of a display memory in which a point is stored; the address point read by the address is loaded, and during the display period following horizontal blanking, counting starts from the address point; A raster scan type character display device comprising: a counter that sequentially generates addresses; and means for converting character codes sequentially read out from a display memory by the output of the counter into a video signal to be applied to the cathode ray tube.