JPS6362747B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a small-sized display device, and more particularly to a small-sized display device that displays gradations.

[Prior art]

A conventionally known liquid crystal display device is illustrated in FIGS. 1, 2, and 3. FIG. 1 is a cross-sectional view of a display panel portion of a known liquid crystal display device, and the surface of the display panel is protected by a transparent protective glass 1. As shown in FIG. This protective glass 1 often has the properties of an optical filter and is also used to prevent deterioration of the liquid crystal material.
A thin linear polarizing film 2 is placed under the protective glass 1, and the linear polarizing film 2 is pressed between the transparent upper electrode glass 3 and the protective glass 1.
An upper electrode 4 is baked onto the lower surface of the upper electrode glass 3. In addition, transparent lower electrode glass 8
A lower electrode 7 as shown in FIG. 3 is also baked into the lower electrode. The upper electrode 4 has a relatively simple undivided pattern, and a connecting member 6 is placed to lead out the upper electrode 4 onto the glass 8 for the lower electrode. Both the upper electrode 4 and the lower electrode 7 are formed by baking a thin layer of transparent conductive material. This is commonly called the Nesa membrane. A liquid crystal material is injected into the gap between these upper and lower electrodes. In order to prevent this liquid crystal from flowing out or deteriorating in quality, the outer periphery of the gap is tightly sealed with a sealing member 5. 9 is the same linear polarizing film as 2, and 10 is a lower substrate glass. A metal film 11 made of aluminum or the like is deposited on the back surface of the lower substrate glass 10, and light incident from above is reflected by this metal film 11 and returns. The display principle of this display panel is already well known and will not be described in detail, but the liquid crystal material rotates incident light when a suitable electric field is generated between the upper and lower electrodes. Therefore, if the polarization angles of the upper and lower linear polarizing films 2 and 9 are made the same, the incident light will be reflected as it is in the part where no electric field is applied between the upper and lower electrodes, but if an electric field is applied between the upper and lower electrodes, the incident light will be Since the light is rotated by the liquid crystal substance along the way, it cannot pass through the linear polarizing film 9 below and is absorbed, causing that part to appear black. FIG. 2 is a plan view of the liquid crystal display panel of FIG. 1, in which the upper electrode 4 is taken out from the lead terminal 13 and each part of the lower electrode 9 is taken out from the lead terminal group 12.

FIG. 3 shows an example of the pattern of the lower electrode 9,
When a number is displayed with seven elements, one number is displayed by combining seven types of patterns consisting of a number forming part 14, a drawer part 15, and a part 16 connecting to a lead terminal.

As described above, in the well-known liquid crystal display device, it is necessary to take out a large number of lead terminal groups, and when displaying a complicated pattern, the number of lead terminals becomes extremely large, making miniaturization impossible.

Furthermore, in such a structure, it is not easy to display gradations, and in particular, it is difficult to display multiple gradations such as television images.

〔the purpose〕

The present invention overcomes the above problems, and
An object of the present invention is to provide a small-sized display device that can realize multi-gradation display by arbitrarily selecting the voltage level applied to a display according to a display signal.

〔Example〕

FIG. 4 shows a conceptual diagram of a display body with a plurality of electrode arrays arranged in a matrix. Each pixel electrode 28 is formed of a film of a conductive material, such as aluminum, and has a flat surface so as to reflect light. Further, signal holding means 29 and 3 temporarily store a display signal for applying an electric field to the pixel electrode 28.
There is a first prize. The signal holding means 29, 31 are shift registers in this embodiment. Furthermore, signal transmitting sections 30 and 31 are formed in order to apply display signals from the signal holding means 29 and 31 and the like to the reflecting section 28 using timing signals to be described later. That is, one pixel electrode 2
8 is combined with one signal holding means 29 and one signal transmission section 30 to form one display island. Terminals 33 and 34 are connected to the shift register 29,
31 and the input terminal of the power supply supplied to the signal transmission sections 30 and 32. 35 is a display signal input terminal;
36 is an input terminal for the clock signal of the shift registers 29 and 31, and 37 is a terminal from the signal transmission section to the pixel electrode 28.
This is an input terminal for a display clock signal that determines the timing of supplying a signal potential to the terminal.

FIG. 5 shows an example of a signal holding means and a signal transmitting section that belong to one display island when displaying in four levels of brightness and darkness. 81 is a terminal for supplying a high potential, 82 is a terminal for supplying a middle-high potential, 83 is a terminal for supplying a middle-low potential, and 84 is a terminal for supplying a low potential. Both the high potential and the low potential are connected to shift registers 65, 69, and 7, which are signal holding means.
3, 77 and signal transmission sections 66, 70, 74, 7
It is supplied as a power source for 8. Furthermore, these four levels of potential are applied to the transmission gates 68 and 7, respectively.
2, 76, and 80 are added as inputs. 8
5, 88, 89, 90 are each shift register 6
5, 69, 73, 77 are input terminals for display signals, 86 is an input terminal for clock signals,
87 is an input terminal for a display clock signal. The display signals input to the input terminals 85, 88, 89, and 90 will be described later based on FIG.

A clock signal transfers each register output to the output of the next shift register. 92 is an output line of the shift register, which is connected to the next stage. When the signal transfer to the shift registers of all the display islands is completed, the display clock signal is applied to the terminal 87, and each signal transmission member transfers the output of the paired shift registers to the transmission gates 68, 72, 76, 80. here 6
7, 71, 75, and 79 are inverters for inverting signals. Since only one of the four shift registers is at a high potential, the transmission gate supplies the input potential only to the output terminal 91 corresponding to the shift register at the high potential. This allows you to select one of the four levels of brightness and darkness.
Two potentials are generated at the output terminal 91 and supplied to the pixel electrode.

Figure 6 shows the state of each signal mentioned above.
FIG. 7 shows an example of what is displayed. 93 is a display clock signal, 94 is a high potential series display signal, 95
96 is a display signal of medium and low potential series, 97 is a display signal of low potential series, and 98 is a clock signal. If such a signal is used for display using the circuit shown in FIG. 5 and 18 display electrodes, a pattern as shown in FIG. 7 will be obtained. In other words, the dark area is 99, the medium dark area is 100, and the medium bright area is 10.
1. A bright area 102 is obtained. That is, in the case where one screen consists of 18 display electrodes, within the display clock timing period, the display signal 94 that controls the timing of applying high voltage to the electrodes is sent to the input terminal 85 in FIG. 5, and the display signal 94 is sent to the input terminal 88. , a display signal 95 that controls the timing of applying medium-high voltage, and an input terminal 8
A display signal 96 for controlling the timing of applying a medium-low voltage is input to the input terminal 90, and a display signal 97 for controlling the timing of applying the low voltage is input to the input terminal 90 at the timing of the clock signal 98. , 69, 73, 77.
Next, at the timing of the display clock signal 93, the display signals 94, 95, 96, 97 held in each shift register 65, 69, 73, 77 are sent to the signal transmission section 66, 70, 74, 78, and the signal Display signals 94, 9 from transmission units 66, 70, 74, 78
According to the instructions of 5, 96, 97, high, medium high, medium low,
One of the low potentials is selected and supplied to the electrode 91.

FIG. 8 is an overall block diagram for driving the small-sized display device of the present invention.

The function of each component in FIG. 8 will be explained with reference to the signal waveform diagram in FIG. 9. The video signal received by antenna 105 passes through well-known amplifier 106, mixer 107, intermediate frequency amplifier 109, video detector 110, and amplifier 111. In addition, the mixer 107
is the signal from local oscillator 108 and amplifier 106
A beat signal is generated by the received signal from the intermediate frequency amplifier 109, and is input to the intermediate frequency amplifier 109. Among these, the audio component passes through an audio amplifier 112, an FM detector 113, and an amplifier 114, and is outputted from a speaker 115.

On the other hand, in the synchronization signal separator 116, a vertical synchronization signal 126 and a horizontal synchronization signal 127 are separated from the composite video signal 128 from the amplifier 111. Furthermore, only the vertical synchronizing signal 126 is extracted from the vertical synchronizing signal generator 117 and supplied to the display section 122 as a display clock signal, and the horizontal synchronizing signal 126 is extracted from the horizontal synchronizing signal generator 118.
Only 7 is taken out. The horizontal synchronization signal 127 is
It is input to clock pulse generator 119. A clock pulse 131 is generated from the clock pulse generation circuit 119, and a clock pulse 131 is generated from the clock pulse generation circuit 119, and the clock pulse 131 is
20.

Next, the composite video signal 128 from the amplifier 111
is supplied to the comparison circuit 120. Comparison circuit 12
At 0, the voltage level of the portion of the composite video signal 128 that contributes to the video signal is equal to the clock pulse 12.
The comparison circuit 12 outputs a step pulse 130 which is sampled at the timing of 9 and compared with the reference level of 16 steps, and which is synchronized with the timing of the clock pulse.
Output from 0. This staged pulse 130 is input to the display signal generator 121, and is classified and separated into each of 16 levels. The display signal generator 121 generates display signals 132-147 according to each level of the classified and separated stage pulses. These display signals 132 to 147 are output as pulses corresponding to a specific level of 16 levels when the stepped pulse reaches that level. For example, signal 132 is a signal corresponding to a black level, and signal 147 is a signal corresponding to a white level. be. Therefore, display signal generator 121 supplies parallel display signals 132 to 147 corresponding to 16 stages to display device 122 via signal transmission bus 125. Display device 1
22 basically has a structure in which a signal holding means 29, a signal transmitting section 30, and an electrode 28 are arranged in a matrix as shown in FIG. Therefore, in FIG. 4, terminal 35 is supplied with parallel display signals 132-147, terminal 36 is supplied with clock pulse 131, and terminal 37 is supplied with clock pulse 131.
A display clock signal 126 is provided to the display clock signal 126. Further, the signal holding means 29 stores the display signals 132 to 1
47, each pixel electrode is composed of 16 shift registers, and the signal transmission section 30 also has a similar structure. In addition, the power input terminal 33 in FIG.
34, 16 voltage levels are provided to 16 transmission gates per pixel in display 122. The transmission gate is substantially the same as the configuration explained in FIG. 5 in that it is opened and closed according to the output signal from the signal transmission section, selects one of 16 levels, and supplies it to the pixel. be. In this way, a voltage level corresponding to the gradation is supplied to each pixel, making it possible to display gradations on the entire screen. In this way, a very small and thin television set can be made. The display materials used for this, such as liquid crystals such as PLZT, can display brightness and darkness with just a few volts, and the power consumption is as small as a few microwatts, making it possible to create unique display devices.

〔effect〕

As described above, the present invention comprises a transparent upper flat plate, a transparent electrode provided in the upper flat plate, a lower flat plate opposed to the upper flat plate with a suitable gap left, and electrodes arranged in a matrix on the lower flat plate. In a small display device comprising a plurality of pixel electrodes and a substance whose chemical or physical properties change depending on an electric field is sealed in the gap, a video signal is compared with a plurality of reference voltage levels, and the image is detected. Display signal generation means for generating a display signal corresponding to the peak value of the signal; signal holding means for holding the plurality of types of display signals for one scanning period of the video signal; and a display clock generated at the timing of each scanning. and a voltage applying means for selecting one level from a plurality of voltage levels prepared in advance based on the display signal output from the signal holding means and applying it to the pixel electrode. It is possible to supply a gradation signal corresponding to the amplitude level of a video signal to a plurality of pixel electrodes, and therefore it is possible to provide a compact display device that realizes a small and thin planar moving image display.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of the display panel of a conventionally known liquid crystal display device. 1... Protective glass, 2, 9... Linear polarizing film, 3... Glass for upper electrode, 4... Upper electrode, 7... Lower electrode,
8... Lower electrode glass, 10... Lower substrate glass. FIG. 2 is a plan view of the display panel of FIG. 1. FIG. 3 shows an example of the pattern of the lower electrode 9. FIG. 4 is a plan view of the small display device of the present invention. 17... Protective glass, 18... Circular polarizing film, 19... Flat plate for upper electrode, 20... Upper electrode, 23... Output lead terminal, 24... Multiple islands serving as pattern elements, 2
5...Lower flat plate, 26...Substrate. FIG. 5 shows an example of a shift register section and a signal transmission section of the present invention. 81, 82, 83, 84...4
Terminals for supplying stage potentials, 73, 77...shift register, 66, 70, 74, 78...signal transmission unit, 67, 71, 75, 79...inverter, 6
8, 72, 76, 80...transmission gate. FIG. 6 is a signal waveform diagram in the circuit of FIG. 5. 93...Display clock signal, 94...High potential series input signal, 95...Mid-high potential series input signal, 96
...Input signal of medium and low potential series, 97...Input signal of low potential series, 98...Clock signal. FIG. 7 is a pattern displayed with the signal of FIG. FIG. 8 is an overall block diagram of the small-sized display device of the present invention. 105...Antenna, 106...Radio frequency amplifier,
107...Mixer, 108...Local oscillator, 109...
Video intermediate frequency amplifier, 110...Video detector, 11
1...Video amplifier, 112...Audio intermediate frequency amplifier,
113...Frequency conversion FM detector, 114...Audio amplifier, 115...Speaker, 116...Synchronization signal separator, 117...Vertical synchronization signal generator, 118...Horizontal synchronization signal generator, 119...Clock pulse generator, 120...Comparison circuit , 121...Display signal generator, 122...Small display device. FIG. 9 is a signal waveform diagram in each block of the small display device of FIG. 8. 126...Output of vertical synchronization signal generator, 127...
Output during horizontal synchronization signal generation period, 128... video signal,
129...Comparison timing signal, 130...Comparison circuit output, 131...Clock signal, 132-147...
Gray level signal.

Claims (1)

[Claims] 1. A transparent upper flat plate, a transparent electrode provided in the upper flat plate, a lower flat plate opposed to the upper flat plate with a suitable gap left, and a plurality of pixel electrodes arranged in a matrix on the lower flat plate. , in a small display device in which a substance whose chemical or physical properties change depending on an electric field is sealed in the gap, the video signal is compared with a plurality of reference voltage levels,
Display signal generating means for generating a display signal corresponding to the peak value of the video signal, signal holding means for holding the plurality of types of display signals for a single screen scanning period of the video signal, and timing for each single screen scanning period. the voltage applying means selects one level from a plurality of voltage levels prepared in advance based on the display signal output from the signal holding means and applies it to the pixel electrode using a display clock generated by the signal holding means; A small display device characterized in that a holding means and a voltage applying means are provided for each pixel electrode on a lower flat plate.