JPS6361380A - Image processor - Google Patents

Abstract

PURPOSE:To facilitate the enlargement and reduction of an optional magnification by controlling a data writing to a memory means, executing the reducing action of data, controlling the data reading and executing the enlarging action of the data. CONSTITUTION:An analog image signal from a CCD 30 is inputted through an analog signal processing circuit 31 to an A/D converter 32, converted to a digital image signal, thereafter, the signal is given to a variable power processing circuit 33 housing an image consecutive processing. The variable power processing circuit 33 executes the reducing action of image data by controlling the data writing to a RAM 36, and executes the enlarging action of the image data by controlling the reading of the image data stored in the RAM 36.

Description

[Detailed Description of the Invention] [Technical Field] The present invention provides, for example, a method for converting a document into a line image display using a CCD or the like.
The present invention relates to an image processing device that processes image signals obtained by reading using a sensor.

[Prior art]

Using a CCD with a reading area smaller than the original, -
2. Description of the Related Art A serial scan type image reading apparatus is known that reads an image of the entire surface of a document by moving the reading area in the sub-scanning direction for each main scan.

FIG. 9 is a diagram for explaining the operation of the serial scan method.

The COD image sensor 1 that performs line reading is connected to a main scanning drive system (not shown) that performs scanning in the main scanning direction from the home position HP shown in the drawing in the order of the arrows shown in the drawing, and a sub-scanning drive system (not shown) that also performs scanning in the sub-scanning direction. The scanning drive system scans the reading area RA. Images are sequentially output in the order of scans ① to ①, and the entire reading area is read.

In order to perform image scaling processing such as reducing or enlarging an image with such an image reading device, there is a mechanical method that varies the scanning speed in the main scanning direction, and an electric method that thins out the image data and increases the amount of data in the CCD scanning direction. The common method is to change the magnification.

If the number of image data in the CCD scanning direction is variable and the CCD photocharge accumulation time is constant and continuous, for example, to perform a 50% reduction, the main scanning feed speed is doubled and the CCD The reduction operation can be performed by thinning out the image data in the scanning direction at a rate of one for every two pixels. Conversely, in the case of 200% enlargement, the main scanning feed speed is halved and the image data in the CCD scanning direction is padded at a rate of 2 per pixel.

At magnifications with well-defined boundaries such as 50% and 200%, image stitching at the boundaries between scans ■ and ■ is relatively easy; Processing becomes very complicated. Furthermore, when image processing such as smoothing processing is performed after scaling processing, extra image data must be sent, making such image joining processing during scaling even more complicated.

FIG. 1O is a diagram for explaining image stitching processing when changing the magnification.

The upper part of FIG. 10 shows the state of the reading line when looking at the reading area in the CCD scanning direction (=sub-scanning direction) of FIG. 9, that is, the state of the output pixel at the same magnification. In the figure, a, b, c, and d indicate pixels related to image connection between the first scan and the 1+1th scan. In this example, smoothing processing using a 3×3 matrix is performed. It is assumed that this is done in a subsequent circuit.゛The lower part of Fig. 10 shows an example of the state of the output pixel when the image is enlarged by 150%. a', a'', b' in the figure.

c/, c#, and dN correspond to pixels a, b, c, and d, respectively, when the inflated enlargement process is performed to 150%.

In this example, when magnifying 150%, a/ , a# '+ b', C/ , C
/ pixel #, br, in 1+1st scan
It is necessary to output pixels of C/, C#, and dN. Further, depending on the number of pixels of the CCD image sensor 1 and the magnification, images may not be connected in the same way every time, and it is necessary to retain information regarding thinning and padding of images.

FIG. 11 is an example of a conventional electrical scaling circuit that thins out and pads image data.

Input image data is stored in random access memory RA
The image data is written alternately to RAM 13 and 15, and the reduction operation is performed by thinning out the image data at that time.
An enlargement operation is performed by padding the image data when reading from l 3 and 15, and is sent to the next stage circuit as output image data.

A D-type flip-flop (DFF) 10 is a circuit for latching input image data, and the data is latched using the image clock WRCK that is also sent.

A decade rate multiplier (DRM) 11 thins out the image clock ~'/RCK and generates a clock WRCM for reduction. DRMII is a standard TTL circuit such as TI's 5N74167, and is a binary coded code such as 99.55.
A decimal (BCD) value is set to the data input terminal (thereby, a clock WRCM thinned out according to the value can be obtained.The 5N74167 cannot pass the image clock WRCK through, so an external circuit is required. The synchronizing signal WR3T is a signal for synchronizing each line, and when this signal becomes low level, DRM1
1. The built-in counter is cleared and the image clock WRCK is thinned out in a pattern similar to that of a lifetime scan.

The counter 12 is a counter for generating a write address of the RAM 13.15, and for example, the synchronization signal W
Following R3T, the count value is sequentially incremented from the value O.

The DFF 18 is a circuit for selecting and latching data read out from the RAM 13.15 by the selector 17, and latches the data using an external image clock RDCK.

The binary rate multiplier (BRM) 19 is
The image clock RDCK is thinned out to generate a clock RDCM for enlarging. BRM19 is a standard TTL circuit like TI's 5N7497.
By setting binary data values such as FF and 955 (hexadecimal number) to the data input terminal, a clock RDCM thinned out according to the value can be obtained. Since the 5N7497 cannot pass the image clock RDCK through, an external circuit is added to prevent the enlarging operation.

The synchronization signal RDST is a signal for synchronizing each I line, and when this signal becomes low level, the BR
The built-in counter of M19 is cleared and the image clock RDCK is thinned out in a pattern similar to that of a lifetime scan.

The counter 20 is a counter for generating read addresses for the RAMs 13 and 15, and for example, successively increments the count value from 0 following the synchronization signal RDST.

The RAM 13.15 is a memory for writing and reading image data in accordance with the write address of the counter 12 and the read address of the counter 2o selected by the selector 14.16. A so-called double buffer configuration is adopted in which a read operation is performed in one RAM while a write operation is performed in the other RAM.

In order to perform accurate image stitching as explained in FIG. 10 with the conventional circuit configuration described above, it is necessary to
It is necessary to match the outputs of the built-in counters of RM 12 and B RM 19, and it is not only necessary to simply clear the counters, but also to preset the counter values, read the counter values at the transition positions, etc., and grasp accurate data regarding magnification. Therefore, the circuit becomes large and complex.

Further, in order to perform image data writing and reading operations at arbitrary timings after inputting the synchronization signals WR3T and RDST, it is necessary to add a circuit as well.

〔the purpose〕

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned conventional drawbacks and to provide an image processing device that can perform enlargement and reduction operations at arbitrary magnifications and easily connect image data to obtain good image signals. be.

〔Example〕

Hereinafter, the present invention will be explained in detail based on examples.

FIG. 1 is an example of a control block diagram of a serial scan type image reading device to which the present invention is applicable.

The CCD 30 corresponds to the CCD image sensor 1 and is an image sensor that performs line reading.

The analog image signal output from the CCD 30 is sent to an analog signal processing circuit, where it undergoes processing such as shading correction, noise component removal, and amplification, and then is sent to the next stage analog-to-digital converter (A/D converter). Sent to 32.

The analog image signal is converted into a digital image signal by the A/D converter 32, and sent to a variable magnification processing circuit 33 that includes image stitching processing.

The magnification processing circuit 33 not only performs magnification processing and image stitching, but also performs the CCD 3 input to the magnification processing circuit 33.
It also generates a plurality of timing signals A1 related to 0 and a plurality of timing signals B related to output image data that is subjected to scaling and image splicing processing and output.

Upon receiving the timing signal A, the CCD driver 34
This is a driver circuit that generates a signal to drive D30.

The CPU 35 is, for example, a microcomputer that controls the entire image reading device. The control program is stored in a read-only memory (ROM) 38, and the CPU 35 uses a random access memory (RAM) 36, which is used for temporary storage of data, to start and stop the reading operation. An operation unit 39 that performs operations such as specifying magnification, a main scanning drive circuit 37 that controls movement of the CCD 30 in the main scanning direction, a sub-scanning drive circuit 40 that controls movement of the CCD 30 in the sub-scanning direction, and a variable magnification circuit 33 control.

FIG. 2 shows an example of a specific configuration of the variable magnification circuit 33 shown in FIG.

First, the circuit that performs the reduction process will be explained.

The DFF 51 is a circuit for latching input image data, and latches the data using the image clock WRCK that is also sent.

The counter 52 is a counter for generating a read address of the RAM 54, and for example, the synchronization signal W RS
Following T, the count value is sequentially incremented from the value O.

The selector 53 receives the address signal of the RAM 54, and
This is a switching circuit for switching the control signal to either the CPU 35 or the counter 52. Usually counter 5
2 side is selected so that the timing stored in the RAM 54 can be read out, and only when the contents of the RAM 54 are to be changed, the process is switched to the CPU 35 side.

The RAM 54 is a memory for storing a plurality of timings regarding the image clock WRCK according to the address signal generated by the counter 52. Timing information set in advance by the CPU 35 is output as a timing signal A in synchronization with the synchronization signal WR3T.

One signal of timing signal A', V RE B
The signal is from RAM58. The clock signal ~V of the counter 57 that generates the write address signal given to RA~160
This is a signal for generating RCU.

DFF55. OR gate 56 is a circuit for generating tarock signal WRCU from WREB signal. Further, the counter 57 is, for example, a counter that sequentially increments the count value from the value 0 following the synchronization signal WR3T.

Next, a circuit that performs enlargement processing will be explained.

The DFF 63 is a circuit for selecting and latching data read out from the RAM 58.60 by the selector 62, and latches the data using the external image clock RDCK.

The counter 64 is a counter for generating a read address of the RAM 66, and includes, for example, a synchronization signal RDST.
Subsequently, the count value is sequentially incremented from the value O.

The selector 65 receives the address signal of the RAM 66, and
This is a switching circuit for switching the control signal to either the CPU 35 or the counter 64. Usually counter 6
4 side is selected so that the timing stored in the RAM 66 can be read out, and only when changing the contents of the RAM 66, etc., the CPU 35 side is selected to perform processing.

The RAM 66 is a memory for storing a plurality of timings regarding the image clock RDCK according to the address signal generated by the counter 66. The timing information set in advance by the CPU 35 is the timing signal B.
is output in synchronization with the synchronization signal RDST.

The RDEB signal, which is one of the timing signals B, is
A clock signal R of the counter 69 that generates a read address signal to be applied to the RAM 58 and RAM 60.
This is a signal for generating DCU.

The DFF 67 and the OR gate 68 are circuits for generating the RDEB signal and the empty clock signal RDCU. Further, the counter 69 is, for example, a counter that sequentially increments the count value from the value O following the synchronization signal RDST.

RAM 58, 59 are the write address of the counter 57 selected by the selector 59.61, and the counter 69
It is a memory that writes and reads image data according to the read address of the memory, and has a double buffer structure similar to that shown in Fig. 11, in which one RAM performs a write operation while the other RAM performs a read operation. There is.

FIG. 3 shows synchronization signals WR3T, RDST, and W
This is an example of a timing chart of the RE B signal and the RDEB signal. In this example, it is assumed that the data at the same time is set, and the clock RD CK is set from the clock WRCK.
It is assumed that the frequency is high. For that purpose, R.D.
The EB signal section is a little shorter.

In this embodiment, timing is generated by reading from RAM, etc.
Since a writable memory is used, the W
It is possible to generate REB and RDEB signals.

FIG. 4 is a timing chart for explaining in detail the operation during reduction.

In FIG. 4, the broken line indicates the timing at 60% reduction.

The counter 52 is a standard TTL 5
It is a synchronous clear counter like the N74LS163, and when the synchronizing signal WR3T goes low, the count value is cleared from the value m to the value O as shown in the figure. The Q output counts at the rising edge of the clock W RCK.
Will be uploaded.

In this example, it is assumed that the W RE B signal has been written from address 1 of the RAM 54, and is read out sequentially as shown in the figure by the count signal of the counter 52, and the WREB*
The W RCU signal is generated as shown in the figure.

The counter 57 is a standard TTL 5
This is an asynchronous clear counter like the N74LS161, and when the synchronizing signal WR3T goes low, the count value is cleared to the value O as shown in the figure.

At the rising edge of clock WRCU, the Q output of counter 57 is counted up.

The clock WRCU can be used not only to count up the counter 57, but also as a write pulse when writing data to the RAM 58.60.

As you can see from Figure 7, 60% reduction is achieved by CPU3
This can be done by thinning out the WREB signal set at
The data of the RDEB signal set in AM66 is the same data.

FIG. 5 is a timing chart for explaining in detail the operation during enlargement.

In FIG. 5, the broken line indicates the timing of l 33 % enlargement.

The counter 64 is a synchronous clear counter such as TI's 5N74LSI63, which is a standard TTL, and when the synchronization signal RDST goes low level, the count value is cleared from the value n to the value O as shown in the figure. Ru. The Q output is counted up at the rising edge of the clock RD Ci.

In this example, the RDEB signal is assumed to have been written from address 1 of the RAM 66, and is read out sequentially as shown in the figure by the count signal of the counter 64, and the RDEB*
The RDCU signal and the RDCU signal are generated as shown in the figure.

The counter 69 is a standard TTL TI 5
This is an asynchronous clear counter like the N74LS161, and when the synchronizing signal RDST goes low, the count value is cleared to the value O as shown in the figure.

The Q output of counter 69 is counted up at the rising edge of clock RDCU.

As can be seen from Figure 5, the 133% expansion is due to the CPU
This can be done by thinning out the RDEB signal set at 35 at a rate of one every four pixels. In this case, the data of the WREB signal set in the RAM 54 is equal-sized data.

Next, a specific program example of the CPU 35 will be explained using a flow chart.

FIG. 6 is an example of a general flowchart of the CPU 35.

When the device is powered on, first step 5P
Initialize with 100. Next, in step 5 PIOI, the process waits until a reading start signal is input. When the reading start signal is input, in step 5P102, the CCD image sensor 1 is moved to the home position and reading of the original is started.

Document reading is executed by repeating one main scan and one sub-scan feed, and the scaling process during one main scan is controlled by setting the timing signal for scaling in the RAM 54.66 just before each raw scan. . Since the algorithm for setting the timing signal for zooming differs depending on whether the zooming is enlargement or reduction, the cases are divided in step 5P103, and the timing signal for zooming is set in step SP1.04. In step 5P105, a timing signal for scaling down is set. Thereafter, one main scan is performed in step 5P106, and one sub-scan feed is performed in step 5P107. In step 5ptos, it is determined whether the entire surface of the document has been read by repeating the above steps, and if Hiiragi is not read, step 5ptos
Return to 103.

On the other hand, if the process has been completed, the process moves to step 5 PIOI and waits again for reading a new document.

RAM at the time of magnification change performed in step 5P104 in Figure 6
The settings of 54 and 66 will be explained using detailed flowchart 1 in FIG.

In this flowchart, a timing signal is written to the RAM 54 in steps 5P200 to 5P201, and R is written in steps 5P202 to 5P218.
Write the timing signal to AM66.

In step 5P200, a timing signal A other than the WREB signal is written into the RAM 54.

In step 5P201, the number of image data to be sent to the subsequent circuit is called the "required number of pixels", and the RAM
The WREB signal is written from address 1 of 54 to address "required number of pixels". As a result, image data of "required number of pixels" is continuously stored in the RAM 58 or RAM 60 starting from the second image data in synchronization with the WR3T signal. This is equivalent to the setting for the RAM 54 at the same magnification.

RAM66 at step 5P202 to step 5P217
Write the RDEB signal to. The "address" given an initial value of 1 in step 5P202 is a variable representing the address of RA'M66. In step 5P203, an "error" at the upper boundary of the I CCD scan is set. This "error"
is a variable that calculates the difference between the magnification that should be realized and the actual magnification. The "error" at this upper boundary is O during the first main scan, and (n-
1) Use the "error" at the lower boundary of the second main scan. With this method, accurate image stitching can be achieved even during arbitrary enlargement and scaling.

In step 5P204, a counter ``output pixel count'' of the padded image data read out from the RAM 58 and RAM 60 by the RDCK clock, and a counter ``read pixel count'' of the image data required to create the ``output pixel count'' image data. Give an initial value O to "number". In the loop after step 5P205, image data is padded according to the "error". At the beginning of the n-th loop (immediately before step 5P205), the relationship is "error" = ("number of read pixels" x magnification ÷ 100 - "number of output pixels J) x 100. Adding a subscript n to this, , [error n
J = (Number of read pixels nJ X magnification - 100 - [Number of output pixels nJ) xlo.

It is written as. When this "error n" exceeds 100, padding is performed.

Due to the padding, the "error n+1" becomes [error n+IJ = (number of read pixels nJ X magnification ÷ 100 = (number of output pixels nJ +1)) Processing is step 5P209, step 5P212
It will be held in

On the other hand, when the "error n" is less than 100, the "number of read pixels" increases by 1 by writing the RDEB signal at the timing represented by the "address", so [error n + IJ
[Error n + IJ = ((Number of pixels read nJ + 1) X magnification ÷ 100 =
([Number of output pixels nJ +1)) xlooo - "error n"
+ (magnification -100). In the flowchart, this process is performed in step 5P206. Step 207. This is done in step 208.

Step 5P210. In step SP2]1, along with step 5P217, pixels to be padded over two adjacent main scans are processed.

At the beginning of main scanning, for the first pixel, there is an "error"
Although it is 100 or more, there are no pixels that should be increased before that, so the RDEB signal is written and the RA
It must be read from M58 and RAM60. Therefore, in step 5P210, it is checked whether it is the first pixel, and in step 5P211, step 5P2 is checked.
07, perform the same processing as step 5P208.

In steps SP2] and 3, the "address" is incremented by 1, and in the next loop, a quasi-1itf is performed to describe the new timing. In step 5P214, step S P 2 ], 2) In step 5P208, RAM6
Regardless of whether the RDEB signal is written to 6 or not, the "number of output pixels" is increased by 1.

In Step 5P215, check whether the "output pixel count" has reached the "required pixel count", and if it has not reached the "required pixel count", step 5
Return to P205. If it has been reached, the "number of read pixels" and "error" at the lower boundary are recorded in step 5P216. This "number of read pixels" becomes the feed amount for the next sub-scanning, and the "error" becomes the "error" of the upper boundary in the next main scan.

In step 5P217, it is checked whether the "error" is 100 or more, and if it is 100 or more, the pixel that was output immediately before must be output at the beginning of the next main scan. Therefore, the "number of read pixels", which is the feed amount for l sub-scanning after l main scanning is completed, is reduced by 1.

Finally, in step 5P218, RDE to RAM66
A timing signal B other than the B signal is written.

RA during reduction/magnification performed in step 5P105 in Figure 6
M54.

The settings of 66 will be explained using the detailed flowchart of FIG.

In this flowchart, a timing signal is written to the RAM 54 in steps 5P300 to 5P313, and R is written in steps 5P314 to 5P315.
A timing signal is written to AM66.

In step 5P300, W RE B to RAM M54
Timing signal A other than the signal is written.

RAM in step 5P301 to step 5P313
Write the WREB signal to 54. The "address" given an initial value of 1 in step 5P301 is a variable representing the address of the RAM 54.

In step 5P302, an "error" at the upper boundary of the ICCD scan is set. This "error" has the same meaning as the "error" in the enlargement settings. The "error" at the upper boundary is O during the first main scan, and the "error" at the lower boundary of the (n-1)th main scan is used for the n-th main scan. With this method, accurate image stitching can be achieved even during arbitrary reduction and scaling.

In step 5P303, RA, M 58 , RA
Give an initial value of 0 to the counter "Number of output pixels" for the thinned image data written to M60 and the counter "Number of read pixels" for the image data required to create "Number of output pixels" image data. . Step SP 3
In the loop after 0 = 1, image data is thinned out according to the "error". The beginning of the nth loop (step 5
Immediately before P304), there is a relationship such as "error J = (number of r output pixels" - "number of read pixels" X magnification + 100) X100. Add a subscript n to this and say “error nJ=
(r Output pixel number n” - “Reading pixel number n” x magnification - 100) It is written as X100. When this "error n" exceeds the magnification, thinning is performed.

Due to thinning, "error n+1" is "error n+IJ -= (r output pixel number n" - ("reading pixel number nJ +1) X magnification + 106) xto.

= "error n" - magnification, and decreases by the magnification bone. In the flowchart, this process includes steps 5P308 and 5P30.
It will be held at 9.

On the other hand, when the "error" is less than the magnification, by writing the WREB signal at the timing represented by "address", "
Since the number of output pixels increases by 1, the error n + IJ is: Error n + IJ = (M output pixel number nJ + 1) = ([Reading pixel number nJ + 1) X magnification - 1OO) xlO
O=[error nJ + (100-magnification)]. In the flowchart, this process is performed in step 5P305, step 306, and step 307.

In step S P 31.0, increase "address" by 1,
In the next loop, prepare to describe new timing. In step 5P311, step 5P307,
In step 5P309, the "number of read pixels" is incremented by 1 regardless of whether the WREB signal is written to the RAM 54 or not.

Step 5P312 checks whether the number of output pixels J has reached the required number of pixels, and if it has not, step 5
Return to P304. If it has been reached, the "number of read pixels" and "error" at the lower boundary are recorded in step 5P313. This "reading pixel number" becomes the feed flea for the next sub-scanning, and the "error" becomes the "error" of the upper boundary in the next main scanning.

In step S P 314, the RDEB signal is written from address 1 to the "required number of pixels" address in the RAM 66.

As a result, from the second timing in synchronization with the RDST signal, the "required number of pixels" image data is continuously stored in the RAM.
58 or RAM 60 to the subsequent circuit. This is equivalent to the setting for the RAM 66 at the same magnification.

Finally, in step 5P315, RDEB to RAM66
Timing signal B other than the signal is written.

In the above embodiment, R is used for temporary storage of image data.
For example, first in
Storage elements such as first-out memory can also be used.

If there are only a few types of magnifications to be used, store multiple pieces of magnification-related information in read-only memory (ROM), etc., and select the information in this ROM to create a data set of magnification information. You can use it instead.

〔effect〕

Second, according to the present invention, it has become possible to easily realize image stitching during scaling processing in a serial scan type image reading device.

Furthermore, the variable magnification circuit, which conventionally required a complicated circuit, can now be realized with a simple circuit configuration as described above.

Furthermore, since information regarding scaling can be managed by a CPU or the like, it is possible to easily perform image splicing processing and manage the amount of movement in the sub-scanning direction when scaling image data in the serial scan method, which has been difficult in the past.

[Brief explanation of the drawing]

FIG. 1 is a control block diagram of a serial scan type image reading device to which the present invention can be applied, FIG. 2 is a specific configuration diagram of a variable magnification circuit, and FIG. 3 is a diagram showing various types of circuits shown in the second diagram. 4 is a timing chart diagram showing the timing. FIG. 4 is a timing chart diagram for explaining in detail the operation during reduction. FIG. 5 is a timing chart diagram for explaining the operation during enlargement in detail. Figures 6 to 8 show the program flow of CPU35.
Chart diagram, Figure 9 is a diagram for explaining the operation of the serial scan method, Figure 1O is a diagram for explaining image stitching processing when changing the magnification, and Figure 11 is a diagram for explaining the operation of the conventional image data. FIG. 3 is a diagram illustrating an example of a variable magnification circuit using thinning and padding. In the figure, 30 is a CCD image sensor, 32 is A
/D converter, 33 is a scaling processing circuit, and 35 is a CPU. 36 is RAM, and 38 is ROM.

Claims (2)

[Claims] (1) A storage means for storing input image data, a write control circuit that performs a data reduction operation by controlling data writing to the storage means in synchronization with the input image data, and a readout of data stored in the storage means 1. An image processing device comprising a readout control circuit that enlarges image data by controlling the image data, and is capable of freely setting variable magnification processing at an arbitrary magnification. (2) Claim 1 is characterized in that the control information for writing data to and reading data from the storage means is stored in a readable/writable storage means, and the data can be rewritten. image processing device.