JPS6359425U - - Google Patents
Info
- Publication number
- JPS6359425U JPS6359425U JP15230186U JP15230186U JPS6359425U JP S6359425 U JPS6359425 U JP S6359425U JP 15230186 U JP15230186 U JP 15230186U JP 15230186 U JP15230186 U JP 15230186U JP S6359425 U JPS6359425 U JP S6359425U
- Authority
- JP
- Japan
- Prior art keywords
- matrix switch
- matrix
- circuit
- output buffer
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 3
Description
第１図はこの考案に係るマトリクススイツチ回
路の一実施例を示すブロツク図、第２図は第１図
の詳細なブロツク図、第３図は従来のマトリクス
スイツチ回路を示すブロツク図である。
１１〜１ｎ……入力端子、３１〜３ｍ……出力
端子、４１〜４ｌ……マトリクススイツチ、５…
…マトリクススイツチ素子、６……出力バツフア
、７……インターフエース回路、８……制御回路
、９１〜９ｌ……制御線。
FIG. 1 is a block diagram showing an embodiment of the matrix switch circuit according to this invention, FIG. 2 is a detailed block diagram of FIG. 1, and FIG. 3 is a block diagram showing a conventional matrix switch circuit. 1 1 to 1 n ...Input terminal, 3 1 to 3 m ... Output terminal, 4 1 to 4 l ... Matrix switch, 5...
... Matrix switch element, 6 ... Output buffer, 7 ... Interface circuit, 8 ... Control circuit, 9 1 - 9 l ... Control line.
Claims (1)
イツチ素子、出力バツフアおよびインターフエー
ス回路から構成され、並列に接続された複数個の
マトリクススイツチと、この複数個のマトリクス
スイツチを選択的に動作また非動作に制御する制
御回路とを備えたマトリクススイツチ回路。 It consists of a matrix switch element consisting of n inputs and m outputs, an output buffer, and an interface circuit, and is composed of a plurality of matrix switches connected in parallel. A matrix switch circuit equipped with a control circuit that controls the operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986152301U JP2510088Y2 (en) | 1986-10-03 | 1986-10-03 | Matrix switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986152301U JP2510088Y2 (en) | 1986-10-03 | 1986-10-03 | Matrix switch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6359425U true JPS6359425U (en) | 1988-04-20 |
| JP2510088Y2 JP2510088Y2 (en) | 1996-09-11 |
Family
ID=31070155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986152301U Expired - Lifetime JP2510088Y2 (en) | 1986-10-03 | 1986-10-03 | Matrix switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2510088Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828434U (en) * | 1981-08-20 | 1983-02-24 | 日本電気株式会社 | Signal switching circuit |
| JPS60180292A (en) * | 1984-02-27 | 1985-09-14 | Nippon Telegr & Teleph Corp <Ntt> | Space switch |
-
1986
- 1986-10-03 JP JP1986152301U patent/JP2510088Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5828434U (en) * | 1981-08-20 | 1983-02-24 | 日本電気株式会社 | Signal switching circuit |
| JPS60180292A (en) * | 1984-02-27 | 1985-09-14 | Nippon Telegr & Teleph Corp <Ntt> | Space switch |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2510088Y2 (en) | 1996-09-11 |