JPS6359264A - Image input device - Google Patents

Image input device

Info

Publication number
JPS6359264A
JPS6359264A JP61203097A JP20309786A JPS6359264A JP S6359264 A JPS6359264 A JP S6359264A JP 61203097 A JP61203097 A JP 61203097A JP 20309786 A JP20309786 A JP 20309786A JP S6359264 A JPS6359264 A JP S6359264A
Authority
JP
Japan
Prior art keywords
logic
control signal
coordinate
signal
read mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61203097A
Other languages
Japanese (ja)
Inventor
Hiroto Sato
佐藤 洋人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61203097A priority Critical patent/JPS6359264A/en
Publication of JPS6359264A publication Critical patent/JPS6359264A/en
Pending legal-status Critical Current

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  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To accurately and rapidly switch and to execute a processing suitable for a character area or a photographing area, by providing a coordinate counter, and a read mode storing memory, and reading out the content of the read mode storing memory by the content of the coordinate counter. CONSTITUTION:The coordinate counter 10 inputs a clock which controls the scan of a photoelectric scanner 1, and a horizontal and a vertical synchronizing signals, and generates the coordinate position of a point on an original being scanned by the photoelectric scanner 1 at present, from those synchronizing signals. In the read mode storing memory 11, a signal logic to be outputted as a control signal 7 is stored corresponding to the position coordinate. In other words, in the read mode storing memory, the logic '0' or '1' of the control signal 7 is set in advance corresponding to the content of the coordinate counter. For example, the logic '0' is written for the bit of the character area 31, and the logic '1' is written for the bit of the photographing area 32. And the above logic is read out by the content of the coordinate counter 10, thereby, a gate circuit is controlled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は画像原稿中の文字領域に対しては白と黒の2
値データ化し、写真領域に対しては濃淡情報を表わすこ
とのできる擬似階調データ化する画像入力装置に関する
ものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention provides two types of white and black text for character areas in image originals.
The present invention relates to an image input device that converts value data into pseudo gradation data that can represent gradation information for photographic areas.

〔従来の技術〕[Conventional technology]

第2図はこの種の装置の従来の構成を示すブロック図で
、図において(1)は光磁スキャナ、(2)は2値デー
タ化回路、(3)は擬似階調データ化回路、(4)は文
字データ信号(すなわち、白黒の2値データ信号)、(
5)は写真データ信号(すなわち擬似階調データ信号)
、!61は読取りモード制御回路、(7)は制御信号、
(8)は画像信号、(9)は画俄処理装置、(41) 
、 (51) 、 (71) 、 (81)はそれぞれ
論理ゲートである。
FIG. 2 is a block diagram showing the conventional configuration of this type of device, in which (1) is a magneto-optical scanner, (2) is a binary data converting circuit, (3) is a pseudo gradation data converting circuit, ( 4) is a character data signal (i.e., black and white binary data signal), (
5) is a photo data signal (i.e. pseudo gradation data signal)
,! 61 is a read mode control circuit, (7) is a control signal,
(8) is an image signal, (9) is an image processing device, (41)
, (51), (71), and (81) are logic gates, respectively.

第3図は第2図の回路で読取られる画像原稿を示す説明
図で、(30)は原稿、(31)は文字エリヤ、(32
)は写真エリヤである。原稿(30)から読取った情報
から原稿を再生する場合、文字エリヤ(31)では一画
素(1ドツト)に対し、それが白であるか黒であるかの
2値データ(1ビツトの信号)を記憶しておれば足りる
が、写真エリヤ(32)に対しては濃淡情報を残してお
くことが希望されるので白と黒との間に所定段階の中間
濃度を入れた擬似階調データとして記憶しておく。すな
わち、擬似階調データでは一画素をnビット(但しnは
2以上の整数)で表わさねばならぬ。たとえば、n=2
とすると白(00) 、  白に近い灰色(01)、黒
に近い灰色(10)、及び黒(11)の4段階で写真エ
リヤ(32)の濃淡を表わすことができる。
FIG. 3 is an explanatory diagram showing an image original read by the circuit shown in FIG. 2, where (30) is the original, (31) is the character area, and (32)
) is a photo of Elijah. When reproducing a document from information read from the document (30), binary data (1 bit signal) indicating whether it is white or black is generated for each pixel (1 dot) in the character area (31). It is sufficient to memorize the gradation information for the photo area (32), but it is desired to retain the gradation information for the photo area (32), so it is stored as pseudo gradation data with a predetermined intermediate density between white and black. Remember it. That is, in pseudo gradation data, one pixel must be represented by n bits (where n is an integer of 2 or more). For example, n=2
Then, the shading of the photo area (32) can be expressed in four stages: white (00), gray close to white (01), gray close to black (10), and black (11).

光電スキャナ(1)は読取り対象の画像原稿(図示せず
)を走査して、その走査点の反射光の強さを電気信号に
変換し、アナログ信号を発生する。このアナログ信号が
2値データ化回路(2)に入力されてlサンプル点1ビ
ツトの2値信号に変換され、擬似階調データ化回路(2
)に入力されて1サンプル点nビットのディジタル信号
に変換される。
A photoelectric scanner (1) scans an image original (not shown) to be read, converts the intensity of reflected light at a scanning point into an electrical signal, and generates an analog signal. This analog signal is input to the binary data converting circuit (2), where it is converted into a binary signal with 1 sample point and 1 bit.
) and is converted into a digital signal of n bits per sample point.

読取りモード制御回路(6)は、たとえば、文字の原稿
を読取るのか、又は写真の原稿を読取るのかに従ってプ
ロセッサ等から発せられるコマンドにより制御され、制
御信号(7)の論理を「0」又は「1」に制御する。制
御信号(7)の論理が「0」のときは文字データ信号(
5)が画像信号(8)となり、制御信号(7)の論理が
「1」のときは写真データ信号(5)が画像信号(8)
となる。
The reading mode control circuit (6) is controlled by a command issued from a processor or the like depending on whether, for example, a text original or a photographic original is to be read, and sets the logic of the control signal (7) to "0" or "1". ”. When the logic of the control signal (7) is "0", the character data signal (
5) becomes the image signal (8), and when the logic of the control signal (7) is "1", the photo data signal (5) becomes the image signal (8)
becomes.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上のような従来の装置では読取りモード制御回路(6
)にコマンドを与える手段の構成が複雑なものとなり、
文字エリヤ(31)と写真エリヤ(32)とが入り組ん
で存在する画像原稿に対しては、迅速かつ正確にコマン
ドを出力することが困難であるという問題点があった。
In the conventional device as described above, the read mode control circuit (6
) has a complicated structure,
There has been a problem in that it is difficult to quickly and accurately output commands for image originals in which a text area (31) and a photographic area (32) are complicated.

この発明は上記のような問題点を解決するためになされ
たもので、文字エリヤ(31)と写真エリヤ(32)と
が複雑に入り組んでいる画像原稿に対しても正確迅速に
ゲート回路(41)、(51)。
This invention was made in order to solve the above-mentioned problems, and the gate circuit (41) can be accurately and quickly applied even to image originals in which the character area (31) and the photo area (32) are intricately intertwined. ), (51).

(71)、(81)を制御することのできる画像入力装
置を得ることを目的としている。
The object of the present invention is to obtain an image input device that can control (71) and (81).

〔問題点を解決するための手段〕[Means for solving problems]

この発明では座標計数器と読取リモート記憶メモリとを
設け、座標計数器には光電スキャナの走査の同期信号か
ら現時点で光電スキャナが画像原稿上のどの点を走査し
ているかを表わす座標位置を計数し、読取りモード記憶
メモリには座標計数器の内容に対応して制御信号(7)
の論理を「0」にするか「1」にするかをあらかじめ記
憶しておき、座標計数器の内容によって読取りモード記
憶メモリの内容を読出すことにした。
In this invention, a coordinate counter and a reading remote storage memory are provided, and the coordinate counter counts the coordinate position representing which point on the image document is currently being scanned by the photoelectric scanner from the scanning synchronization signal of the photoelectric scanner. The read mode storage memory stores a control signal (7) corresponding to the contents of the coordinate counter.
It was decided to store in advance whether the logic of is set to ``0'' or ``1'', and read out the contents of the read mode storage memory according to the contents of the coordinate counter.

〔作用〕[Effect]

この発明では制御信号を読取りモード記憶メモリから読
出すだけの操作をすればよいので正確迅速な制御が可能
になる。
In the present invention, since it is only necessary to read the control signal from the read mode storage memory, accurate and quick control is possible.

〔実施例〕〔Example〕

以下この発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第1図はこの発明の一実施例を示すブロック図で、第1
図において第2図と同一符号は同−又は相当部分を示し
、第2図の場合と同様な動作をするので重複した説明は
省略する。(10)は座標計数器、(11)は読取りモ
ード記憶メモリである。
FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same reference numerals as in FIG. 2 indicate the same or corresponding parts, and since the operations are similar to those in FIG. 2, redundant explanation will be omitted. (10) is a coordinate counter, and (11) is a reading mode storage memory.

座標計数器(10)は元屯スキャナ(1)の走査を制御
するクロック及び水平同期、垂直同期の同期信号(この
明細書ではこれらを総称して同期信号という)を入力し
て、これら同期信号から現時点で光電スキャナ+11が
走査している原稿上の点の位置座標(X # yの直角
座標上の数値とする)を発生する。読取りモード記憶メ
モリ(11)にはこの位置座標に対応して制御信号(7
)として出力すべき信号論理を記憶する。この記憶は第
3図に示すような簡単な原稿に対してはy□くyくy2
かつXユくx (X2  であれば論理「1」を出力し
、それ以外は論理「0」を出力するという簡単なメモリ
でもよく、又は光゛電スキャナ(1)の走査範囲のすべ
ての画素に対し1画素1ビットのメモリを備え、文字エ
リヤ(31)のビットに対しては論理「0」を書込み、
写真エリヤ(32)のビットに対しては論理「1」を書
込んでおいてもよい。これが座標計数器(lO)の内容
によって読出されてゲート回路(51) 、(71)、
(41)、(81)を制御する。
The coordinate counter (10) inputs the clock that controls the scanning of the Yuantun scanner (1) and synchronization signals for horizontal synchronization and vertical synchronization (in this specification, these are collectively referred to as synchronization signals), and receives these synchronization signals. The positional coordinates (assumed to be numerical values on the rectangular coordinates of X # y) of the point on the document currently being scanned by the photoelectric scanner +11 are generated from . A control signal (7) is stored in the reading mode storage memory (11) corresponding to this position coordinate.
) is stored as the signal logic to be output. This memory is y□kuykuy2 for a simple manuscript as shown in Figure 3.
And, it may be a simple memory that outputs logic ``1'' if X2 and outputs logic ``0'' otherwise It has a memory of 1 bit per pixel, and writes logic "0" to the bit of the character area (31).
Logic "1" may be written to the bit of the photo area (32). This is read out by the contents of the coordinate counter (lO) and sent to the gate circuits (51), (71),
(41) and (81) are controlled.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、文字エリヤと写真エリ
ヤが混在した原稿に対しても文字エリヤ及び写真エリヤ
に対してそれぞれ好適な処理が正確迅速に切換えて実行
される。
As described above, according to the present invention, even for a document in which text areas and photo areas coexist, suitable processes can be accurately and quickly switched and executed for the text areas and photo areas, respectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すブロック図、第2図
は従来の装置を示すブロック図、第3図は読取り対象と
なる画像原稿の一例を示す説明図。 (1)は光柩スキャナ、(2)は2値データ化回路、(
3;は擬似階調データ化回路、(41) 、 (51)
 、 (71)。 (81)はゲート回路、(10)は座標計数器、(11
)は読取りモード記憶メモリ。 尚、各図中同一符号は同−又は相当部分を示す。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional apparatus, and FIG. 3 is an explanatory diagram showing an example of an image original to be read. (1) is a light coffin scanner, (2) is a binary data conversion circuit, (
3; is a pseudo gradation data conversion circuit, (41), (51)
, (71). (81) is a gate circuit, (10) is a coordinate counter, (11
) is read mode storage memory. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】 読取り対象の画像原稿を走査しこの画像原稿上の各部の
反射光の強さを電気信号に変換する光電スキャナ、 この光電スキャナの出力を2値のディジタル信号に変換
する2値データ化回路、 上記光電スキャナの出力を、1画素の反射強度がnビッ
ト(但しnは2以上の整数)のディジタル信号で表わさ
れるように変換する擬似階調データ化回路、 制御信号の論理が「0」のときは上記2値データ化回路
の出力を選択し、制御信号の論理が「1」のときは上記
擬似階調データ化回路の出力を選択するゲート回路、 上記光電スキャナから同期信号を入力して、上記画像原
稿上で上記光電スキャナが走査している座標位置を計数
する座標計数器、 この座標計数器の内容の座標位置に対応して上記制御信
号の論理を記憶する読取りモード記憶メモリ、 この読取りモード記憶メモリの内容を設定する手段、 上記座標位置計数器の内容により上記読取りモード記憶
メモリを読出して上記ゲート回路への制御信号として出
力する手段、 を備えたことを特徴とする画像入力装置。
[Scope of Claims] A photoelectric scanner that scans an image original to be read and converts the intensity of reflected light from each part of the image original into an electrical signal; 2 that converts the output of this photoelectric scanner into a binary digital signal; A value data conversion circuit, a pseudo gradation data conversion circuit that converts the output of the photoelectric scanner so that the reflection intensity of one pixel is represented by an n-bit digital signal (where n is an integer of 2 or more), and control signal logic. a gate circuit that selects the output of the binary data converting circuit when the control signal is "0" and selects the output of the pseudo gradation data converting circuit when the logic of the control signal is "1"; and a gate circuit that is synchronized from the photoelectric scanner. a coordinate counter that inputs a signal and counts the coordinate position scanned by the photoelectric scanner on the image document; a reader that stores the logic of the control signal in correspondence with the coordinate position of the contents of the coordinate counter; A mode storage memory, means for setting the contents of the read mode storage memory, and means for reading the read mode storage memory according to the contents of the coordinate position counter and outputting it as a control signal to the gate circuit. image input device.
JP61203097A 1986-08-29 1986-08-29 Image input device Pending JPS6359264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61203097A JPS6359264A (en) 1986-08-29 1986-08-29 Image input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61203097A JPS6359264A (en) 1986-08-29 1986-08-29 Image input device

Publications (1)

Publication Number Publication Date
JPS6359264A true JPS6359264A (en) 1988-03-15

Family

ID=16468327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61203097A Pending JPS6359264A (en) 1986-08-29 1986-08-29 Image input device

Country Status (1)

Country Link
JP (1) JPS6359264A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136995A (en) * 1991-10-30 1993-06-01 Samsung Electron Co Ltd Simple binary-coding and false halftone mixture processing method and device for image data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136995A (en) * 1991-10-30 1993-06-01 Samsung Electron Co Ltd Simple binary-coding and false halftone mixture processing method and device for image data

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