JPS6354882A - Image pickup camera for still picture - Google Patents

Abstract

PURPOSE:To require no mechanical type shutter and to comparatively simplify a constitution by providing a shutter timing signal forming circuit, a shutter control circuit and a timing generating part. CONSTITUTION:A control part 7 is provided with an oscillation circuit 13 for generating a reference clock making the transfer time of one picture element of a horizontal transfer part 11 a cycle, the shutter timing signal forming circuit 15 for forming the shutter timing signal based on a vertical synchronizing signal clock from a frequency dividing circuit 14 and a shutter time T applied from an EE control part 5, the shutter control circuit 16 for outputting a shutter opening signal and the timing generating part 17 for generating transfer pulses Pi, Ps, Pt and a clear pulse Cp. The signal charge of a CCD image pickup part 9 is cleared synchronously with the shutter opening signal by the clear pulse and a period from the clear of the signal charge of the CCD image pickup part to the output of the transfer pulse in response to the vertical synchronizing signal after the elapse of the shutter time is the storage time of the signal charge, namely an exposure time. Thereby, the mechanical type shutter is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a still image capturing camera using a frame transfer type CCD solid-state image sensor.

<Prior art and its problems> The shutter section of conventional still image imaging cameras of this type consists of a lens shutter that performs exposure by opening and closing several shutter blades (sectors), or a thin film directly in front of the image forming surface. All kinds of mechanical shutters, such as a four-force shutter, are used to expose the image through a slit. These mechanical shutters expose the CCD solid-state image sensor.

It is necessary to match the transfer drive timing and the shutter timing, which requires a device for this purpose, resulting in a complicated structure and high cost. The object of the present invention is to provide a still image capturing camera that does not require a mechanical shutter, has a relatively simple configuration, and is low in cost.

<Configuration and Effects of the Invention> In order to achieve the above-mentioned object, the present invention provides a still image imaging camera equipped with a frame transfer type CCD solid-state imaging device having a CCD imaging section, a CCD storage section, and a horizontal transfer section. Based on the clock corresponding to the synchronization signal and the set shutter time, the period is longer than the shutter time, and is the time obtained by subtracting the shutter time from the smallest integral multiple of the vertical synchronization period. a shutter timing signal that forms a shutter timing signal whose period is a period of the integral multiple of the vertical synchronization signal, whose level becomes a level corresponding to shutter opening, and maintains that level over the shutter time; a shutter control circuit that outputs a shutter open signal over a period corresponding to the shutter time based on the shutter timing signal and the release signal; and a shutter control circuit that outputs a shutter open signal over a period corresponding to the shutter time; generates a clear pulse for clearing the signal charges of the CCD imaging section by transferring one field's worth of signal charges of the CCD imaging section to the CCD storage section; and transfers the signal charges of the CCD imaging section to the CCD storage section. output of transfer pulses other than the clear pulse is prohibited, and in a period other than the period of the shutter open signal, one field worth of signal charge of the CCD imaging section is transferred to the CCD storage section in response to the vertical synchronization signal. and a timing generator that outputs a transfer pulse.

According to the above configuration, the signal charge of the CCD imaging section is cleared by a clear pulse in synchronization with the shutter open signal formed based on the shutter timing signal, and the signal charge of the CCD imaging section is cleared after the shutter time has passed since the signal charge of the CCD imaging section is cleared. Since the period until the output of the transfer pulse in response to the vertical synchronization signal is equal to the accumulation time of the signal charge, that is, the exposure time, there is no need for a conventional mechanical shutter.
It is no longer necessary to match the drive timing of the CCD solid-state image pickup device with the shutter timing, making the configuration simpler than the conventional example and making it possible to reduce costs. Furthermore, by forming a shutter timing signal corresponding to an arbitrary shutter time, it becomes possible to freely set the shutter period.

<Description of Examples> Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic diagram of an embodiment of the present invention. In the figure, 1 is a photographing lens, 2 is a condensing lens, and 3
4 is a diaphragm, and 4 is a light receiving element for photometry. 5 is a BE control unit that adjusts the aperture 3 when setting the shutter time T based on the output of the photometric light receiving element 4; 6 is a CCD solid-state image sensor; Part 7 1st. Second. Third transfer pulses Pi, Ps, P
L and a clear pulse Cp, which will be described later, are applied. The control section 7 is given a release signal corresponding to the operation of the shutter button. The output of the CCD solid-state image sensor 6 is given to a control section 7 and subjected to predetermined signal processing, and then given to an image recording section 8 as a video signal to be recorded. Further, the image recording section 8 is given a signal indicating the output timing of the image signal from the control section 7.

FIG. 2 is a block diagram of the CCD solid-state image sensor 6 and control section 7 shown in FIG. 1, and FIG. 3 is a time chart thereof. The CCD solid-state imaging probe 6 includes a CCD imaging unit 9, C
This is a frame transfer type image sensor having a CDCC storage section and a horizontal transfer section (horizontal not register) II. CCD! The most image section 9 transfers signal charges for one horizontal scanning line to the COD storage section 1O in response to one pulse input of the first transfer pulse Pi from the timing generation section 17 of the control section 7. The COD storage section 10 receives the second transfer pulse Ps from the timing generation section 17! The signal charges for l horizontal scanning lines are transferred to the horizontal transfer section 11 by pulse manual power. The horizontal transfer section 11 outputs signal charges for one pixel to the analog gate 12 of the control section 7 in response to one pulse input of the third transfer pulse Pt from the timing generation section 17 .

The control unit 7 basically includes an oscillation circuit 1 that generates a reference clock whose period is the transfer time of one pixel of the horizontal transfer unit 11.
3, a frequency dividing circuit 14 which divides the frequency of this reference clock to form a vertical synchronizing signal clock having a period of 1/60 seconds shown in FIG. 3(A) corresponding to the vertical synchronizing signal; A shutter timing signal forming circuit 15 that forms a shutter timing signal shown in FIG. The shutter control circuit 16 outputs the shutter open signal shown in FIG. 3(D) based on the release signal shown in FIG. 3(C), and the shutter open signal, the vertical synchronization signal clock, and the reference clock. Based on the above, the first . Second. It includes a timing generating section 17 that generates each of the third transfer pulses Pi, Ps, and Pt and a clear pulse Cp.

The shutter timing signal forming circuit 15 is shown in FIG. 3(A).
Based on the vertical synchronization signal clock and shutter time T shown in FIG. In the embodiment, the high level signal rises with a delay from the vertical synchronization signal clock by a time T2, which is obtained by subtracting the on-screen shutter time T from the period (3 times the vertical synchronization period), and continues over the shutter time T, corresponding to the shutter opening. t
A shutter timing signal as shown in FIG. 3(B) having a period equal to the period TI (a period three times the vertical synchronization period) which is an integer multiple of the above-mentioned integer times the vertical synchronization period during which the signal is maintained is generated. The purpose of forming such a shutter timing signal is to match the shutter opening timing, that is, the fall timing of the shutter timing signal, with the vertical synchronization signal clock. This ensures smooth transfer of signal charges after exposure. It will be held in

As shown in FIG. 11, this shutter timing signal forming circuit 15 generates a natural number N (=0.1, 2.3...
), and the integer value N+1, which is obtained by adding 1 to this natural number N, is multiplied by 1/60 seconds, which is a period longer than the above-mentioned shutter time T, and which has a vertical synchronization period (
A multiplier 19 calculates a period TI that is a minimum integral multiple of 1/60 seconds), and a shutter time T from this calculated period TI.
and a subtracter 20 for subtracting . Based on the output T2 of this subtracter 20 and the vertical synchronization signal clock, the third
The shutter timing signal shown in FIG. 3(B) is formed and output to the shutter control circuit 16.

The shutter control circuit 16 generates a shutter open signal as shown in FIG. 3 during a period when the release signal shown in FIG. Output as shown in (D). This shutter open signal is generated by the timing generator 1.
7 and the gate signal forming circuit 21. The gate signal forming circuit 21 is also given a vertical synchronizing signal clock, and based on these, it outputs the gate signal shown in FIG. do.

The timing generator 17 is further supplied with a vertical synchronization signal clock from the frequency divider circuit 14 and a reference clock from the oscillation circuit 13 . This timing generation wJ17 is based on these inputs as shown in FIG.
G). Second. Third transfer pulse Pi, P
s and Pt, and also generates a clear pulse Cp and applies it to the CCD solid-state image sensor 6.

This timing generator 17 outputs the first transfer pulse Pi and the second transfer pulse Ps in synchronization with the vertical synchronization signal, and outputs the third transfer pulse Pt during a period in which the shutter open signal is not applied. has been done. The first one synchronized with this vertical synchronization signal. second transfer pulse Pi,
Ps is output in a number equal to the number of vertical stages of the CCDCD imaging section (=the number of vertical stages of the CCD storage section IO). The first of these.
Assuming that the accumulated signal charges for one field of 1 field are transferred to the flat CCD storage section IO of the CCDCD imaging section by the second transfer nodal crosses Pi and Ps, the signal charges of the COD storage section IO are horizontally transferred. The information is transferred to section 11.

Thereafter, signal charges corresponding to l horizontal scanning lines in the COD storage 110 are sequentially transferred to the horizontal transfer section 11 by a second transfer pulse Ps output in synchronization with the horizontal synchronization signal. The signal charges transferred to the horizontal transfer section 11 are output pixel by pixel to the analog gate 12 by the third transfer pulse pt, which is output in the same number as the number of pixels constituting one horizontal scanning line during the horizontal scanning period. .

Next, when the timing generator 17 receives the shutter open signal, it synchronizes with the shutter open signal and generates a
XF ), the signal charges for the flat field of the CCDCD imaging section are transferred to the COD storage section IO and are stored in the CC
A clear pulse Cp is generated to clear the DCD imaging section flat charge, and this clear pulse Cp is applied to the CCD CD imaging section flat charge and the CCD storage section 10. This allows the CCD
The signal charge for the flat field of the CD imaging unit is stored in the COD storage unit l.
It is transferred to COD storage unit 1 and cleared.
A signal charge of 0 is transferred to the horizontal transfer section 11.

Furthermore, during the period in which this shutter open signal is given, the output of transfer pulses for transferring the normal charge of the CCDCD imaging section to the COD storage section IO is prohibited, except for the clear pulse Cp, and thereby the shutter open signal From the clearing of the signal charge of the CCD imaging element by the clear pulse synchronized with the falling of the shutter open signal, that is, the first vertical synchronization signal clock synchronized with the first. Second transfer pulse Pi, P
The signal charge is accumulated over the period A of the output of s. This accumulation period A! J<exposure period, that is, shutter time. Note that during this exposure period A, the second
．． The third transfer pulses Ps and Pt are output in the same manner as described above.

At this time, the CCDCD imaging unit was installed.
The signal charge for one field is the first signal charge synchronized with the vertical synchronization signal. The signal is transferred to the COD storage section 10 by the second transfer pulses Pi and Ps, and is outputted from the horizontal transfer section 11 to the analog gate 12 during the (2) field period. At this time, since the analog gate 12 is given the gate signal shown in FIG. 3(H), the output of the CCD solid-state imaging probe 6 is
It is applied to the adder circuit 22 via the analog gate 12.

This adder circuit 23 is supplied with a synchronizing signal from the non-imaging signal generating circuit 23, and this synchronizing signal is added and output to the image recording section 8 as a video signal shown in FIG. 3(I). The gate signal of the gate signal forming circuit 21 is also given to the image recording section 8 in order to indicate the output timing of the video signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a time chart of the embodiment shown in FIG. 1, and FIG. 4 is a block diagram of a part of the shutter timing signal forming circuit. 6... CCD solid-state imaging element, 15... Shutter timing signal forming circuit, 16... Shutter control circuit, 1
7... Timing generation section.

Claims (1)

[Claims] (1) In a still image imaging camera equipped with a frame transfer type CCD solid-state imaging device having a CCD imaging section, a CCD storage section, and a horizontal transfer section, the a period longer than the shutter time, and
the integer whose level is delayed from the vertical synchronization signal by a period equal to the smallest integer multiple of the vertical synchronization period minus the shutter time, and whose level corresponds to shutter opening, and which maintains that level over the shutter time; a shutter timing signal forming circuit that forms a shutter timing signal having a period twice as long as the period; and a shutter control circuit that outputs a shutter open signal over a period corresponding to the shutter time based on the shutter timing signal and the release signal. During the period of the shutter open signal, a clear pulse is generated to transfer one field worth of signal charge of the CCD imaging section to a CCD storage section in synchronization with the shutter open signal and clear the signal charge of the CCD imaging section. Further, the output of transfer pulses for transferring signal charges of the CCD imaging section to the CCD storage section is prohibited other than the clear pulse, and in a period other than the period of the shutter open signal, the output of the transfer pulse is performed in response to the vertical synchronization signal. CC captures signal charge for one field of CCD imaging section.
A still image capturing camera comprising: a timing generating section that outputs a transfer pulse to be transferred to a D storage section.