JPS6353959A - Lead frame for semiconductor device and manufacture thereof - Google Patents
Lead frame for semiconductor device and manufacture thereofInfo
- Publication number
- JPS6353959A JPS6353959A JP19756286A JP19756286A JPS6353959A JP S6353959 A JPS6353959 A JP S6353959A JP 19756286 A JP19756286 A JP 19756286A JP 19756286 A JP19756286 A JP 19756286A JP S6353959 A JPS6353959 A JP S6353959A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- pattern
- lead
- tips
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 5
- 238000003825 pressing Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置用リードフレーム及びその製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lead frame for a semiconductor device and a method for manufacturing the same.
〔従来の技術］
従来、半導体装置用リードフレームに半導体素子（チッ
プ）をボンディングする場合、パッド１（第９図及び第
１０図）にチップ２を熱圧着もしくは導電性接着剤等に
より固着し、このチップ２のボンディングパッドとリー
ドフレームのインナーリード３の先端とを金線等を用い
て電気的に接続するワイヤボンディング方式と、高価な
ポリイミドテープに’ＡＢを貼り付けてその後エッチン
グして成るＴ Ａ Ｂ （Ｔａｐｅ Ａｕｔｏｌｌａｔ
ｅｄ Ｂｏｎｄｉｎｑ）用パターン（第１１図）を前も
って作っておき、このパターンの先端のバンプ５ａをチ
ップ６のボンディングパッド６ａに接続し１．続いてパ
ターン５の他端をパッドのないリードフレームのインナ
ーリード７の先端に接１伏することによりチップ６とイ
ンナーリード７とを電気的に接続するダンプ式ボンディ
ング方式（バンプ付ＴＡ８方式）とがある。[Prior Art] Conventionally, when bonding a semiconductor element (chip) to a lead frame for a semiconductor device, a chip 2 is fixed to a pad 1 (FIGS. 9 and 10) by thermocompression bonding or a conductive adhesive. There are wire bonding methods in which the bonding pads of the chip 2 and the tips of the inner leads 3 of the lead frame are electrically connected using gold wire, etc., and a T method in which 'AB is pasted on an expensive polyimide tape and then etched. A B (Tape Autollat
A pattern for ed Bondinq (FIG. 11) is prepared in advance, and the bump 5a at the tip of this pattern is connected to the bonding pad 6a of the chip 6.1. Next, a dump type bonding method (TA8 method with bumps) is used in which the chip 6 and the inner leads 7 are electrically connected by connecting the other end of the pattern 5 to the tip of the inner lead 7 of the lead frame without a pad. There is.
（発明が解決しようとする問題点〕
上記ダンプ式ボンディングは、ワイヤボンディングのよ
うに１本づつボンディングするのではなく、チップに全
リードの先端を１度にボンディングすることができるた
め、ボンディング時間の大幅な短縮を図ることがてきる
が、高価なテープを使用してＴＡＢ用パターンを作らな
ければならず、またＴＡＢ用パクーンをチップのボンデ
ィングパッドとインナーリードの先端の２箇所で接続し
なければならないため、工程数が多く、かつボンディン
グの信頼性の低下もＪＯいていた。(Problems to be Solved by the Invention) The dump type bonding described above can bond the tips of all the leads to the chip at once, instead of bonding one lead at a time as in wire bonding, which reduces the bonding time. Although it is possible to significantly shorten the time, it is necessary to create a TAB pattern using expensive tape, and the TAB pattern must be connected at two points: the bonding pad of the chip and the tip of the inner lead. As a result, the number of steps is large and the reliability of bonding is reduced.
本光明は上記ダンプ式ボンディングにおける問題点を解
決することができる半導体装置用リードフレーム及びそ
の製造方法を提供することを目的とする。It is an object of the present invention to provide a lead frame for a semiconductor device and a method for manufacturing the same, which can solve the problems in the dump type bonding.
〔問題点を解決するための手段］
本発明によれば、半導体装置用リードフレームのリード
の先端に、該リードフレームの素材の厚さよりも十分薄
く、かつその先端に凸部を有するダンプ式ボンディング
用のバンプ付パターン一体成形するようにしている。[Means for Solving the Problems] According to the present invention, a dump type bonding method is provided in which the tip of the lead of a lead frame for a semiconductor device is sufficiently thinner than the thickness of the material of the lead frame and has a convex portion at the tip. The bump pattern is integrally molded.
すなわち、リードフレームのインナーリードの先端に、
ダンプ式ボンディング用のバンプ付パターンを一体成形
したため、高価なテープを使用してバンプ付パターンを
作るという工程、このパターンの他端をインナーリード
の先端に接続する工程等を省略することができ、また接
続箇所を減らすことによりボンディングの信頼性の向上
も図ることができる。In other words, at the tip of the inner lead of the lead frame,
Since the bump pattern for dump type bonding is integrally molded, it is possible to omit the process of creating the bump pattern using expensive tape and the process of connecting the other end of this pattern to the tip of the inner lead. Furthermore, by reducing the number of connection points, it is possible to improve bonding reliability.
以下、本光明を添付図面を参照して詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
第１図は本発明に係る半導体装置用リードフレームの製
造工程中の一実施例を示す平面図で、クワッド（ＱＵＡ
Ｄ）形のリードフレームに関して示している。FIG. 1 is a plan view showing an embodiment of the manufacturing process of a lead frame for a semiconductor device according to the present invention.
D) is shown for a lead frame of type D).
同図に示すように、まず、リードフレームのアラクーリ
ード１０及びインナーリード形成予定部先端１２が臨む
箇所にスリット状の逃げ窓１４をプレス加工によって形
成する。As shown in the figure, first, a slit-shaped escape window 14 is formed by press working at a portion of the lead frame where the Araku lead 10 and the tip 12 of the portion where the inner lead is to be formed face.
続いて、上記インナーリード形成予定部先端１２をコイ
ニングによって薄く形成する。なお、前記逃げ窓１４は
、コイニングの際に、素材の延びる空間を確保するため
のものである。また、第３図は、コイニング終了後の第
１図における八−１へ断面図であり、１６はコイニング
によって薄板状に形成された部分である。Subsequently, the tip 12 of the portion where the inner lead is to be formed is thinly formed by coining. The escape window 14 is provided to ensure a space for the material to extend during coining. Moreover, FIG. 3 is a sectional view taken along line 8-1 in FIG. 1 after coining is completed, and 16 is a portion formed into a thin plate shape by coining.
次に、第２図に示すようにリードフレームのインナーリ
ード１８及びバンプ付パターン２０（第４図）をエツチ
ングによって形成する。バンプ付パターン２０は、前記
薄板状に形成された部分１６から斜線で示した部分２２
をエツチングで除去することにより形成され、その先端
には凸部（バンプ）２０ａが形成される。Next, as shown in FIG. 2, the inner leads 18 and bumped pattern 20 (FIG. 4) of the lead frame are formed by etching. The pattern 20 with bumps includes a portion 22 indicated by diagonal lines from the portion 16 formed in the shape of a thin plate.
It is formed by removing it by etching, and a protrusion (bump) 20a is formed at the tip.
なお、エツチングによって形成されるインナーリード先
端のＲ狭間隔と、エツチングされるＦｉ厚とは密接な関
係があり、インナーリード先端のバンプのように直接チ
ップのボンディングバットに接続されるものにあっては
、例えばワイヤボンディングの際の金線（２５μ７７Ｌ
）の約３倍程度、すなわち７５μ雇程度の板厚でなけれ
ばならない。Note that there is a close relationship between the R narrow spacing at the tips of the inner leads formed by etching and the thickness of the etched Fi. For example, gold wire (25μ77L) is used for wire bonding.
), or approximately 75μ thick.
一方、バンプ付パターンを形成するために一般的に使用
されるテープ（ＴＡＢ用銅箔）は、厚さが３５μ汎であ
り、リードフレームの素材の厚さを例えば上記テープの
厚さの２倍く７０μ７７Ｌ）としても、リードフレーム
としては博すぎてリードフレームとして使用する場合の
強度が確保できない。On the other hand, the tape (copper foil for TAB) commonly used to form bumped patterns has a thickness of 35 μm, and the thickness of the lead frame material is, for example, twice the thickness of the tape. Even if the lead frame is 70μ77L, it is too wide to be used as a lead frame, and the strength when used as a lead frame cannot be ensured.
一般的にリードフレームの素材は、持に多ピンハーフピ
ッチ、ファインピッチ等では１５０μｍ〜２００μｍの
厚さのものを使用しているのが通例である。 そこで、
本実施例では、前述したようにインナーリード形成予定
部先端１２を予めコイニングによって薄く形成するよう
にしている。Generally, lead frame materials with a thickness of 150 μm to 200 μm are usually used for multi-pin half-pitch, fine-pitch, and the like. Therefore,
In this embodiment, as described above, the tip 12 of the portion where the inner lead is to be formed is thinly formed in advance by coining.
なお、コイニングに限らず、エツチングにより前もって
薄く形成するようにしてもよい。In addition, it is not limited to coining, and etching may be used to form a thin layer in advance.
以上のようにしてインナーリード先端に一体成形された
バンプ付パターン２０のバンプ２０ａは、金メッキが施
されたのち、従来から使用されているチップのボンディ
ングパッドに直接接続されるが、チップのボンディング
パッドに金メッキを施しておき、また、第５図に示すよ
うにバンプ付パターン２１のバンプ２１ａをシャープに
形成し、このバンプ２１ａを楔のように押し込むことに
よって接続するようにしてもよい。The bumps 20a of the bumped pattern 20 integrally molded on the tips of the inner leads as described above are gold-plated and then directly connected to the bonding pads of the chip, which have been conventionally used. Alternatively, the bumps 21a of the bump pattern 21 may be formed sharply as shown in FIG. 5, and the bumps 21a may be pressed in like a wedge to connect.
また、上記ダンプ式ボンディングを行なう際には、パッ
ド２４（第２図参照）は取り除かれている。したがって
、前記スリット状の逃げ窓を形成する際に、パッド形成
予定部分もプレス加工によって予め取り除くようにして
もよい。Further, when performing the dump type bonding, the pad 24 (see FIG. 2) is removed. Therefore, when forming the slit-shaped escape window, the portion where the pad is to be formed may also be removed in advance by press working.
一方、パッドにチップを載置する場合には、パッドの上
部までバンプ付パターンを伸ばす必要がある。この場合
には、第６図及び第７図に示すように、パッド３１及び
サポートバー３２を含むパッド部３０とこのパッド部３
０を除くインナーリード４１、アウターリード４２等の
部分４０とをそれぞれ別体形成する。On the other hand, when placing a chip on a pad, it is necessary to extend the bump pattern to the top of the pad. In this case, as shown in FIGS. 6 and 7, a pad portion 30 including a pad 31 and a support bar 32 and a pad portion 3
Portions 40 such as inner leads 41 and outer leads 42 other than 0 are formed separately.
ここで、サポートパー３２及び枠体４３には、パッド部
３０とパッド部３０を除く部分４０とが互いに嵌合し１
ｑるようにそれぞれ凸部３２ａ及び凹部４３ａを形成し
ておく。また、インナーリード４１の先端にはバンプ４
１ａ付パターン（第８図）が一体成形されていることは
いうまでもない。Here, the pad portion 30 and the portion 40 excluding the pad portion 30 fit into each other in the support par 32 and the frame body 43.
A convex portion 32a and a concave portion 43a are respectively formed so as to be q. In addition, a bump 4 is provided at the tip of the inner lead 41.
It goes without saying that the pattern with 1a (FIG. 8) is integrally molded.
そして、このリードフレームを使用して半導体装置を製
造する場合には、第８図に示すように、まずパッド３１
にデツプ５０を固着し、続いてパッド部３０をパッド部
を除く部分４０に嵌装する。When manufacturing a semiconductor device using this lead frame, first, as shown in FIG.
Then, the pad portion 30 is fitted into the portion 40 excluding the pad portion.
また、このとぎチップ５０のボンディングパッド５０ａ
とインナーリード４１の先端のバンプ付パターン４１ａ
のバンプとが当接するようになっており、両者が接続さ
れる。Also, the bonding pad 50a of this cutting chip 50
and a bump pattern 41a at the tip of the inner lead 41.
The bumps come into contact with each other, and the two are connected.
〔発明の効果）
以上説明したように本光明によれば、半導体装置用リー
ドフレームのインナーリード先端にダンプ式ボンディン
グ用のバンプ付パターンを一体成形するようにしたため
、リードフレーム製造工程とは別にバンプ付パターンを
作る工程、このバンプ付パターンをインナーリード先端
に接続するための工程を省略することができる。また、
従来は接続箇所がバンプ付パターンのバンプとチップ、
バンプ付パターンとインナーリードの２箇所であったの
に対し、本発明ではバンプとチップの１箇所で済み、接
ｖ、箇所が少ない分だけボンディングの信頼性の向上を
図ることができる。[Effects of the Invention] As explained above, according to Komei, a pattern with bumps for dump-type bonding is integrally molded on the tip of the inner lead of a lead frame for a semiconductor device. The process of creating a pattern with bumps and the process of connecting this pattern with bumps to the tips of the inner leads can be omitted. Also,
Conventionally, the connection points were bumps and chips with bump patterns,
In contrast to the two locations, the bumped pattern and the inner lead, the present invention requires only one location, the bump and the chip, and the reliability of bonding can be improved by reducing the number of contact points.
更に、微＠１加工の少ないアウターリードはプレス加工
によって形成し、微細加工を有するインナーリード、バ
ンプ等はエツチングによって形成するようにしたため、
エツチングのみによる場合に比べてエツチング液の劣化
が遅く、またスクラップ回１１１１２ｆｆｉが大きいた
め、製造コストを安くすることができる。更にまた、ア
ウターリードをプレス加工によって形成するため、通常
エツチングで発生する可能性のある即ち上下両面よりエ
ツチングするために発生するミスマツチ（ピッチずれ）
がなく、信頼性の高いアウターリードを形成することが
でき、またアウターリードの形状はピン数が同じであれ
ばパターンはほぼ同一であるため、同一のアウターリー
ド形成用金ヤで、インナーリード部はエツチングで対応
するため多品種のリードフレームに対処することができ
るという効果がある。Furthermore, the outer leads with less micro@1 processing are formed by press processing, and the inner leads, bumps, etc. with micro processing are formed by etching.
Compared with etching alone, the etching solution deteriorates more slowly and the number of scraps (11112ffi) is greater, so manufacturing costs can be reduced. Furthermore, since the outer leads are formed by press working, there is no mismatch (pitch deviation) that may occur during normal etching, that is, due to etching from both the top and bottom surfaces.
Since the outer leads have almost the same pattern as long as they have the same number of pins, the inner leads can be formed using the same gold plate for forming the outer leads. Because it is handled by etching, it has the advantage of being able to handle a wide variety of lead frames.
第１図は本発明に係る半導体装置用リードフレームの製
造工程中の一実施例を示す平面図、第２図は第１図のリ
ードフレームから更にインナーリード及びバンプ付パタ
ーンを形成した後の平面図、第３図は第１図のＡ−Ａｔ
！Ｉｉ面図、第４図は第１図のインナーリード先端部分
の側面拡大図、第５図は他のインナーリード先端部分の
一例を示す側面拡大図、第６図はパッド部を示す斜視図
、第７図は第６図のパッド部を除くリードフレームの平
面図、第８図は第６図及び第７図に示すリードフレーム
によってダンプ式ボンディングが行なわれる様子を示す
側面図、第９図は従来のリードフレームの一例を示す平
面図、第１０図はワイヤボンディングを説明するために
用いた図、第１１図は従来のダンプ式ボンディングを説
明するために用いた図である。
１０・・・アウターリード、１２・・・インナーリード
形成予定部先端、１４・・・逃げ窓、１６・・・薄板状
に形成された部分、１８・・・インナーリード、２０゜
２１・・・バンプ付パターン、２０ａ、２１ａ・・・凸
部（バンプ）。
第１図
第２図
第３図
ｇａ
第４因
第５図
第６図
第７図
第８図FIG. 1 is a plan view showing an embodiment of the manufacturing process of a lead frame for a semiconductor device according to the present invention, and FIG. 2 is a plan view after inner leads and bump patterns are further formed on the lead frame of FIG. 1. Figure 3 is A-At in Figure 1.
! 4 is an enlarged side view of the tip of the inner lead in FIG. 1, FIG. 5 is an enlarged side view of another example of the tip of the inner lead, and FIG. 6 is a perspective view of the pad portion. FIG. 7 is a plan view of the lead frame excluding the pad portion shown in FIG. 6, FIG. 8 is a side view showing how dump type bonding is performed using the lead frame shown in FIGS. 6 and 7, and FIG. 9 is a side view of the lead frame shown in FIG. A plan view showing an example of a conventional lead frame, FIG. 10 is a diagram used to explain wire bonding, and FIG. 11 is a diagram used to explain conventional dump type bonding. DESCRIPTION OF SYMBOLS 10... Outer lead, 12... Tip of inner lead formation planned portion, 14... Relief window, 16... Portion formed in thin plate shape, 18... Inner lead, 20° 21... Pattern with bumps, 20a, 21a...convex portions (bumps). Figure 1 Figure 2 Figure 3 ga 4th factor Figure 5 Figure 6 Figure 7 Figure 8
Claims (2)
先端に、該リードフレームの素材の厚さよりも十分薄く
、かつその先端に凸部を有するダンプ式ボンディング用
のバンプ付パターンを一体成形したことを特徴とする半
導体装置用リードフレーム。(1) A bump pattern for dump type bonding, which is sufficiently thinner than the thickness of the material of the lead frame and has a convex portion at the tip, is integrally molded on the tip of the inner lead of a lead frame for semiconductor devices. Lead frame for semiconductor devices.
のアウターリード及びインナーリード形成予定部先端が
臨む箇所に逃げ窓を形成し、 次に、コイニング若しくはエッチングによって前記イン
ナーリード形成予定部先端を薄板状に形成し、 最後に、エッチングによって前記半導体装置用リードフ
レームのインナーリード及び前記薄板状に形成した部分
の先端に凸部を形成し、 前記インナーリードの先端にダンプ式ボンディング用の
バンプ付パターンを一体成形したことを特徴とする半導
体装置用リードフレームの製造方法。(2) An escape window is formed by pressing at a location where the tips of the outer lead and inner lead forming portions of the lead frame for semiconductor devices face, and then, the tips of the inner lead forming portions are formed into a thin plate shape by coining or etching. Finally, a convex portion is formed on the inner lead of the semiconductor device lead frame and the tip of the thin plate-shaped portion by etching, and a bump pattern for dump type bonding is integrally formed on the tip of the inner lead. A method for manufacturing a lead frame for a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19756286A JPS6353959A (en) | 1986-08-22 | 1986-08-22 | Lead frame for semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19756286A JPS6353959A (en) | 1986-08-22 | 1986-08-22 | Lead frame for semiconductor device and manufacture thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62306457A Division JPS63239852A (en) | 1987-12-03 | 1987-12-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6353959A true JPS6353959A (en) | 1988-03-08 |
Family
ID=16376563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19756286A Pending JPS6353959A (en) | 1986-08-22 | 1986-08-22 | Lead frame for semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6353959A (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239557A (en) * | 1988-07-29 | 1990-02-08 | Toppan Printing Co Ltd | Lead frame and semiconductor device |
| US5367766A (en) * | 1990-08-01 | 1994-11-29 | Staktek Corporation | Ultra high density integrated circuit packages method |
| US5369058A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US5377077A (en) * | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5420751A (en) * | 1990-08-01 | 1995-05-30 | Staktek Corporation | Ultra high density modular integrated circuit package |
| US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5448450A (en) * | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| US5475920A (en) * | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
| US5644161A (en) * | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5702985A (en) * | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
| KR980012371A (en) * | 1996-07-16 | 1998-04-30 | 사와무라 시꼬 | Bumpless connection of internal leads to semiconductor integrated circuits |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
| US6051450A (en) * | 1997-07-01 | 2000-04-18 | Sony Corporation | Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus |
| JP2010040595A (en) * | 2008-07-31 | 2010-02-18 | Mitsui High Tec Inc | Lead frame and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
| US9581248B2 (en) | 2012-10-04 | 2017-02-28 | Eagle Industry Co., Ltd. | Mechanical seal |
-
1986
- 1986-08-22 JP JP19756286A patent/JPS6353959A/en active Pending
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0239557A (en) * | 1988-07-29 | 1990-02-08 | Toppan Printing Co Ltd | Lead frame and semiconductor device |
| US5367766A (en) * | 1990-08-01 | 1994-11-29 | Staktek Corporation | Ultra high density integrated circuit packages method |
| US5377077A (en) * | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5420751A (en) * | 1990-08-01 | 1995-05-30 | Staktek Corporation | Ultra high density modular integrated circuit package |
| US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5475920A (en) * | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
| US5550711A (en) * | 1990-08-01 | 1996-08-27 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5566051A (en) * | 1990-08-01 | 1996-10-15 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5448450A (en) * | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| US5528075A (en) * | 1991-08-15 | 1996-06-18 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| US5702985A (en) * | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
| US5644161A (en) * | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5864175A (en) * | 1993-03-29 | 1999-01-26 | Staktek Corporation | Wrap-resistant ultra-thin integrated circuit package fabrication method |
| US5369058A (en) * | 1993-03-29 | 1994-11-29 | Staktek Corporation | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US6194247B1 (en) | 1993-03-29 | 2001-02-27 | Staktek Group L.P. | Warp-resistent ultra-thin integrated circuit package fabrication method |
| US5801437A (en) * | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5828125A (en) * | 1993-03-29 | 1998-10-27 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5843807A (en) * | 1993-03-29 | 1998-12-01 | Staktek Corporation | Method of manufacturing an ultra-high density warp-resistant memory module |
| US5581121A (en) * | 1993-03-29 | 1996-12-03 | Staktek Corporation | Warp-resistant ultra-thin integrated circuit package |
| US5895232A (en) * | 1993-03-29 | 1999-04-20 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| KR980012371A (en) * | 1996-07-16 | 1998-04-30 | 사와무라 시꼬 | Bumpless connection of internal leads to semiconductor integrated circuits |
| US5945732A (en) * | 1997-03-12 | 1999-08-31 | Staktek Corporation | Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package |
| US6190939B1 (en) | 1997-03-12 | 2001-02-20 | Staktek Group L.P. | Method of manufacturing a warp resistant thermally conductive circuit package |
| US6051450A (en) * | 1997-07-01 | 2000-04-18 | Sony Corporation | Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus |
| US6563202B1 (en) | 1997-07-01 | 2003-05-13 | Sony Corporation | Lead frame, manufacturing method of a lead frame, semiconductor device, assembling method of a semiconductor device, and electronic apparatus |
| JP2010040595A (en) * | 2008-07-31 | 2010-02-18 | Mitsui High Tec Inc | Lead frame and method of manufacturing the same, and semiconductor device and method of manufacturing the same |
| US9581248B2 (en) | 2012-10-04 | 2017-02-28 | Eagle Industry Co., Ltd. | Mechanical seal |
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