JPS635324Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention applies a capstan servo intermittently to a videotape running at high speed, records the playback video signal in memory, and repeatedly plays the recorded signal in the memory every time recording is completed. The present invention relates to a video tape recorder designed to provide noiseless reproduced images while the video tape is running at high speed.

In general, helical scan video tape recorders are equipped with two video heads in order to record high-density video tape, and each video head has a different azimuth to reduce strokes from adjacent tracks during playback. There are many things.

However, when a video signal recorded on a video tape is played back while the video tape recorder using the above-mentioned method is running at high speed, the video head crosses many tracks on the video tape, so the azimuth is different from that of the head during playback. The recorded track becomes a noise band on the TV screen, making the TV screen unsightly.

This invention has been made with the above-mentioned points in mind, and next, this invention will be explained in detail with reference to the drawings of FIGS. 1 to 3 showing one embodiment of the invention.

In FIG. 1, A is a signal generating section to which a search signal is input from a search input terminal a by operating a search button (not shown), and is composed of an oscillation circuit. For example, from t1 to t2 and from t3 to t4
stays high for about 1 second, t2
From time t3, that is, a square wave pulse signal that is in a low state for about 2 seconds is supplied from the control terminal b to the pinch roller (not shown) and the supply reel stand brake (not shown), and the pulse signal is in a high state. , the supply reel stand brake is turned on, the capstan drive motor (not shown) is controlled to be almost equal to the speed during standard playback, and the pinch roller is pressed against the capstan, and conversely, due to the low state of the pulse signal, Release the pinch roller from the capstan and turn off or release the supply reel stand brake. B is a frequency dividing section connected to the signal generating section A, which consists of a flip-flop, and divides the frequency of the input pulse signal into 1/2 as shown in Fig. 2, for example, from time t2 to time t4. Outputs a square wave control signal that goes high.
h1 and h2 are video heads that detect the reproduced composite video signal from a videotape (not shown) during the high state of the pulse signal; C are both video heads h1 and h;
2 is a preamplifier that amplifies the detected reproduced composite video signal; D is a limiter connected to preamplifier C; E is a demodulation circuit that demodulates the output of limiter D;
F is a synchronization separation circuit connected to the demodulation circuit E, and outputs a reproduced vertical signal and a reproduced horizontal signal. A coincidence signal input terminal c receives a coincidence signal indicating that the relationship between the phase of the position pulse and the phase of the control pulse, which determine the phase of the rotating video head, is substantially the same as that during standard reproduction. G is a write control unit to which a coincidence signal is input, and by controlling the pulse signal, the reproduction vertical signal, and the reproduction horizontal signal, it synchronizes with the reproduction synchronization signal while the pulse signal is in the high state as shown in Fig. 2. A write clock pulse is output which is ON only for one field period of the reproduced composite video signal, that is, from time t1' to time t2 and from time t3' to time t4 shown at v in the figure. S1 is a two-contact type first switch whose movable piece is connected to the write control section G, and is switched and controlled by a control signal from the frequency dividing section B.
S2 is a two-contact type second switch whose movable piece is connected to the demodulation circuit E, into which the reproduced video signal obtained by removing the reproduction synchronization signal from the reproduced decombined video signal is input, and the switch is controlled by the control signal of the frequency divider B. be done.
M1 is the first memory, which consists of a small-capacity analog memory, such as BBD, CCD, or digital memory, and is connected to one contact of the first switch S1 and the second
It is connected to one contact of switch S2, and records one field of reproduced video signal under the control of the write clock pulse. M2 is a second memory, which is a small-capacity analog memory or digital memory like the first memory M1, and is connected to the other contact of the first switch S1 and the other contact of the second switch S2, and is connected to the write clock pulse. Under the control of the controller, one field of playback video signal is recorded. Reference numeral H designates a second synchronization separation circuit to which the composite video signal without passing through the video tape and both video heads h1 and h2 is input directly through the video input terminal d, and extracts a synchronization signal component from the composite video signal and outputs it. is a readout control unit to which the synchronization signal component from the second synchronization separation circuit H is input;
Outputs read clock pulse. S3 is a two-contact type third switch whose movable piece is connected to the readout control section, one contact is connected to the first memory, the other contact is connected to the second memory, and the frequency dividing section B is connected to the second memory. Switching is controlled by control signals,
A read clock pulse is output to the first and second memories M1 and M2 each time recording is completed in each of the first and second memories M1 and M2. S4 is a 2-contact type fourth switch, and one contact is connected to the first memory M1.
At the same time, the other contact is connected to the second memory M2, and the movable piece is switched and controlled by the control signal of the frequency dividing section B, and the first and second memories M1 and M2 are connected to each other.
Recording signals are input alternately. J is a mixing part connected to the movable piece of the fourth switch S4,
The composite video signal from the video input terminal d and the recording signal from the fourth switch S4 are combined, and the composite video signal is outputted to a television (not shown) via the output terminal e, as shown in FIG. , a main image 1a formed from a composite video signal and a sub-image 1b formed from a recording signal are multiplexed on a television screen 1.

Next, the operation of the above embodiment will be explained. For example, when a videotape is run at high speed in the forward direction, a search signal is input to the signal generator A through the search input terminal a by operating the search button, and the signal generator A generates a square wave pulse as described above. The signal is output and the pulse signal is sent to the control terminal b
is supplied to the pinch roller and the reel stand brake through the pulse signal from time t1 to time t2 in Fig. 2, and the supplied reel stand brake is turned on, and the speed of the capstan drive motor is set to the speed during standard playback. At the same time, the pinch roller is pressed against the capstan, and the running of the videotape during high-speed running is switched to capstan control in which the video tape is driven by the capstan.

Furthermore, the pulse signal is input to the frequency divider B, and as shown in FIG. , S2, S3, S4,
The movable pieces of the first and second switches S1 and S2 are connected to one contact point, and the movable pieces of the third and fourth switches S3 and S4
The movable piece is connected to the other contact.

On the other hand, the rotating video heads h1 and h2 detect a reproduced composite video signal from the video tape, and the detected reproduced composite video signal is input to the demodulation circuit E via the preamplifier C and the limiter D.
The output of the first synchronous separation circuit F and the second switch S2
is input.

The relationship between the phase of the position pulse that controls the rotation of the rotating video heads h1 and h2 and the phase of the control pulse that applies servo to the capstan drive motor almost matches the phase relationship during standard playback. In other words, when the traces of the video heads h1 and h2 become almost the same as during standard playback and no noise band appears, the coincidence signal is sent to the write control unit G via the coincidence signal input terminal d.
The pulse signal from the signal generator A and the first synchronization separation circuit F are input to the write control unit G.
The period from time t1' to time t2 in FIG. 2, that is, the period of one field of the reproduced composite video signal,
A write clock pulse that goes high in synchronization with the reproduction horizontal synchronization signal is output, and the write clock pulse is sent to the first memory M via the first switch S1.
1, and the reproduced video signal is also input to the first memory M1 from the demodulation circuit E via the second switch S2, and during the period from time t1' to time t2,
A reproduced video signal of one field is recorded.

Then, at time t2, the pulse signal of the signal generator A goes low, and the control signal of the frequency divider B goes high, and the low state of the pulse signal causes
The pinch roller is separated from the capstan, the brake of the supply reel stand is turned off or released, the videotape is run at high speed, and the high state of the control signal causes the movable pieces of the first and second switches S1 and S2 to close to the other contact point. At the same time, the movable pieces of the third and fourth switches S3 and S4 are connected to one of the contacts.

Furthermore, the composite video signal is input to the second sync separation circuit H and the mixing section J via the video input terminal d, and the second sync separation circuit H extracts the sync signal component from the composite video signal, and also extracts the sync signal component from the composite video signal. is output to the read control unit I, the read control unit I outputs a read clock pulse according to the control signal of the frequency dividing unit B, and the read clock pulse is input to the first memory M1 via the third switch S3. The reproduced video signal of one field recorded in the memory M1, that is, the recording signal, is sent to the mixing section J via the fourth switch S4 from time t2 shown in FIG. The composite video signal and the recording signal are combined by the mixing section J to form a composite video signal, and the composite video signal is supplied to the television via the output terminal e. As shown in FIG. 3, the recorded contents of the first memory M1 are reproduced on the TV screen 1 by multiplexing the main image 1a based on the composite video signal and the sub-image 1b based on the recording signal, and at this time, the sub-image 1b is displayed on the TV screen. It accounts for 1/4 of 1.

Moreover, when the pulse signal of the signal generator A changes from the low state to the high state again at time t3 shown in FIG.
As described above, the running of the videotape during high-speed running is switched to capstan control. However, since the control signal of the frequency divider B does not change its state, the switches S1, S2, S3, and S4 are not controlled.
Therefore, between time t3' and time t4, the write clock pulse in the high state output from the write control unit G is transferred to the second memory M2 via the first switch S1.
At the same time, the reproduced video signal is input from the demodulation circuit E to the second memory M via the second switch S2.
2, and the period from time t3' to time t4, that is, the reproduced video signal of one field is recorded.

Then, at time t4, the pulse signal of the signal generator A goes low again, and the control signal of the frequency divider B goes low, causing the videotape to run at high speed and switching the first and second switches S1 and S2. Connect the movable piece to one contact, and connect the movable pieces of the third and fourth switches S3 and S4 to the other contact, and t4
time, that is, after the end of recording in the second memory M2,
Next, until the control signal of the frequency divider B goes high, the reproduced video signal of one field recorded in the second memory M2 is repeatedly output to the mixing section J, and the mixing section J outputs the reproduced video signal from the video input terminal d. The composite video signal and the recorded signal are combined to form a composite video signal, and the recorded content of the second memory is reproduced by multiplexing the main image 1a based on the composite video signal and the sub-image 1b based on the recorded signal on the TV screen 1. do.

By repeating the above operations, while the control signal of the frequency dividing section B is in a high state, the recording signal of the first memory M1 is repeatedly input to the mixing section J, and the main image 1a based on the composite video signal is displayed on the TV screen 1. First memory M1
The recorded content of the first memory M1 is reproduced by multiplexing the sub-image 1b based on the recorded signal of A main image 1a and a second image are displayed on the TV screen 1 by the composite video signal.
The sub-image 1b based on the recording signal of the memory M2 is multiplexed to reproduce the recorded contents of the second memory M2, and the video tape is run at high speed in the forward direction.

Therefore, according to the embodiment, when the videotape is running at high speed in the forward direction, the videotape is intermittently switched to capstan-controlled running by operating the search button, and while the videotape is running under capstan control, Under the control of the write clock pulse, each memory M1, M2 alternately records one field of the reproduced video signal, and each time each memory M1, M2 finishes recording, the video tape is made to run at high speed again, and each memory M1, M2 By repeatedly and alternately reproducing one field of recorded video signal on the television screen 1 as a sub-image 1b multiplexed with the main image 1a, a noiseless sub-image 1b can be displayed on the TV screen while the videotape is running at high speed. Furthermore, by multiplexing the sub-image 1b onto the main image 1a and reproducing the sub-image 1b on 1/4 of the screen 1, the first and second memories M
For example, a small analog memory of about 64×64 elements can be used for 1 and M2.

Further, by synchronizing the write clock pulse with the reproduction horizontal synchronization signal, horizontal jitter can be reduced.

As described above, according to the videotape recorder of this invention, a videotape running at high speed is intermittently switched to running under capstan control by operating the search button, and while the videotape is running under capstan control, The first, first and second channels alternately record the reproduced video signal of one field under the control of the write clock pulse of the write control section.
A second memory is provided, and each time recording in the first and second memories is completed, a recording signal is output from the first and second memories by the readout clock pulse of the readout control unit, and the recorded contents of each memory are displayed on the TV screen. By repeatedly and alternately playing back the video tape and running the videotape at high speed, it is possible to provide a noiseless reproduced image while the videotape is running at high speed.

Furthermore, the readout clock pulse is formed by the synchronization signal component of the composite video signal, and the main image of the composite video signal and the sub-image of the recording signal are multiplexed on the television screen.
The capacities of the first and second memories can be reduced.

[Brief explanation of the drawing]

Figure 1 shows one of the videotape recorders of this invention.
The block diagram of the embodiment, FIG. 2, is a waveform diagram of the pulse signal, control signal, and write clock pulse shown in FIG. 1, and FIG. 3 is an explanatory diagram of a television screen on which a main image and a sub-image are multiplexed. A... Signal generation section, B... Frequency division section, G... Write control section, I... Read control section, J... Mixing section, M1, M2,... First and second memory, h1,
h2...Video head, 1...TV screen, 1a
...Main image, 1b...Sub-image.

Claims (1)

[Claims for Utility Model Registration] A frequency dividing unit that divides the frequency of the pulse signal and outputs a frequency-divided signal is connected to a signal generation unit that outputs a pulse signal when a search button is operated, and one of the on and off of the pulse signal is connected. Depending on the state of , the speed of the capstan drive motor is controlled to be approximately equal to the speed during standard playback, the pinch roller is pressed against the capstan, the videotape running at high speed is switched to running under capstan control, and the other side of the pulse signal is Depending on the state, the pinch roller is separated from the capstan, the brake of the reel stand is released, the videotape is made to run at high speed again, and a reproduced composite video signal is detected from the videotape during one of the states of the pulse signal. a video head that
a write control unit that outputs a write clock pulse when the relationship between the phase of a position pulse that controls the rotational speed of the rotating video head and the phase of a control pulse substantially matches the phase relationship during standard playback; The write clock pulses are alternately inputted in response to a frequency signal, and the write clock pulses record one field of the reproduced video signal from the reproduced composite video signal in the first and second memories, and each of the first and second memories ends recording. a readout control unit that outputs readout clock pulses to the first and second memories to repeatedly reproduce the recorded signals of the first and second memories on the television screen; The videotape recorder runs the videotape at high speed while repeatedly and alternately reproducing the recording. A mixing unit is provided for inputting a synchronization signal component of the composite video signal to a readout control unit, forming a readout clock pulse using the synchronization signal component, and synthesizing the respective recorded signals of the first and second memories and the composite video signal, Utility model registration claim 1, in which a main image from the composite video signal and a sub-image from the recording signal are multiplexed on a television screen by a composite video signal from the mixing section.
The videotape recorder described in Section.