JPS6350228A - Multiplex communication equipment - Google Patents

Abstract

PURPOSE:To give the versatility to the discriminating means of channel boards by providing the discriminating means with a command discriminating means and a command reporting means in common to all channel boards. CONSTITUTION:A demultiplexer 100, channel boards 201-20n, and a control circuit 300 are provided, and the control circuit 300 is provided with selectors 1 and 6-9, a parallel/serial converter 2, a comparator 3, an adder 4, a subtracter 5, a driver 10, a latching circuit 11, a memory 12, NOR circuits 13 and 24, decoders 14, 20, 21, and 25, AND circuits 15, 16, 22, and 23, an OR circuit 17, and exclusive OR circuits 18 and 19. The demultiplexer 100 demultiplexes coming multiplexed data to distribute data to respective channel boards. The control circuit 300 discriminates the presence or the absence of a loop back command in each of all channels based on a loop back set command (a), a reset command (b), and demultiplex data (c) and issues command execution instructions to channel boards based on discrimination results. Since loop back commands from all channels are concentratedly discriminated in one circuit in such a manner, the burden of each channel board is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to multiplex communication means. In particular, the present invention relates to a demultiplex system that determines a loop back command from received data and instructs the channel board of the channel where the command is found to execute the command. The present invention is used for monitoring digital exchanges.

〔overview〕

The present invention provides a means for determining the channel board on which a command is executed among the channel boards of a multiplex communication device, by providing a common command determining means and a command notification means for all channel boards, thereby making the determining means universal. It was designed so that it could be given gender.

[Conventional technology]

Conventionally, command discrimination was performed on each channel board.

[Problem that the invention seeks to solve]

In such conventional means, it is necessary to install a command discrimination circuit for each channel, which increases cost.
Another drawback is that the device cannot be made compact. Also,
Even when the command discrimination circuit is implemented as an LSI, there is a drawback that it cannot respond to changes in command codes.

The present invention aims to eliminate such drawbacks and provides a multiplex communication device equipped with a compact command discrimination circuit.

[Means for solving problems]

The present invention provides a multiplex communication device comprising a demultiplexing/converting means for separating data arriving via a transmission path having a plurality of channels into data corresponding to the channels, and a channel board provided corresponding to the channels. , comprising a determining means for determining a channel corresponding to data that is a command code among the separated data, and a notifying means for instructing a channel board corresponding to the determined channel to execute a command. do.

[For production]

The incoming multiplexed data is demultiplexed and the data is distributed to each channel board. At this time, the presence or absence of a loop back command is determined for all channels, and a command execution command is issued to the channel board based on the result of this determination.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of this embodiment circuit, and FIG. 2 is a block diagram showing the configuration of the control circuit of this embodiment circuit.

First, the configuration of this embodiment circuit will be explained. This embodiment circuit includes a demultiplexing/converting device 100 and a channel board 201 to
2On, and a control circuit 300, where the control circuit 3
00 is selectors 1.6 to 9, parallel to serial converter 2,
Comparator 3, adder 4, subtracter 5, driver 10, latch circuit 11, memory 12, NOR circuits 13 and 24, decoders 14, 20, 21 and 25, and AND circuit 15, 16 .22 and 23 and OR circuit 17
and exclusive OR circuits 18 and 19.

Next, based on a table showing state transitions of each channel, an explanation will be given of an operation in which the state of a channel changes from ■ to ■ in the table in response to a loop back set command a sent by a certain channel.

A state flag and a command reception counter (all 4 bits are 0 in the data communication state) of the channel in the normal data communication state (2) are stored at an address assigned to the channel in the memory 12.

When the address assigned to the current channel is input to the memory 12 from the demultiplex address j, the current state flag and counter value of the channel are transferred to the launch circuit by the RAM read signal g and latch pulse e. It is output from 11.

In this state, when a loop back set command is input to the parallel to serial converter 2 from the demultiplex data C, the serialized loop back set command is input according to the L/RSEL flag (state 1). Loop back cent command code a selected by selector 1
It is also input to the comparator 3. As a result of the comparison between two people,
"1" is output to the OK side and "0" to the NG side. OK
It is input to the side ratio output adder 4 and the selector 6, the counter in the adder 4 becomes (0001)z, and this counter value is selected by the selector 6. Further, this counter value is selected by the selector 8 according to the C/B SEL flag held in the launch circuit 11. Furthermore, in the gate circuits 13 and 15 to 19 and the decoders 14 and 25, the current state flag is held until the carry bit (H bit) of the counter becomes "1". Communication reset signal d
is in the normal state "0", so the counter value and the state flag are selected by the selector 9.

These values are written to the memory address corresponding to the channel through the driver 10.

In this way, when the adder 4 receives the "OK side ratio output 1" from the comparator 3 eight times in succession, the carry bit becomes "1" and the gate circuits 13 and 15 to 19 and the decoder 14 and 25, and the status flag input to the selector 9 changes to ■ in the table.

Then, the counter <1000)z and the status flag are written to the address corresponding to the channel in the memory 12 through the selector 9 and driver 10.

Furthermore, when these values are output from the NOR circuit 11, a command approval signal k is output from the gate circuit 24 due to the input of the C/B SBL flag (state fio) and the RAM write signal state O. .

After eight command codes have been received from the channel, the data input from the demultiplexed data C typically becomes communication data. When this data is input to the comparator 3, "0" is output to the OK side and "1" is output to the NG side. The counter that is input to the NG side output subtracter 5 and the selector 7 and whose current value is (1000) is the subtracter 5.
This results in (0111)z, and the selector 7 selects this counter value. Further, this counter value is selected by the selector 8 according to the C/B SEL flag held in the latch circuit 11. In addition, gate circuits 13 and 1
5 to 19 and decoders 14 and 25, the current state flag is held until the counter becomes 0 by the subtracter 5. These count values and status flags are sent to selector 9.
and is written to the address corresponding to this channel in memory 12 through driver 10. Further, a command approval signal k is outputted from the gate circuit 24 every time the RAM write signal state becomes c or O.

In this way, when the subtractor 5 receives ``NG side output 1'' from the comparator 3 eight times in a row, the value of the counter becomes ``0''.
Then, the state flag calculated by the NOR circuit 13, the AND circuits 15 to 19, and the decoders 14 and 25 and input to the selector 9 changes to ■ in the table. Then, these counter values and status flags are written to the address corresponding to the current channel in the memory 12 through the selector 9 and driver 10. Here, when the value read from the memory 12 is output from the launch circuit 11,
By inputting the S/RLPB flag (state 1) and the RAM write signal state O, the loop bank set signal i is output from the gate circuit 23.

In the present invention, the above processing is performed on each channel data in a time-division manner. This control is performed by inputting the demultiplex address and demultiplex data. Also, the status flags and command reception counter values of each channel are stored in memory 1 according to the demultiplex address.
Writing and reading to and from 2 are performed, realizing time-division parallel processing.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing the burden on each channel board because the loop bank commands from all channels are centrally determined by one circuit.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the control circuit shown in FIG. 1. 1-6-9...Selector, 2...Parallel-serial converter,
3...Comparator, 4...Adder, 5...Subtractor, 1
0...Driver, 11...Latch circuit, 12...
Memory, 13.24...NOR circuit, 14.20.21
．． 25...Decoder, 15.16.22.23...
AND circuit, 17...OR circuit, 18.19...exclusive OR circuit, 100...multiplexing/demultiplexing conversion device, 201
~2On...Channel board, 300...Control circuit, a
...loop back set command code, b
...loop back reset command code,
C...Demultiplex data, d...Communication reset signal, e...Latch pulse, f...RAM
Write signal, g...RAM read signal, h...Loop.
Back reset signal, i...Loop bank cent signal, j...Demultiplex address, k...
・Command Approval Letter Patent Applicant: NEC Corporation. Agent: Naotaka Ide, patent attorney.

Claims (1)

[Claims] (1) In a multiplex communication device equipped with a demultiplexing/converting means for separating data arriving via a transmission path having a plurality of channels into data corresponding to the channels, and a channel board provided corresponding to the channels, The present invention is characterized by comprising a determining means for determining a channel corresponding to data that is a command code among the separated data, and a notifying means for instructing a channel board corresponding to the determined channel to execute a command. Multiplex communication equipment.