JPS6350220A - Error correction system - Google Patents

Abstract

PURPOSE:To increase the transmission capacity and reduce the used clock frequency by transmitting error correction encoded redundant bits through a stand-by line to perform the error correcting operation in the reception side if current lines and the stand-by line are normal and inhibiting the error correcting operation if either of current and stand-by lines is abnormal. CONSTITUTION:An error correction encoding part FEC ENC generates check bits for respective channels in accordance with signals on respective lines from a serial/parallel converter S/P. Check bits are converted to a radio frequency signal of a stand-by line P and are synthesized with signals of current lines and are supplied to an antenna. Error correction decoding parts FEC DEC1 and EEC DEC2 alternately take out check bits of current lines from a demodulated signal of the stand-by line P frame by frame and generate error position detection signals. An exclusive OR circuit EOR uses the error position detection signal of each channel to operate exclusive OR and corrects error bits. If trouble occurs in any of current lines, the signal of the trouble line is switched to the stand-by line.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Prior Art (Figures 5 and 6) Field of Industrial Application Problems to be Solved by the Invention Means for Solving the Problems (Figure 1) Working Examples (Figures 2 to 4) Effects of the Invention [Summary] In a communication system in which one protection line is provided for a plurality of working lines, when all the working lines and protection lines are normal, each working line is The signal on the line is encoded with error correction code, the redundant bits of the error correction code are transmitted using the protection line, and the error correction operation is performed on the receiving side, thereby improving the error rate of each working line. If any of the backup lines is abnormal, the transmission of redundant bits is stopped and error correction operations on the receiving side are prohibited, and the signal of the failed working line is transmitted using the protection line to recover from the failed working line. At this time, by providing at least two systems of error correction decoding units that perform error correction decoding on the receiving side and performing error correction decoding alternately, the transmission speed on each working line can be improved by error correction. Enable the same speed as before encoding.

[Industrial application field]

The present invention relates to a communication system that uses error correction codes for signal transmission and detects and corrects code errors on the receiving side. In particular, in such a communication system, when the working line and the protection line are all normal, the error correction code is not used. This invention relates to an error correction method in which redundant bits are transmitted via a protection line.

In wireless communication systems, code errors in received signals often occur due to deterioration of propagation conditions due to selective fading. For this reason, a method is generally used in which signals are transmitted using error correction codes and errors are detected and corrected on the receiving side.

In this case, by transmitting redundant bits of the error correction code,
It is desired that the frequency usage efficiency in communication lines does not decrease.

[Conventional technology]

In wireless communication systems, in order to prevent deterioration of the received signal due to deterioration in line quality, a method is generally used to provide backup lines and to switch over to the failed working line when the level falls below the momentary interruption standard. ing.

In addition, many methods are used to increase the frequency utilization efficiency of the line by using the digital multiphase multivalue conversion method, but in this case, because the signal point spacing is narrow, the transmission path due to equipment deterioration or propagation condition deterioration, etc. Code errors are likely to occur on the receiving side due to increases in distortion and noise. For this reason, a method is used in which signal transmission is performed using an error correction code, and error detection and correction is performed on the receiving side to improve signal quality.

When using an error correction code system, it is necessary to transmit error correction check bits (check bits) at the same time as the main signal, but conventionally, check bits are inserted into the main signal line by speed converting the main signal. A transmission method is generally used.

Figure 5 shows the configuration of a conventional wireless communication system, where (a) shows the transmitting side and (bl shows the receiving side.On the transmitting side, when all the working lines are normal) Input signals 1 to N of multiple channels are distributed to N working lines 1 to N and one protection line P through the baseband switch BB SW. The input line of each line consists of a bipolar signal 1, which is converted into a unipolar signal through a bipolar/unipolar converter B/U.

Each of the converted signals is sent to an error correction encoder FEC and converted from a serial signal to a parallel signal and sent to a modulator MOD.
added to. The modulator MOD inputs parallel input signals, e.g.
Convert to multi-phase multi-value signal such as 4-value QAM signal and send to transmitter TX
, and the transmitter Tx thereby generates the radio frequency signals 1 to N of the working line. These radio frequency signals are combined via a multiplexer (not shown), supplied to the antenna, and sent from the antenna to the receiving side.

On the receiving side, a signal received via an antenna (not shown) is separated into signals 1-N of each channel via a splitter and sent to receiver 1? X, the received signal of each channel is demodulated via the demodulator DEM, and the parallel signal is converted to a serial signal via the speed conversion/parallel/serial converter SC-P/S, and speed conversion is performed. Separate test bits.

Each error correction decoding unit FECDEC performs, for example, 1-bit error correction and 2-bit error detection using the check bits separated from the serial signal of each channel. The error-corrected signals are unipolar signals, each of which is converted to a bipolar signal via a unipolar/bipolar converter U/B and applied to the baseband switch BBS-, which switches between the working line and the protection line. hand,
It produces N channels of output signals 1-N.

When a fault occurs in any of the working lines 1 to N, the baseband switch BB SW switches the signal of the faulty line to the protection line, whereby the signal of the faulty working line is transmitted via the protection line, and the radio frequency signal Output as P. The receiving side receives the radio frequency signal P and performs the necessary processing, and the baseband switch BB SW switches to output the signal of the protection line to the channel corresponding to the faulty line, thereby relieving the faulty working line. be done.

FIG. 6 shows the transmission code structure during normal operation in the conventional wireless communication system shown in FIG. 5, in which the information bits ■, ■, . . .
-1■ and check bits c l, c2 . -, c
, , information bit ■°, ■゛.

−, o' and the check bits c, l,
c21°-1CN′ etc. are transmitted sequentially for each frame.

On the other hand, no signals are transmitted to the protection line, and in order to shorten the switching time when switching to the protection line, random
Only a pattern (PN code) may be transmitted.

[Problem that the invention seeks to solve]

When the check bits of the error correction code system are inserted into the main signal line and transmitted as described above, the information increases by the amount of the check bits, so it is necessary to increase the speed of the main signal line. Therefore, it is necessary to increase the clock frequency of the system, and there is a problem that the frequency utilization efficiency decreases.

On the other hand, the backup line is idle when the working line is healthy.
The equipment and the power required to operate it are wasted, but no consideration has been given to utilizing this in the past.

[Means for solving problems]

The present invention aims to solve the problems of the prior art, and provides a wireless communication system having the basic configuration shown in FIG. 1, in which one protection line is provided for a plurality of working lines. , an error correction encoding means 101 on the transmitting side;
Redundant bit multiplexing means 102 and switching means 103
, 104, and an error correction decoding means 105 on the receiving side.
and switching means 106 and 107.

The error correction encoding means 101 generates an output by error correction encoding the signals of each working line.

Redundant bit multiplexing means 102 multiplexes redundant bits in the error correction code of each line to create one channel signal.

The first switching means 103 on the transmitting side switches the signal of the working line to the protection line when a failure occurs in any of the working lines.

The second switching means 104 on the transmitting side receives the multiplexed redundant bit signal from the redundant bit multiplexing means 102,
The output of the first switching means 103 is switched and output to the protection line.

The error correction decoding means 105 consists of at least two systems and operates alternately to perform error correction decoding on the signals of each working line using respective redundant bits transmitted via the protection line.

The first switching means 106 on the receiving side alternately switches the output of each error correction decoding means 105 for each frame and outputs it to each working line.

The second switching means 107 on the receiving side switches the signal of the faulty working line transmitted via the protection line to the corresponding working line and outputs the signal.

[For production]

When both the working line and the protection line are normal, the signal of each working line is encoded with error correction code and only the respective redundant bits are transmitted via the protection line, and the redundant bit signal is separated for each line on the receiving side. An error correction operation is performed for each working line based on the signal of each working line.

At this time, at least two systems of error correction decoding sections for performing error correction operations are provided on the receiving side, and are operated alternately for each frame. Therefore, the clock for error correction operation can be made to have the same frequency as the received signal, and the signals on each working line appear to be not encoded with error correction codes.

Therefore, compared to the conventional method of inserting check bits on the main line, the transmission capacity can be increased if the clock frequency is the same, and the clock frequency used can be lowered if the transmission capacity is the same.

On the other hand, if either the working line or the protection line is abnormal, the error correction operation on the receiving side is prohibited, and if there is a failure in the working line, the signal of the faulty working line is transmitted via the protection line to prevent the failure. By rescuing the working line, the protection line can be used for its original purpose.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention, where +a) shows the transmitting side and (b) shows the receiving side.

Transmission (separately, when all working lines are free of faults, the baseband switch BB SW receives input signals 1 to N
is connected so as to be transmitted to N working lines 1 to N.

The signals of each line are converted from bipolar signals to unipolar signals through bipolar/unipolar converters B/U, and then converted from serial signals to parallel signals at serial/parallel converters S/P, and then modulated by modulators MOD. added to.

Each modulator MOD converts the input parallel signal into a multiphase multilevel signal, and each transmitter 'rχ thereby generates a radio frequency signal for the working lines 1 to N. These signals are combined via a multiplexer (not shown) and supplied to the antenna.

The error correction encoder FECENC is a serial/parallel converter S/P
A test bit is created for each channel according to the signals from each line. Check bit multiplexing unit CB
MIIX multiplexes the test bits of each working line into one channel of signals. On the other hand, the switch SW selects the check bit multiplexing unit CB? according to the control signal from the baseband switch BBSW. The multiplexed check bit signal from ItJX is applied between the modulators. The modulator MOD is
Converts the input signal into a multi-phase, multi-value signal similar to that of the working line.

This signal is converted to a radio frequency signal of the protection line P via the transmitter TX, combined with the signal of the working line via a multiplexer, and then supplied to the antenna.

FIG. 3 shows the transmission code structure during normal operation in the embodiment shown in FIG. 2, and shows the transmission code structure for channels 1, 2, .
..., information bits ■, ■, ...- in N, respectively.
2 [phase], ■゛, ■“, . −
Inspection bit mark 2 corresponding to 1■.

Figure 1 shows that +:n'', o', ..., etc. are multiplexed and sent out corresponding to the information bits There is.

In this case, the signals on each working line appear to be the same as those without error correction coding, and therefore the signals on each working line have the same clock frequency as when error correction coding is not performed. be.

On the receiving side, the signal from the antenna passes through a duplexer (not shown) and is separated into signals for the working lines 1 to N and signals for the protection line P. Each receiver Rx receives the signal of the respective line and inputs it to the demodulator OEM, and each demodulator DEM demodulates the input signal and reproduces the original parallel signal.

The demodulated signals of each of the working lines 1 to N are applied to the exclusive OR circuit EOR via the delay circuit DLY. On the other hand, the demodulated signals of each working line 1 to N and protection line P are applied in parallel to error correction decoding units FECDEC, FECDEC2.

The error correction decoding units FECDEC, FECDEC2 are as follows:
It operates alternately for each frame according to the control signal, and its output is switched through the selector SEL synchronously.
It is added to exclusive OR circuit EOR.

In each error correction decoding unit FECDEC, FECDEC2, check bits of each working line are taken out frame by frame from the demodulated signal of the protection line P, and the check bits of each working line are extracted from the demodulated signal of the protection line P to avoid syndromes. A calculation is performed to generate an error position detection signal. The exclusive OR circuit EOR performs an exclusive OR operation on the demodulated signal of each working line whose phase has been adjusted through the delay circuit DLY, using the error position detection signal for each channel added via the selector SEL. By performing calculations, error bits are corrected.

The error-corrected signal of each working line is converted from a parallel signal to a serial signal via a parallel/serial converter P/S to produce an output consisting of a unipolar signal. The unipolar/bipolar converter 11/B converts the unipolar signal input into a bipolar signal and outputs the bipolar signal, thereby generating N-channel output signals 1 to N via the baseband switch BI3 SW.

FIG. 4 explains the decoding procedure on the receiving side in the embodiment of FIG. 2. That is, the signals ■, ■゛, ■'' of any working line i and the corresponding test signals (Ci, Ci', C1'', -) of the protection line correspond to the time 1. and t, the error correction decoding unit FEC alternately
Error detection operation is performed in DEC, FECDEC2, and error correction decoding units FECDECI, FECD
EC2 alternately generates error position detection signals. Both signal outputs are applied to an exclusive OR circuit FOR via a selector SEL which is switched synchronously, thereby performing an error correction operation on the signals of each working line.

In this way, in the present invention, two systems of error correction decoding units are provided and operated alternately, so the same clock as that for the received data can be used for error correction decoding, and No need to compress data.

Note that the number of error correction decoding units is not necessarily limited to two systems, and a larger number may be provided and operated sequentially. Although the method of the present invention increases the number of circuits in the error correction decoding section, if an LSI circuit is used, there is no problem in terms of economy or space.

On the other hand, if there is a fault in any of the working lines, the baseband switch BB SW on the transmitting side switches the signal of the faulty line to the protection line.

At the same time, the switch is switched to the serial/parallel converter S/P side by a control signal, and the signal on the protection line is transferred to the modulator M.
By adding it to OD, the signal of the protection line is output as a radio frequency signal P. At the same time, on the receiving side, the signal on the protection line P is phase-adjusted via the delay adjuster DLY ADJ, and is added to the parallel/serial converter P/S, where it is converted from a parallel signal to a serial signal along with the signals on the remaining working line. Then, the signal is further converted from a unipolar signal to a bipolar signal via a unipolar/bipolar converter U/B, and is input to the baseband switch BBSH. As a result, N-channel signals 1 to N are generated from the baseband switch BB SW by adding the signal of the protection line P. At this time, the operation of the error correction decoding units FECDEC, FECDEC2 is prohibited, and the exclusive OR circuit EOR does not perform the error correction operation.

〔Effect of the invention〕

As explained above, according to the present invention, when the working line and the protection line are normal, the redundant bits of the error correction code are transmitted via the protection line, and the receiving side uses this to perform the error correction operation. In addition to improving line quality, when a line abnormality occurs, switching to a protection line for transmission allows the protection line to be used for its original purpose.

Furthermore, according to the present invention, a clock with the same frequency as the received data can be used as an error correction clock, so compared to conventional systems, if the clock frequency is the same, the transmission capacity can be increased, and with the same transmission capacity. If so, the clock frequency used can be lowered.

Furthermore, in the system of the present invention, if there is sufficient transmission capacity on the protection line, more powerful error correction can be performed by using a variable number of check bits or by using longer check bits.

[Brief explanation of the drawing]

1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a diagram showing the transmission code configuration in the embodiment of FIG. 2, FIG. 5 is a diagram illustrating a configuration example of a conventional wireless communication system, and FIG. 6 is a diagram illustrating a conventional transmission code configuration. BB SW---Baseband switch B/U---Bipolar/unipolar converter S/P---Series/parallel converter and 00---Modulator TX---Transmitter FECENC---Error correction encoder CB MUX' - One check bit multiplexing unit S Lee switch RX... Receiver DEM - Demodulator DLY ADJ - Delay adjuster DLY - Delay circuits FECDECl, FECDEC2 - Error correction decoding unit E
OR・-Exclusive OR circuit P/S--Single parallel/serial converter

Claims (1)

[Scope of Claims] A communication system in which one protection line is provided for a plurality of working lines, comprising: error correction encoding means (101) for converting signals of each working line into error correction codes; and each of the error correction codes. redundant bit multiplexing means (102) for multiplexing redundant bits in the redundant bit multiplexing means (102); first switching means (103) for switching the signal of the failed working line to the protection line; and the output of the redundant bit multiplexing means (102) and the a second switching means (104) for switching between the output of the first switching means (103) and outputting the output to the protection line; At least two systems of error correction decoding means (105) that perform error correction decoding on signals of each line, and the output of each error correction decoding means (105) is alternately switched for each frame and output to each working line. The receiving side is equipped with a first switching means (106) for switching the signal of the faulty working line transmitted via the protection line to the corresponding working line and outputting it. When all lines and protection lines are normal, each working line is encoded with error correction code, each redundant bit is transmitted via the protection line, and the receiving side performs error correction for each working line. An error correction method characterized in that the error correction operation is prohibited when any of the protection lines is abnormal.