JPS6350189A - Interpolating circuit for digital color video signal - Google Patents

Abstract

PURPOSE:To maintain a high frequency component without providing pre-filter and prevent occurrence of reflection distortion by providing a distortion removing circuit that replaces an interpolation value with a maximum value when the interpolation value is larger than the maximum value of color video data of plural picture elements and replaces with the minimum value when smaller than the minimum value. CONSTITUTION:The circuit is provided with an interpolating circuit 16 that interpolates color video data of specified picture elements by composing existent color video data around the specified picture elements and a distortion removing circuit 17 that is positioned around specified picture elements, and compares color video data of plural picture elements having the same phase of subcarrier with the specified picture elements and interpolation value of specified picture elements from the interpolating circuit 16, and replaces the interpolation value with a maximum value when the interpolation value is layer than the maximum value of color video data of plural picture elements, and replaces the interpolation value with a minimum value when the interpolation value is smaller than the minimum value of color video data of plural picture elements. Data of picture elements thinned by subsampling can be interpolated by data made by composing data of picture elements near the thinned picture elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interpolation circuit provided on the receiving side of a digital composite color video signal transmission system or on the reproducing side of a recording/reproducing system.

[Summary of the invention]

In the present invention, in a digital color video signal interpolation circuit for interpolating predetermined pixels whose data has been thinned out by subsampling or the like using existing color video data, existing color video data of pixels surrounding a predetermined pixel is used. The color video data of a predetermined pixel is interpolated, and this interpolated value is supplied to a distortion removal circuit. When there is no interpolated value within the level range of the maximum value and minimum value of the color video data of the plurality of pixels, the interpolated value is replaced with the maximum value or the minimum value, thereby preventing the occurrence of distortion.

[Conventional technology]

When transmitting a digital color video signal obtained by directly encoding an NTSC composite color video signal, subsampling is used to narrow the transmission band. By subsampling, for example, the data of the pixels are thinned out. When performing subsampling,
A bristle filter is provided to prevent the occurrence of aliasing distortion. On the receiving side, an interpolation circuit is used to interpolate the thinned out pixels.

[Problem that the invention seeks to solve]

A digital low-pass filter is known as a conventional interpolation circuit. However, in the case of a composite color video signal in which a carrier color signal is superimposed on a luminance signal, it is difficult to apply conventional interpolation filters because it is necessary to consider the phase of the carrier color signal.

Furthermore, when a bristle filter is used, there is a problem in that high-frequency components of the color video signal are lost.

An object of the invention is to provide an interpolation circuit designed in the time domain that can be applied to composite color video signals.

Another object of the present invention is to provide an interpolation circuit for a digital color video signal that can preserve high frequency components of a color video signal and prevent generation of aliasing distortion without providing a bristle filter.

[Means for solving problems]

In the digital color video signal interpolation circuit according to the present invention, the digital color video signal interpolation circuit interpolates the color video data of a predetermined pixel between the existing color video data and the corresponding pixel using the existing color video data. , an interpolation circuit 16 that interpolates color video data of a predetermined pixel by combining existing color video data around the predetermined pixel; compares the color video data of a plurality of pixels with the same value and the interpolated value of a predetermined pixel from the interpolation circuit 16, and when the interpolated value is larger than the maximum value of the color video data of the plurality of pixels, replaces the interpolated value with the maximum value. However, a distortion removal circuit 17 is provided which replaces the interpolated value with the minimum value when the interpolated value is smaller than the minimum value of the color video data of a plurality of pixels.

[Effect]

Since a telephoto image has a correlation in the horizontal direction (sample direction) and vertical direction (line direction), the data of pixels thinned out by subsampling is processed by the interpolation circuit 16 into data of pixels in the vicinity of the thinned out pixels. can be interpolated using the synthesized data. This interpolation circuit 1
6 can perform interpolation of composite color video signals, unlike conventional digital low-pass filters.

Furthermore, no bristle filter is provided before subsampling, and high frequency components of the color video signal are preserved. On the receiving side, aliasing distortion may occur and as a result, the interpolated value may be distorted, but the distortion removal circuit 17 can remove visually noticeable distortion. In other words, in the distortion removal circuit 17, for example, data x1 of four pixels in the vicinity where the color subcarriers are in the same phase.
x4 and the interpolated value 2° are compared, and the interpolated value father is obtained. When is the maximum, the interpolated value father. is replaced with the maximum value in the data xlxx, and the interpolated value is replaced. When is the minimum, the interpolated value 9° is replaced with the minimum value in the data X+''-X4.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description is given in the order of the items below.

a, Configuration of the transmitting side, Configuration of the receiving side C, Blocking circuit d, Dynamic range extraction circuit e, Quantization circuit f, Interpolation circuit g, Distortion removal circuit, Modification a, Configuration of the transmitting side No. FIG. 1 shows the overall configuration of the transmitting side (recording side). For example, an NTSC color video signal is supplied to an input terminal indicated by 1. This color video signal is supplied to the A/D converter 2, for example, 4 fsc (fsc
A digital color video signal is obtained from the A/D converter 2, in which one sample is quantized to 8 bits at a sampling frequency of 0.01, 0.01, 0.01, 0.01, 1.00, 0.000000000000000 (color subcarrier frequency), and 1 sample is quantized to 8 bits. This digital color video signal is supplied to a sub-sampling circuit 3, and the output signal of the sub-sampling circuit 3 is supplied to a blocking circuit 4. No band-limiting filter is provided before the sub-sampling circuit 3, and high-frequency components of the input color video signal are not lost.

In the sub-sampling circuit 3, the digital color video signal is sampled at a sampling frequency of 2 fsc. Further, the blocking circuit 4 converts the input digital television signal into a continuous signal for each two-dimensional block, which is a unit of encoding. In this example,
One block formed by dividing the screen of one field is (4
The size is 32 pixels (line x 8 pixels = 32 pixels). FIG. 3 shows this l block. In FIG. 3, solid lines indicate odd field lines and broken lines indicate even field lines. The present invention can also be applied to a three-dimensional block composed of four two-dimensional regions belonging to .

The sub-sampling circuit 3 provided before the blocking circuit 4 thins out the pixels in the block as shown in FIG. 4, so that the number of pixels in one block is 16.

In FIG. 4, ◯ indicates pixels that have been subsampled, and × indicates pixels that have been thinned out.

The output signal of the blocking circuit 4 is supplied to a dynamic range detection circuit 5 and a delay circuit 6. The dynamic range detection circuit 5 detects the dynamic range DR for each block.
and detect the minimum value MIN. The pixel data PD from the delay circuit 6 is supplied to a subtraction circuit 7, and the subtraction circuit 7 forms pixel data PDI from which the minimum value MIN has been removed.

The quantization circuit 8 includes a subsampling circuit and a subtraction circuit 7.
The pixel data PDT and dynamic range DR after minimum value removal are supplied via the pixel data PDT and the dynamic range DR.

The quantization circuit 8 quantizes the pixel data PDI in accordance with the dynamic range DR. A code signal DT in which one pixel data is converted into 4 bits is obtained from the quantization circuit 8.

The code signal DT from this quantization circuit 8 is supplied to a frame formation circuit 9. The framing circuit 9 is supplied with a dynamic range DR (8 bits) and a minimum value MIN (8 bits) as additional codes for each block. The framing circuit 9 performs error correction encoding processing on the code signal DT and the above-mentioned additional code, and also adds a synchronization signal. Transmission data is obtained at the output terminal 10 of the framing circuit 9, and this transmission data is sent out to a transmission path such as a digital line. In the case of a digital VTR, an output signal is supplied to a rotary head via a recording amplifier, a rotary transformer, etc.

b. Receiving side configuration FIG. 2 shows the configuration of the receiving (or reproducing) side.

The received data from the input terminal 11 is sent to the frame decomposition circuit 1.
2. The frame decomposition circuit 12 separates the code signal DT from the additional codes DR and MIN, and also performs error correction processing. The code signal DT is supplied to the decoding circuit 13, and the dynamic range DR is supplied to the decoding circuit 13.

The decoding circuit 13 performs processing opposite to the processing of the quantization circuit 8 on the transmitting side, that is, the data after the 8-bit minimum level is removed is decoded to the representative level, and this data and the 8-bit minimum value M I N is added by the adder circuit 14, and the original pixel data is decoded.

Output data of the adder circuit 14 is supplied to a block decomposition circuit 15. The block decomposition circuit 15 is a circuit for converting the decoded data of the block order into the same order as the scanning of the television signal, contrary to the block northward B4 on the transmitting side. The output signal of the block decomposition circuit 15 is transmitted to the interpolation circuit 16.
supplied to

In the interpolation circuit 16, the data of the thinned out pixel is
interpolated by sub-sample data.

A digital color video signal with a sampling frequency of 4 fsc from the interpolation circuit 16 is supplied to the distortion removal circuit 17. The output signal of the distortion removal circuit 17 is supplied to the D/A converter 18. An analog color video signal is obtained at the output terminal 19 of the D/A converter 18. If a bristle filter is not provided on the transmitting side, aliasing distortion may occur, for example, at a point where the brightness level changes sharply, and the interpolated value may be greatly distorted.

This distortion is removed by the distortion removal circuit 17.

C. Blocking Circuit The blocking circuit 4 will be explained with reference to FIGS. 5, 6, and 7. For the sake of explanation, it is assumed that the L field screen has a configuration of (4 lines x 8 pixels) as shown in Figure 6, and this screen is divided into two vertically and horizontally as shown by the broken lines. A case will be described in which the image is divided into four in the direction and eight blocks (2 lines x 2 pixels) are formed.

In FIG. 5, as shown in FIG. 7A, the input terminal indicated by 21 is supplied with input data A consisting of four lines (T h o to Th,), and the input terminal indicated by 22 is supplied with input data A and the like. Synchronized sampling clock B (Fig. 7 B)
) is supplied. The numbers (1 to 8) are the line T he
The numbers (11 to 18) show the sample data of the line Th, respectively, and the numbers (2
1 to 28) respectively indicate sample data on line Th, and numbers (31 to 38) indicate sample data on line Th3, respectively.Input data A is delay circuit 23 and 27s (Ts: sampling A delay amount of (period) is supplied to the delay circuit 24. Further, the sampling clock B is supplied to the A frequency dividing circuit 27.

The output signal C (FIG. 7C) of the delay circuit 24 is supplied to one input terminal of the switch circuits 25 and 26, respectively, and the output signal D (FIG. 7D) of the delay circuit 23 is supplied to the other input terminal of the switch circuits 25 and 26. are supplied to the input terminals of the respective input terminals. The switch circuit 25 is controlled by the output signal E (FIG. 7E) of the A frequency dividing circuit 27, and the switch circuit 26 is controlled by a pulse signal obtained by inverting the pulse signal E by an inverter 28. The switch circuits 25 and 26 alternately select the input signal (C or D) every 2Ts. The output signal F from the switch circuit 25 is shown in FIG. 7F, and the output signal G from the switch circuit 26 is shown in FIG. 7G.

The output signal F of the switch circuit 25 is connected to the first input terminal of the switch circuit 29 and the delay circuit 30 has a delay amount of 4Tl.
supplied to The output signal G of the switch circuit 26 is 2Ts
The signal is supplied to a delay circuit 31 having a delay amount of . The output signal H of the delay circuit 30 (H in FIG. 7) is supplied to the third input terminal of the switch circuit 29. The output signal (■) of the delay circuit 31 (FIG. 7) is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 4Ts. The output signal J (FIG. 7J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the frequency divider 27 is supplied to the A frequency divider 33, and an output signal K (K in FIG. 7) is formed. The switch circuit 29 is controlled by this signal K, and the first . Second. The third and fourth input terminals are sequentially selected.

Therefore, the signal output from the switch circuit 29 to the output terminal 34 is as shown in the seventh diagram. That is, the order of each field of data is converted to the order of each block (for example, 1→2→11→12). Of course, the actual number of pixels in the l field is much larger than in the example shown in FIG. 6, but it is converted into the block-by-block order shown in FIG. 3 by scan conversion similar to that described above.

d. Dynamic Range Detection Circuit FIG. 8 shows the configuration of an example of the dynamic range detection circuit 3. The input terminal designated by 41 receives encoding data for each block from the blocking circuit 4 as described above. Image data of the required area is sequentially supplied. Pixel data from this input terminal 41 is supplied to a selection circuit 42 and a selection circuit 43. The - selection circuit 42 selects and outputs the one with a higher level between the pixel data of the digital color video signal and the output data of the latch 44.

The other selection circuit 43 selects and outputs the one with a smaller level between the pixel data of the input digital color video signal and the output data of the latch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is taken into the latch 44. The output data of the 0 selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and is taken into the latch 45. Latches 44 and 45
A latch pulse is supplied from the control section 49. The control unit 49 is supplied from a terminal 50 with timing signals such as a sampling clock and a synchronization signal that are synchronized with the digital color video signal. The control unit 49 has a latch 44.4.
5 and latches 47 and 48 at predetermined timing.

At the beginning of each block, the contents of latches 44 and 45 are initially set. The latch 44 is initialized with data of all "0", and the notch 45 is initialized with data of all 1. Among the sequentially supplied pixel data of the same block, the maximum level is stored in the latch 44. Furthermore, among the pixel data of the same block that is sequentially supplied, the minimum level is stored in the latch 45.

When the maximum level and minimum level detection is completed for one block, the maximum level of the block appears at the output of the selection circuit 42. On the other hand, the output of the selection circuit 43 produces the minimum level of the block.

When the detection for the l block is completed, latches 44 and 45 are reinitialized.

The dynamic range DR of each block is obtained from the output of the subtraction circuit 46 by subtracting the maximum level MAX from the selection circuit 42 and the minimum level MIN from the selection circuit 43. These dynamic range DR and minimum level MIN are controlled by the latch pulse from the control block 49.
They are latched by latches 47 and 48, respectively. The dynamic range DR of each block is obtained at the output terminal 51 of the latch 47, and the minimum value MIN of each block is obtained at the output terminal 52 of the latch 48.

e. Quantization circuit The quantization circuit 8 performs encoding adapted to the dynamic range DR. FIG. 9 shows an example of the quantization circuit 8. In FIG. 9, the ROM indicated by 55 stores a data conversion table for converting the pixel data PDr (8 bits) after minimum value removal into a compressed focus number, for example, 4 bits.

The dynamic range DR from the input terminal 56 and the pixel data PDI from the input terminal 57 are supplied to the ROM 55 as address signals. In the 80M55, a data conversion table is selected depending on the size of the dynamic range DR, and a 4-bit code signal DT is sent to the output terminal 58.
is taken out.

In the quantization circuit 8, the code signal DT is 2 bits (
In the embodiment, in the case of 4 bits), the dynamic range DR of the block is divided into four regions as shown in FIG. These four areas are (00) (01) (10)
Distinguished by the 2-bit code signal DT in (11),
Central level LO.

LL, L2. L3 is the representative level of each area.

2 depending on the area containing the data PDI after minimum value removal
A bit code signal DT is generated.

The level of the digital color video signal has a correlation within the block even if the digital carrier color signal is superimposed, and the dynamic range DR of each program is concentrated in a narrow range in the stationary part that is not the transient part. are doing. Therefore, there is almost no deterioration in image quality even when quantizing with a bit number compressed to 2, such as 4 bits.In addition, since each pixel is encoded independently from other pixels, the digital color video signal It is possible to reproduce the rapid level changes of
Frequency characteristics can be improved compared to DPCM.

Note that pixel data having the respective levels of the fit small level MIN and the maximum level MAX always exist within one block. Therefore, in order to increase the number of code signals with an error of O, as shown in FIG.
Divide into (2″′″-1) (where m is the number of quantization bits), and let the minimum level MIN be the representative minimum level LO,
The maximum level MAX may be set as the representative maximum level L3.

In addition to the ROM, the quantization circuit 8 also includes a divider for dividing the dynamic range DR and a data PD after minimum value removal.
A configuration including a comparison circuit for determining the level area to which I belongs may be used.

C1 interpolation circuit FIG. 12 shows an example of the interpolation circuit 16. In FIG.
Digital color video data (real data) is provided from. Data X of four pixels used for interpolation in the peripheral pixel extraction circuit 61. +X! 0+
X30*x4° is taken out. The peripheral pixel extraction circuit 61 includes two line delay circuits and a plurality of sample delay circuits.

Figure 13 shows the pixel of interest (data xo) to be interpolated.
This shows the positional relationship between the pixel and the surrounding pixels. Since the sampling frequency is selected to be 4 fsc, four phases (represented by OΔ·mu) are periodically repeated with respect to the phase of the color subcarrier. The phases of the color subcarriers ○ and . and the phases of the color subcarriers Δ and m are opposite in phase. Data of pixels adjacent to the top, bottom, left and right of the pixel of interest X l@+ X R*+ X 31
1+×40 is used for interpolation. In addition, data xl + of four pixels located diagonally to this pixel of interest and whose color subcarrier phase is the same as that of the pixel of interest.
X t and X 2+ x4 are used for distortion removal, which will be described later.

Data X from the peripheral pixel extraction circuit 61. and X-hui. is supplied to the adder circuit 62, and the output signal of the adder circuit 62 is supplied to the adder circuit 68. Additionally, the peripheral pixel extraction circuit 61
The data xao and x4° are supplied to % multiplier circuits 63 and 64, respectively, which are constituted by shift registers. The output signals of these A multiplier circuits 63 and 64 are supplied to an adder circuit 67 via inverters 65 and 66, respectively. The output signal of the adder circuit 68 is the interpolated value. It is then taken out to the output terminal 69.

In the interpolation circuit 16 described above, the interpolation value father. is determined by the following formula.

9 o =Xto+Xto+'A(-Xsa Xao
) Data X1ll to X4 due to correlation of television images
° is expressed as follows.

x, o=Y+C' Xzo==Y C-x,. =
Y-Cx4. , -Y-c (Y: luminance signal component, C, C': @ fading signal component) Therefore, the interpolated value father. is, 9゜= (y+C')+ (Y-C')+%(Y+CY
+C) = 2Y+ (-Y+C) = Y+C Note that a number other than four surrounding pixels can be used for interpolation.

g. Distortion Elimination Circuit An example of the distortion elimination circuit 17 will be explained with reference to the 14th episode. In FIG. 14, a 0 peripheral pixel extraction circuit 72, to which existing color video data is supplied from an input terminal 71, is connected to a peripheral pixel extraction circuit 72, as shown in FIG. Pixel data X l , X t which are located diagonally to the interpolated data 9° and whose color subcarrier phase is the same as the interpolated data 9°
* ” !+ Extract X4. Data X and x are supplied to a comparison circuit 73, a selection circuit 74 and a selection circuit 75, respectively, and data X3 and x4 are supplied to a comparison circuit 77, a selection circuit 78 and a selection circuit 79, respectively. Selection circuit 74
The output signal of the selection circuit 78 and the output signal of the selection circuit 78 are
and a selection circuit 82, respectively, and an output signal of the selection circuit 75 and an output signal of the selection circuit 79 are supplied to a comparison circuit 83 and a selection circuit 84, respectively.

Comparison circuits 73, 77, 81, and 83 compare the levels of the two input signals and generate an output signal of 10' or "1" depending on the magnitude relationship of the levels.

By the output signal of this comparison circuit, the selection circuit 74°75
．． 78.79.82.84 state is controlled. The selection circuit 74 selects the data with a higher level between the data X and x2, and the selection circuit 78 selects the data with a higher level between the data X and x4. The 0 selection circuit 75 supplies data
, and 2, the data with the smaller level is selected, and the selection circuit 79 selects the data with the smaller level among the data X and x4.

Among the output signals of selection circuits 74 and 78, the output signal having a higher level is selected by selection circuit 82. Therefore, the selection circuit 82 outputs the data having the maximum value among the data X, to x4. Further, the output signal of the comparison circuit 83 is supplied to the selection circuit 84 via the inverter 85, and the output signal of the lower level among the output signals of the selection circuits 75 and 79 is selected by the selection circuit 84. Therefore, the data having the minimum value among the data X, to x4 is output from the selection circuit 84.

The maximum value outputted from the selection circuit 82 and the interpolated value 9° from the terminal 70 are supplied to a comparison circuit 86, and the minimum value and interpolated value outputted from the selection circuit 84 are supplied to the comparison circuit 86.

is supplied to the comparison circuit 87. These comparison circuits 86
and 87 are supplied to a decoder 88. In the decoder 88, a 0 selection circuit 8°9 that generates a control signal for the selection circuit 89 is supplied with an interpolated value 9o, maximum value data, and minimum value data.

A selection circuit 89 is controlled by a control signal generated by a decoder 88. That is, interpolation (Il!Q.

is within the level range from the minimum value to the maximum value of the data X, xX, this interpolated value is selected by the selection circuit 89, and the interpolated value odor. is smaller than the minimum value of data X1 to x4, interpolated value history.

is replaced with the minimum value, and furthermore, the interpolated value 9° is the data X, ~
When it is larger than the maximum value of x4, the interpolated value 9° is replaced with the maximum value. The output signal of this selection circuit 89 is taken out to an output terminal 90 as an output signal of the distortion removal circuit 17.

The interpolation circuit 16 can be realized by a simple circuit configuration as shown in FIG. When aliasing occurs, the decoded data at the receiving end is distorted, resulting in an interpolated value history. The above-mentioned distortion removal circuit 1 also distorts like impulse noise.
7, the distorted interpolation value is replaced with the maximum value or minimum value of the neighboring data, so that the distortion can be made less noticeable.

h. Modifications The ninth invention can be applied not only to fixed length encoding methods but also to variable length encoding methods as an encoding method adapted to a dynamic range. In variable length encoding,
The dynamic range DR for each block is divided by a quantization step corresponding to a predetermined quantization distortion, that is, the dynamic range DR is divided into a number of level ranges adapted to the dynamic range DR, and the data after minimum value removal is A code signal is formed that corresponds to the level range to which it belongs.

In the above explanation, the code signal DT, dynamic range DR, and minimum value MIN are transmitted.

However, instead of the dynamic range 080, the maximum value MAX, quantization step, or maximum distortion may be transmitted as the additional code.

Furthermore, subsampling may be performed after the input signal is processed into blocks. Furthermore, one block of data may be taken out simultaneously by a circuit that combines a frame memory, a line delay circuit, and a sample delay circuit.

〔Effect of the invention〕

Since this invention is designed in the time domain, it can be applied even when the sampling frequency is different, and it can also be applied to composite color video in which a carrier chrominance signal is superimposed on a luminance signal, which is difficult to do with conventional interpolation filters. It has the advantage that signals can be interpolated. In addition, in this invention,
High frequency components of the transmitted color video signal can be preserved without providing a burry filter before subsampling. In this case, aliasing distortion may occur, but visually noticeable distortion can be removed by the distortion removal circuit provided on the receiving side.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the transmitting side of a color video signal transmission system to which this invention can be applied, Fig. 2 is a block diagram showing the configuration of the receiving side, and Fig. 3 is an explanation of blocks that are units of encoding processing. Figure 4 is a route map used to explain subsampling, Figures 5, 6, and 7 are block diagrams of an example of a blocking circuit, route maps used to explain it, and explanations of its operation. Fig. 8 is a block diagram of an example of a dynamic range detection circuit, Fig. 9 is a block diagram of an example of a quantization circuit, and Fig. 10 is a block diagram of an example of a quantization circuit.
11 is a route map used to explain one example of quantization and another example, FIG. 12 is a block diagram of an example of an interpolation circuit, FIG. 13 is a route map used to explain peripheral pixels, and FIG. 14 is a route map used to explain an example of quantization and another example. FIG. 2 is a block diagram of an example of a distortion removal circuit. Explanation of main symbols in the drawings 1: Color video signal input terminal, 4 Niblock decomposition circuit, 5: Dynamic range detection circuit, 7: Subtraction circuit, 8: Quantization circuit, 13; Decoding circuit, 15 Niblock decomposition circuit. Circuit, 16: Interpolation circuit, 17; Distortion removal circuit.

Claims (1)

[Scope of Claims] A digital color video signal interpolation circuit for interpolating color video data of a predetermined pixel between the existing color video data and the corresponding pixel using the existing color video data; an interpolation circuit that interpolates the color video data of the predetermined pixel by synthesizing the existing color video data around the predetermined pixel; The color video data of the same plurality of pixels is compared with the interpolation value of the predetermined pixel from the interpolation circuit, and when the interpolation value is larger than the maximum value of the color video data of the plurality of pixels, the interpolation value is and a distortion removal circuit that replaces the interpolated value with the minimum value when the interpolated value is smaller than the minimum value of the color video data of the plurality of pixels. interpolation circuit.