JPS6349925A - Constituting method for rapid pattern matching gate array - Google Patents

Abstract

PURPOSE:To execute binary and quaternary pattern matching with rapid response time only by one transistor by considering the property of matching operation at a gate level and executing all matching operations by complete parallel processing. CONSTITUTION:In a production system (PS), knowledge is described by if-then type and constituted of a condition part and an action part. The PS executes pattern matching between work memory (WM) for storing external information and the condition part of respective rules (PR), selects one of the rules succeeded in matching and executes the action part. A question is solved by repeating the recognition-action cycle. In the pattern matching, the condition part of a PR matched with the contents of the WM is rapidly detected. In order to attain rapid matching, complete parallel type architecture is adopted and the contents of the WM and PR are coded to binary and quaternary numbers.

Description

Detailed Description of the Invention Pattern matching is one of the most basic and important operations in fields such as knowledge information processing systems where data is non-numeric. In a problem solving system called PS, more than 90% of the processing cycle is spent on pattern matching.

By the way, knowledge information processing systems do not require any processing flow to be described, so they do not require specialized knowledge of programming, and are characterized by being strong against gradual development and modification of programs (sets of rules). Therefore, it is considered suitable for application to system control where control methods are frequently changed, but as the scale of the system to be controlled increases, the number of conditions to be specified in rules and the total number of rules increase. Processing time becomes enormous.

In other words, in order to apply knowledge information processing to real-time processing systems such as system control, it is considered necessary to perform pattern matching at high speed and to minimize the amount of data matching possible.

First, an overview of PS related to the present invention will be explained.

In PS, knowledge is described in the following 1f-then type.

C engineering △C2△・・・△CA (1) However, C engineering △C2Δ...△C□ is the condition part, and A is the action part. P
In S, pattern matching is performed between the part called work record ta (WM) that records information from the outside and the condition part of each rule (PR), one of the rules that has been successfully matched is selected, and the Problem solving occurs through the reversal of the recognition-action cycle, which involves carrying out the action part. High-speed pattern matching is to detect at high speed which PR condition part the content of WM matches. In order to speed up the matching, this configuration employs a fully parallel architecture6. However, a configuration based on a fully parallel architecture tends to increase the amount of circuit hardware. In the following, a method of encoding WM and PR into binary and quaternary values will be described in order to reduce the amount of hardware required for the part that performs matching.

(Encoding for pattern matching) First, consider encoding of working memory. In WM, information regarding the existence of element C in the condition part of each rule
Convert value. (However, x1ε (0, 1)) Now, two adjacent elements in WM c21-1"2□
In order to combine the information about Mu - 0 and X2□ into one, the four-valued decoding table spell X□ is defined as follows.

The binary embossing table spell y and the four-value embossing expression Y of each production rule can also be defined in the same way as the above-mentioned X□ and X engineering.

(Formulation of pattern matching) From the diagram shown in FIG. 1, which shows the matching results for each corresponding element between WM and PR that have been subjected to quaternary encoding, the following relationship is expressed by 4.

(i) When Yε (0, 2, 3), Yi3 (4) ζ=Xi (11) ME: When (1), Ui""21-1 However, Ui is Indicates the result of matching the ii-th element converted into a four-value code,
X□ represents the value of WM after four-value encoding, and "21-1" represents the value of WM before four-value encoding.

Note that xab is a literal and is defined as follows. (However, a, bE L = (0, 1, 2, 3)
) Based on the above definition, the matching result W of the h-th rule is generally formulated as follows.

See = U-work△bow△・ ・ ・△U,
(6) = , ;m3... Eight balls... △x: n3
Part of c condition (+) △・2. , △...△・2. −
0△...△" 2n-E Partial part of condition (ii) However, s
l+ 1''+ ''+ IIl+ no '* J is any natural number, and 1≠j.

The matching result for each corresponding element between WM and PR that has been converted into binary encoding is shown in Figure 2. From Figure 1, the matching result V□ between the i-th element that has been converted into binary encoding is as follows. It can be defined as

v1=to△y□ (7) However, the value of ■□ has the meaning shown below.

From the above formula, in general, the matching result W5 of the h-th rule
In the case of binary encoding, the formula “+1=vl
Δv91\... △vn (9)=
(x work△y work)△ (X2△y2) Δ・ ・ ・△
(xnAyn) (Configuration of gate array for high-speed pattern matching) First, the configuration of the gate array for four-value pattern matching will be described. The four-value pattern matching is given as follows.

However, ye (Q, 2.3) X□1 is the threshold that changes depending on the rule value Y□.
For example, by associating the four-value symbol and the voltage value as shown in FIG. 3, it can be realized as shown in FIG. 4. Note that the logical threshold values of transistors Tr and I in the figure are determined by the logical value of Yl (
0, 2, 3), respectively (-0, 5, 1, 5,
2, 5).

Next, the logical product △ connects transistors by the number of product terms as Tr,
By making a wired OR connection in parallel with l, Figure 5
This can be easily accomplished as follows.

If X is also associated with the voltage value as shown in Fig. 6, it can be realized in the same way as the circuit in Fig. 4. Therefore, the entire configuration of the 4-value pattern matching part is in the form of a gate array as shown in Fig. 7. , Decision Table, which organizes and provides rules in a table format.
The configuration is similar to that of the e method modified by 'X' at the gate level. However, two inputs x2i-□ and X are sent to each transistor from the WM and the encoder, and one of them is selected depending on the value of Y.

In order to perform binary pattern matching, it is sufficient to realize equation (9) in the same way as in the case of four values.

A gate array for binary pattern matching is constructed as shown in FIG. Note that in the case of a binary configuration, the threshold voltages of the transistors Tr and i in FIG. 4 are < s, ov, respectively, depending on the logical value (0, 1) of y□.

2.01/).

(Effects of the Invention) In the gate array of the present invention, binary and quaternary pattern matching can be performed with a single transistor by considering the characteristics of matching operations at the gate level. In addition, since all verifications are configured to be processed completely in parallel, all verifications can be performed in the response time (several Ions) for one game, and the circuit's VL
It is extremely suitable for SI. Furthermore, the transistor arrangement remains unchanged.

By simply replacing the ion mask during the manufacturing process, rules can be freely set according to specifications.

[Brief explanation of drawings]

FIG. 1 shows a truth table when WM and PR are matched in a four-value pattern. Figure 2 shows WM and PR
This shows a truth table when binary pattern matching is performed. FIG. 3 shows the correspondence between four-value logical values and voltage values. FIG. 4 shows a circuit diagram in which the literal XT13 is composed of NMOS transistors. Figure 5 shows
A circuit diagram for realizing the logical product Δ is shown. Figure 6 shows W
It shows the correspondence between binary logical values from M and voltage values. FIG. 7 shows an overall diagram of a gate array for four-value pattern matching. FIG. 8 shows an overall view of the gate array for binary pattern matching.

Claims (3)

[Claims] (1) A method of encoding input signals into binary and quaternary values to perform binary and quaternary pattern matching. (2) A method of realizing binary and quaternary pattern matching using a pass transistor whose threshold voltage is controlled by multi-level ion implantation technology, based on the encoding method according to claim 1. (3) Based on the method for realizing pattern matching recited in claim 2, a binary and How to configure a 4-level gate array.