JPS6346879A - Sampling and holding circuit - Google Patents

Abstract

PURPOSE:To protect an IC from electrostatic destruction and eliminate a step of DC level by providing a protective resistance in a prescribed position in case a circuit is made into the IC. CONSTITUTION:Protective resistors R2 and R3 are connected in series between collectors of transistors TRs Q3 and Q5 and the base of a TR Q7, and a capacitor C1 is connected to the connection middle point of resistors R2 and R3 through a terminal T1. Thus, a blanking level Eb of a luminance signal S2 is clamped at a reference voltage Ec. Even if static electricity is supplied to the terminal T1, it is stopped by resistors R2 and R3 to protect TRs Q3, Q5, and Q7.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a sample and hold circuit.

[Summary of the invention]

This invention enables a sample-hold circuit such as a clamp circuit to protect the IC from electrostatic damage by connecting a protective resistor to a predetermined location when it is integrated into an IC, without deteriorating its original characteristics. This is how it was done.

[Conventional technology]

A feedback clamp circuit used in a video camera or the like is configured as shown in FIG. 2, for example.

That is, in the figure, a differential amplifier fl) is constituted by transistors Q1 and Q2 and a constant current source Q11, and a luminance signal S+ is supplied to the base of the transistor Q1 from a pre-stage circuit (11) such as a preamplifier. This signal S
1 is a luminance signal whose white level is in the positive direction and which does not have a synchronization pulse, for example, as shown in the figure.

Then, a luminance signal S2 having the same polarity as the signal S1 and having a blanking period level of value Eb is extracted from the collector of the transistor Q2, and this signal S2 is supplied to a subsequent circuit (12) such as a gamma correction circuit. .

In addition, the emitters of transistors Q3 and Q4 are connected to each other and to a constant current source Q13 through the collector and emitter of a switching transistor Q8 to form a differential amplifier (2). A reference voltage Ec is supplied, and the base of transistor Q4 is supplied to the collector of transistor Q2.

Furthermore, a current mirror circuit (3) is configured by transistors Qs and Qs with the power supply line as a reference potential point,
The collectors of the transistor Q6 on the input side and the transistor Q5 on the output side are connected to the transistor Q4. Each is connected to the collector of Q3.

Further, transistor Q7 is made an emitter follower from constant current source Q12, and its base is connected to transistor Q3 +
It is connected to the collector of Qs, its emitter is connected to the base of transistor Q2, and the base of transistor Q7 is connected to capacitor C1 through protection resistor R□ and terminal T1.

Further, the emitters of the transistors Qs, Qs are connected to the constant current source Q-, 3, and the signal source (13) turns on the transistor Q8 during the blanking period and turns off the transistor Q9, and turns on the transistor Q9 during the scanning period. The clamp pulse P c + P c that turns off Q11 and turns on transistor Q9 is applied to transistors Qs and Qs.
supplied to the base of

Note that the above circuit has a capacitor C as shown by the chain line.
All but one IC (10) are integrated into one IC (10), and the capacitor C1 is connected to the IC (10) through an external pin terminal T.
0) is attached externally.

Therefore, in the blanking period, the pulse Pc,
Since the transistor Q8 is turned on by Pτ, the differential amplifier (2) becomes active, and the voltage Ec is compared with the blanking level Eb of the signal S2.

In this case, if (3) to (5) are the collector currents of the transistors Q3 to Q5, then when the level Eb rises and Ec<Eb, 13<14 and the current mirror circuit (3
), since l5=rnow, 13<15, and the difference current (Is I3) flows from the transistor Q5 to the capacitor C1, charging the capacitor C1 and increasing the terminal voltage E1. Since this voltage E1 is supplied to the base of the transistor Q2 through the transistor Q7, at this time, the collector potential of the transistor Q2, that is, the level Eb of the signal S2 decreases.

On the other hand, when the level Eb of the signal S2 falls and Ec>Eb, contrary to the above, 73>IS, so the difference current (I3-15) flows from the capacitor C1 to the transistor Q.
3, and its terminal voltage E1 decreases. Therefore, the base potential of transistor Q2 also decreases, causing a signal of "9".
The level Eb of S2 increases.

Therefore, the level Eb of the signal S2 converges toward the reference voltage Ec and becomes stable at Eb=Ec.

Then, such an operation is performed every blanking period, and during the scanning period, the pulses Pc and Pc turn off the transistor Q8 and turn off the transistors Q3 to Qs, so the blanking level Eb of the brightness signal S2 is , will be clamped or held to the reference voltage Ec.

Therefore, this circuit acts as a clamp circuit, ie, a sample and hold circuit.

In this case, when handling IC<10), if the terminal T1 is touched by a hand, static electricity is supplied to the transistors Q3, Qs, and Qv through the terminal T1 as shown by the broken line, and the transistor Q3 + Qs rQ7 is destroyed. However, this IC (10) has a built-in resistor R1 that blocks static electricity from flowing through the terminal T1, so even if you touch the terminal T1, the transistor Q3. QS and Q7 are not destroyed by static electricity.

[Problem that the invention seeks to solve]

However, in this clamp circuit, during steady state,
Since Ec = Eb, l3 during the blanking period
= ISO, and at this time, the capacitor C1 should not be charged or discharged.

However, in reality, the current I4 is connected to the current mirror circuit (3
), resulting in a current I5, so that a delay period j1+L2 due to the current mirror circuit (3) occurs in the current Is with respect to the current I3, as shown in FIGS. 3A and 3B.

Then, during the rising delay period t1, I3<Is, and during the falling delay period t2, I3<Is, so even if Ec = Eb, the capacitor C
1, a pulsed charging/discharging current 1p as shown in FIG. 1C flows during period ti+j2.

This current rp also flows through the resistor R1, so
A pulse voltage Ep having the same waveform as the current generator p is generated in the resistor R1, and this is generated in the transistor Q? .

It is added to the signal S2 through Q2.

In addition, during the blanking period, when Eb is Eb, a clamp current, that is, a differential current (Is I3), flows through the capacitor C1, but this differential current also flows through the resistor R1 at the same time, and the resistor R1 is Generates a voltage drop proportional to the difference current. Therefore, resistor R1 and capacitor C1
Because of the time constant, when Eb has not converged to Ec at the start of the scanning period, the voltage drop across resistor R1 causes a step in the base potential of transistor Q7, and therefore, a step in the DC level occurs in signal S2. will occur.

This invention attempts to solve these problems.

[Means for solving problems]

Transistor Q3. Collector of QS and transistor Q
A protective resistor R2゜R3 is connected in series between the base of the resistor 7 and the terminal T
1 through which the capacitor C1 is connected.

[Effect]

The influence of the delay of the current I5 and the clamp current is eliminated.

〔Example〕

In FIG. 1, transistor Q3. A protective resistor R2 is connected between the collector of Q5 and the base of transistor Q7.
, R3 are connected in series, and the capacitor C1 is connected to the resistor WR2 through the terminal T1.

Connected to the connection midpoint of R3.

Furthermore, - as an example, R2=R3=100Ω CL = 0.1μF τ=R2C1=10μs R41/16kHz It is.

According to such a configuration, the luminance signal S
The blanking level Eb of No. 2 is clamped to the reference voltage Ec.

〔Effect of the invention〕

In this case, even if static electricity is supplied to the terminal T1,
This is blocked by resistors R2, R3 and transistor Q 31 Q s r Q ? These transistors Ql, Qs, and Q7 are protected from static electricity.

Also, the delay period t1+t2 of the current I5 with respect to the current 13N
Even if an attempt is made to generate a pulse current Ip by
Since R2 and capacitor C1 constitute a low-pass filter, no pulse voltage Ep is generated in capacitor C1. At this time, the base current of the transistor Q7 is sufficiently small and can be ignored, and the 70 transistors directly take in the terminal voltage of the capacitor c1, so the pulse voltage E9 cannot be supplied to the transistor Q7. Therefore, the pulse voltage Ep is not included in the brightness signal s2.

Furthermore, if Ec does not converge to Eb at the start of the scanning period, the charging and discharging of capacitor c1 will be abruptly stopped, but since the terminal voltage of capacitor Cs is fed back as is, at the start of the scanning period Ec Even if it does not converge to =Eb, there is no step in the base potential of the transistor Q7, and therefore, there is no step in the DC level in the signal S2.

[Brief explanation of drawings]

FIG. 1 is a connection diagram of an example of the present invention, and FIGS. 2 and 3 are diagrams for explaining the same. +l), (21 is a differential amplifier, (3) is a current mirror circuit.

Claims (1)

[Claims] A first amplifier to which an input signal is supplied, samples the input signal for a predetermined period, and outputs the sample; and a hold amplifier to which the output of the first amplifier for the predetermined period is supplied. In a sample-and-hold circuit that includes a capacitor and a second amplifier that extracts the terminal voltage of the capacitor, the first and second amplifiers are integrated into one IC, and the capacitor is externally attached to the IC, In the IC, a first protection resistor is connected between the capacitor and the first amplifier, and the midpoint of the connection between the capacitor and the first protection resistor is connected to the second protection resistor. a sample and hold circuit connected to said second amplifier through.