JPS6346498B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for automatically detecting a playback time mode in a video tape recorder (hereinafter referred to as VTR) or the like in which the recording and playback time can be switched.

In recent years, with advances in high-density recording, long-duration VTRs have been developed in which the running speed of the magnetic tape is slowed and the track pitch is narrowed. This is not only for long-time recording and playback, but also for example, standard time (hereinafter referred to as S.P.), super long time (hereinafter referred to as
A single VTR is configured with time modes with different recording and playback times, such as S, L, and P. Therefore, the user can freely select the desired recording time using the changeover switch. When playing back a magnetic tape recorded on such a VTR whose recording time can be switched, unless the tape is played back in the same time mode as when it was recorded, the playback image will be distorted because the tape format is different. Switching the playback time mode manually while looking at the playback image would be very difficult for the user to handle, so it is possible to automatically detect the recording time mode in some way and change the tape feed speed etc. There must be. Furthermore, unless the detection time is as short as possible, the reproduced image will be distorted during the period during which detection is not performed. In particular, when playing back a magnetic tape with many scratches, malfunctions may occur if the control signal cannot be played back due to scratches or dust on the tape (control signal dropout). Therefore, if a control loss occurs, the playback screen becomes distorted and the screen becomes disconnected, which is a drawback.

The present invention reliably prevents malfunctions even if the control signal is dropped as described above, and the detection time is very short. Furthermore, the present invention enables slow playback and still playback in which the tape is played back at a running speed different from the tape running speed at the time of recording. The present invention provides a device that can reliably detect a playback time mode without malfunctioning even in playback, special mode playback such as fast playback, or arbitrary speed playback such as variable speed playback.

The present invention will be explained below based on the illustrated embodiments. FIG. 1 is a diagram showing the main part of a VTR in playback mode using an example of the present invention. In the figure, reference numeral 1 denotes a magnetic tape, which is run in the direction of arrow W by a capstan 2 and a pinch roller 3. A video signal recorded obliquely with respect to the longitudinal direction of the magnetic tape 1 is reproduced from the magnetic tape 1 by a rotating magnetic head (not shown) built in a well-known rotating cylinder.

The capstan 2 is rotationally driven by a capstan motor 4 via a belt 5 at a predetermined speed.
Reference numeral 6 denotes a frequency generator that detects the rotational speed of the capstan motor 4, and the number of output pulses and the running speed of the magnetic tape 1 are in a proportional relationship. The output signal of the frequency generator 6 is amplified by an amplifier 7 and inputted to a clock input terminal CK of a counter 8 as a clock signal. 9 is a control head;
A control signal recorded at one frame interval during recording on a magnetic tape 1 is reproduced. The control signal reproduced by the control head 9 is amplified by the amplifier 10, and the NAND gate circuit 11,
Each of the 12 signals is input to one input terminal.

On the other hand, the output signal of the amplifier 10 is
3 and is inverted to form a D-type flip-flop (hereinafter referred to as D
-FF) is input to the D terminal of the circuit 14.
The Q output from the Q output terminal of the D-FF circuit 14 is
It is input to the D terminal of the next stage D-FF circuit 15, and the D
The output of the -FF circuit 14 is input to one input terminal of the NOR gate circuit 16, and the Q output of the D-FF circuit 15 is input to the other input terminal.

The Q ₄ and Q ₆ outputs of the counter 8 are input to the other input terminals of the NAND gate circuits 11 and 12, respectively. NAND gate circuits 17, 18 and
Two pairs of NAND gate circuits 19 and 20 each form an R-S flip-flop (hereinafter referred to as R-S flip-flop).
(referred to as FF) circuits 41 and 42 are configured,
The output of the NAND gate circuit 11 is connected to the set input terminal of the R-S/FF circuit 41 and the R-S/FF circuit 42.
is applied to the reset input terminal of the NAND
The output of the gate circuit 12 is applied to a reset input terminal of an R-S/FF circuit 41 and a set input terminal of an R-S/FF circuit 42. R-
The outputs of the S/FF circuits 41 and 42 are High or Low depending on the respective set and reset signals. Furthermore, since the set signal of one R-S/FF circuit serves as the reset signal of the remaining R-S/FF circuits, the R-S/FF circuits 41,
If only one output of 42 becomes High,
The output of the other R-S/FF circuit becomes Low.
The output terminals of the R-S/FF circuits 41 and 42 are 21,
22, if the output terminal 21 is High, S・L・P
mode, and if the output terminal 22 is High, the S/P mode is detected, and the respective light-emitting display elements 23 and 24 are turned on for display. Note that light emitting diodes may be used as the light emitting display elements 23 and 24.

On the other hand, the Q ₅ and Q ₇ outputs of the counter 8 are input to the D terminals of the D-FF circuits 25 and 26, respectively.
The Q output of the FF circuit 25 is input to the D terminal of the next stage D-FF circuit 27, and the output of the D-FF circuit 25 is
The signal is input to one input terminal of the NOR gate circuit 29, and the Q output of the D-FF circuit 27 is input to the other input terminal. The Q output of the D-FF circuit 26 is input to the D terminal of the D-FF circuit 28 in the next stage, and the D-FF
The output of the circuit 26 is input to one input terminal of the NOR gate circuit 30, and the output of the NOR gate circuit 30 is input to the other input terminal.
The Q output of the FF circuit 28 is input. A clock signal is applied from a clock signal generator 31 to the T terminals of the D-FF circuits 25, 26, 27, 28 and the aforementioned D-FF circuits 14, 15. The clock signal generator 31 may be composed of, for example, an oscillation circuit, or may be generated by frequency-dividing a 3.58 MHz oscillation signal used in a VTR. Further, the frequency may be around 100KHz, for example.

The output of the NOR gate circuit 29 is input to one input terminal of the NAND gate circuit 32, and the output of the RS/FF circuit 41 is input to the other input terminal. The output of the NOR gate circuit 30 is
The signal is input to one input terminal of the NAND gate circuit 33, and the output of the R-S/FF circuit 42 is input to the other input terminal. The outputs of the NAND gate circuits 32 and 33 are respectively input to the input terminals of the NAND gate circuit 34, and the output thereof is
It is input to one input terminal of the NAND gate circuit 36.

On the other hand, the output of the NOR gate circuit 16 is
The signal is input to one input terminal of the NAND gate circuit 35 and is also input to one input terminal of the NAND gate circuit 37. The NAND gate circuits 35 and 36 constitute an RS/FF circuit 43, the output of the NAND gate circuit 34 being a set signal, and the output of the NOR gate circuit 16 being a reset signal. The output of this R-S/FF circuit 43 is input to the other input terminal of the NAND gate circuit 37, and its output is supplied to the reset terminal R of the counter 8.

Next, the operation of this embodiment will be explained.

FIG. 2 shows a signal waveform diagram of important parts during S/P mode reproduction. All levels are High,
This is a low digital signal. A in FIG. 2 shows a control signal reproduced by the control head 9 at one frame intervals. B is a NAND gate circuit 37 that serves as a reset signal for the counter 8.
The D-FF circuits 14 and 1 are outputted so that the output is a thin pulse indicating the rear end of the control signal of A.
5 and a NOR gate circuit 16 for waveform processing. C is a signal obtained by amplifying the output of the frequency generator 6 for detecting the rotational speed of the capstan motor 4 by an amplifier 7, and this signal becomes the clock signal input to the counter 8. Moreover, the waveforms D to K in FIG. 2 are output waveforms corresponding to Q ₀ to Q ₇ of the counter 8,
The output waveform C of the frequency generator 6 is being counted. The number of pulses of the output waveform C of the frequency generator 6 in the interval of the control signal A is always constant because the magnetic tape 1 is run by the rotation of the capstan motor 4, and for example, in special modes such as slow motion playback. In the case of playback, the tape running slows down, so the interval between the control signals A becomes longer, but the frequency of the frequency generator 6 also becomes lower, and the output waveform C of the frequency generator 6 at the interval of the control signal A becomes shorter. The number of pulses is always constant. In the S/P mode of this embodiment, the output waveform C of the frequency generator 6 at the interval of the control signal A is configured to be 72 pulses. Therefore, the output waveform D of the outputs Q ₀ to _{Q 7} of the counter 9
The relationship between ~K and control signal A within one frame is always constant as shown in FIG. 2, and since the counter 8 is reset by the signal B obtained by shaping the control signal A, the output _Q Waveforms D to K of ₇ are repetitions of the waveforms shown in FIG. 2 for each control signal. Outputs of counter 8 Q ₄ and Q ₆
are input to the NAND gate circuits 11 and 12, respectively, and a control signal A is commonly input as the other input. Note that the period when only the output of Q ₄ is High is 16 pulses to 31 pulses and 48 pulses to 63 pulses, and the period when only the output of Q ₆ is High is 64 pulses to 79 pulses and 96 pulses to 111 pulses.
It's a pulse. In the S/P mode of this embodiment, the frequency generator 6
Since the output signal of Q6 is 72 pulses, at this time, the output of the NAND gate circuit 12 to which the output of _Q6 , which is High in the counter 8, is input is L as shown in FIG.
The waveform shown is obtained. At this time, the output of Q ₄ is
Since it is Low, the output of the NAND gate circuit 11 remains High.

In addition, when the L/P mode is entered, the output signal of the frequency generator 6 is configured to be 24 pulses at the control signal interval, which is 1/3 of the S/P mode, so the NAND gate circuit 11 receives the L signal. A waveform is obtained.

In the S/P mode of this embodiment, the signal shown in FIG. 2 L obtained at the output of the NAND gate circuit 12 becomes a set signal for the R-S/FF circuit 42,
Since it serves as a reset signal for the R-S/FF circuit 41, the output terminal 22 of the R-S/FF circuit 42 is
At High, the output terminal 21 of the R-S/FF circuit 41 is
The signal becomes Low, and the light emitting display element 24 for S/P mode detection lights up. Since the output terminal 21 of the light emitting display element 23 for S/L/P mode detection is Low, it does not light up. From this, detection of the S/P recording time mode is performed.

Next, as an example, a case will be described with reference to FIG. 3 in which the control signal is not reproduced just once due to scratches, dust, etc. on the magnetic tape 1. In FIG. 3, a is the control head 9.
The figure shows the control signal reproduced in , and there is one control signal dropout on the way (the part indicated by the broken line). FIG. 3b shows a waveform obtained by converting the digital outputs of Q ₀ to Q ₇ of the counter 8 into analog signals, and this D/A conversion can be realized using a ladder resistor or the like. FIG. 3c shows the output of the NAND gate circuit 37 which becomes the reset signal for the counter 8, and like the control signal a, the reset signal is missing once. Therefore, due to this lack of control, the counter 8 is not reset at the 72nd count in the S/P mode, and continues counting until the next control signal is reproduced. In Figure 3b, due to one loss of control, the count reaches 72 counts x 2 = 144 counts. At this time, the output of _Q6 of the counter 8 is Low, the output of _Q4 is High, and the set/reset signal L is output to the output terminal of the NAND gate circuit 11 as described above, so that the S/P mode is established. Nevertheless, a problem arises in that the S/L/P mode is detected and malfunction occurs. Furthermore, there are cases where recording time mode detection is missed due to two or three consecutive failures in control, or depending on the recording time mode and counter capacity at that time. Therefore, in the present invention, if a loss of control occurs even once, the counter 8 continues counting and the next high-order bit always changes from Low to High.
(In the S/P mode of this embodiment, the output of _Q7 becomes High from the 128th count), so the D-FF circuits 26 and 28 and the NOR gate circuit 30 detect this rise.

In addition, in S・L・P mode, _Q5
Rising from Low to High (from the 32nd count)
becomes High) to the D-FF circuits 25, 27 and
It is detected by the NOR gate circuit 29. The detected rising pulse of the upper bit is sent to the NAND gate circuit 32, so that only the necessary information can be extracted depending on the recording time mode detected at that time.
33. In the S/P mode of this embodiment, one input of the NAND gate circuit 33 is connected to the output terminal 22 and is High.
The output of the NOR gate circuit 30 is inverted and output, and further inverted by the NAND gate circuit 34.
The output of this NAND gate circuit 34 is called a control loss detection signal, and its waveform is shown in FIG. 3d. R-S/FF with NAND gate circuits 35 and 36
A circuit 43 is configured to generate a signal that is set by the control loss detection signal d and reset by the first control signal after the control loss, and this is waveform-processed into a thin pulse indicating the rear end of the control signal. This signal is used as a reset signal for the counter 8. This waveform is shown in FIG. 3e. Q ₀ ~ of counter 8 in this process
If the digital output of Q ₇ is converted to analog, the third
The waveform is shown in Figure f. As a result, during steady running, the count of the counter 8 when the control signal is regenerated is 72 pulses, but the count of the counter 8 is always 0 when the first control signal is regenerated after a loss of control occurs. At this time, NAND
An R-S/FF circuit 41 is connected to the output of the gate circuit 12,
The waveform shown in FIG. 3g, which is a set/reset signal of 42, is obtained. In this waveform, the set signal and reset signal are missed several times due to control loss, but at this time, the output terminals 21 and 22 of the R-S/FF circuits 41 and 42 maintain their previous states, so no malfunction occurs. There is no problem.

In other words, in the present invention, since the running speed of the magnetic tape 1 per unit time is different in S/P mode and S/L/P mode, 1 control interval (1 frame = 33.3
Counts how many pulses the output signal of the frequency generator 6 has in one control interval, which detects the number of revolutions of the capstan motor 4, which is proportional to how far the magnetic tape travels in mS), that is, the traveling distance of the magnetic tape. This will automatically switch the playback time mode. Furthermore, when a control loss occurs, the number of pulses of the frequency generator 6 in the control pulse interval is not determined, so by configuring the counter 8 to be reset during the period when the first control signal is regenerated from the control loss detection pulse. , to prevent malfunctions. Furthermore, during steady running, the recording time mode is detected for each control signal, so the detection speed is fast and accurate.

Furthermore, even in special mode playback such as slow motion playback, fast motion playback, and variable speed playback, the number of pulses of the frequency generator 6 in one control interval is always constant, so it can be detected in the same way. Furthermore, by using a magnetic flux response type head for the control head 9, even when performing still playback, for example, the control signal can be played back until the magnetic tape 1 is about to stop, so detection of the recording time mode is the same. Can be done.

As is clear from the above description, according to the present invention, the recording time mode can be detected accurately with a very simple circuit configuration and with a fast detection speed. Also,
It has the excellent feature that it does not malfunction even if the control is lost due to damage to the magnetic tape or adhesion of dust, and the recording time mode can be detected in the same way during special mode playback regardless of the playback speed during playback. have

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a video tape recorder embodying an example of the present invention, and FIGS. 2 and 3 are signal waveform diagrams of the main parts in the same embodiment. 1...magnetic tape, 2...capstan, 3...
...Pinch roller, 4...Capstan motor, 6
... Frequency generator, 8 ... Counter, 9 ... Control head, 23, 24 ... Light emitting display element,
41, 42, 43...R-S/FF circuit.

Claims (1)

[Scope of Claims] 1. A magnetic tape running means including a capstan and a pinch roller, a control head for reproducing control signals recorded on the magnetic tape at one-frame intervals, and a frequency power generator for detecting the rotational speed of the capstan. A time mode detection device in a helical scan video tape recorder capable of switching recording/playback time, comprising: a frequency generator which is generated within an interval of a control signal played by the control head during playback; a counting means for counting the number of output pulses of the control signal; a detection means for detecting the omission of the control signal; A time mode detection device characterized by comprising a counting prohibition means for prohibiting counting of the number of output pulses of a generator. 2. The time mode detection device according to claim 1, characterized in that a magnetic flux responsive head is used as the control head. 3. The time mode detection device according to claim 1, characterized in that the counting means uses a counter that uses the number of output pulses of the frequency generator as a clock signal and uses the control signal as a reset signal. . 4. In claim 3, the detection means for detecting the omission of the control signal comprises:
A time mode detection device characterized in that it is configured to detect a rising edge of an upper bit due to the counter not being reset due to the control signal omission, and output a control omission signal.