JPS6335139U - - Google Patents

Info

Publication number
JPS6335139U
JPS6335139U JP11313087U JP11313087U JPS6335139U JP S6335139 U JPS6335139 U JP S6335139U JP 11313087 U JP11313087 U JP 11313087U JP 11313087 U JP11313087 U JP 11313087U JP S6335139 U JPS6335139 U JP S6335139U
Authority
JP
Japan
Prior art keywords
processing mode
timer
system processing
built
logic unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11313087U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11313087U priority Critical patent/JPS6335139U/ja
Publication of JPS6335139U publication Critical patent/JPS6335139U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案による非決定的処理処理装置の一実
施例構成を示す。 図中、1はタイマ、2は算術論理ユニツト(A
LU)を夫々表す。
The figure shows the configuration of an embodiment of a non-deterministic processing device according to the present invention. In the figure, 1 is a timer, 2 is an arithmetic logic unit (A
LU) respectively.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] タイマが内蔵されてなりかつ複数の選択対象処
理のうち任意の処理を非決定的に選択するシステ
ム処理モードを有するデータ処理装置において、
上記システム処理モード時に上記内蔵されている
タイマの指示内容を被除数情報とし、かつシステ
ムの処理モードに対応して与えられる値を除数と
して除算処理を行う算術論理ユニツトをそなえ、
該算術論理ユニツトによる剰余出力情報により、
該剰余出力情報と予め対応づけられた上記選択対
象処理の1つを選択するようにしたことを特徴と
する非決定的処理処理装置。
In a data processing device that includes a built-in timer and has a system processing mode that non-deterministically selects an arbitrary process among a plurality of selection target processes,
an arithmetic logic unit that uses the instruction content of the built-in timer as dividend information in the system processing mode and performs division processing using a value given in accordance with the system processing mode as a divisor;
Based on the remainder output information by the arithmetic logic unit,
A non-deterministic processing device, characterized in that one of the selection target processes previously associated with the residual output information is selected.
JP11313087U 1987-07-23 1987-07-23 Pending JPS6335139U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11313087U JPS6335139U (en) 1987-07-23 1987-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11313087U JPS6335139U (en) 1987-07-23 1987-07-23

Publications (1)

Publication Number Publication Date
JPS6335139U true JPS6335139U (en) 1988-03-07

Family

ID=30994634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11313087U Pending JPS6335139U (en) 1987-07-23 1987-07-23

Country Status (1)

Country Link
JP (1) JPS6335139U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11948567B2 (en) 2018-12-28 2024-04-02 Samsung Electronics Co., Ltd. Electronic device and control method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11948567B2 (en) 2018-12-28 2024-04-02 Samsung Electronics Co., Ltd. Electronic device and control method therefor

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