JPS633414A - Manufacture of silicon film - Google Patents
Manufacture of silicon filmInfo
- Publication number
- JPS633414A JPS633414A JP14738086A JP14738086A JPS633414A JP S633414 A JPS633414 A JP S633414A JP 14738086 A JP14738086 A JP 14738086A JP 14738086 A JP14738086 A JP 14738086A JP S633414 A JPS633414 A JP S633414A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chamber
- silicon film
- trisilane
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 14
- 229910052710 silicon Inorganic materials 0.000 title claims description 14
- 239000010703 silicon Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 44
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000002230 thermal chemical vapour deposition Methods 0.000 claims abstract description 12
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 229910000077 silane Inorganic materials 0.000 claims abstract description 7
- 239000002994 raw material Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 abstract description 18
- 230000008021 deposition Effects 0.000 abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 12
- 150000004756 silanes Chemical class 0.000 abstract description 3
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 25
- 239000007789 gas Substances 0.000 description 14
- 238000010586 diagram Methods 0.000 description 10
- 239000010409 thin film Substances 0.000 description 10
- 229910052739 hydrogen Inorganic materials 0.000 description 8
- 239000001257 hydrogen Substances 0.000 description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000001816 cooling Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 101000979735 Homo sapiens NADH dehydrogenase [ubiquinone] 1 beta subcomplex subunit 8, mitochondrial Proteins 0.000 description 1
- 102100024975 NADH dehydrogenase [ubiquinone] 1 beta subcomplex subunit 8, mitochondrial Human genes 0.000 description 1
- 241000220317 Rosa Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 238000003763 carbonization Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000010574 gas phase reaction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、経時変化の少ない薄膜トランジスタ等に用
いるシリコン膜の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a silicon film used for thin film transistors and the like that undergoes little change over time.
（発明の概要〕
この発明は、トリシラン以上の高次シランを用いた熱Ｃ
ＶＤにより、高品質で安定なアモルファスシリコン膜を
製造するものである。(Summary of the Invention) This invention provides thermal carbonization using a higher order silane than trisilane.
A high quality and stable amorphous silicon film is manufactured by VD.
プラズマ等のＲ’Ｃ粒子によるダメージのないシリコン
膜の製造方法に熱ＣＶＤがある。Thermal CVD is a method for manufacturing silicon films that is not damaged by R'C particles such as plasma.
従来、水素化アモルファスシリコン膜を熱ＣＶＤ法で成
膜する場合、原料ガスにモノシラン（ＳｉＵＳ）を用い
ると基板温度を６００〜６５０℃の高温にする必要があ
り、膜中の構造欠陥を補償する結合水素量が極めて少な
く膜の特性が良くなかった。Conventionally, when forming a hydrogenated amorphous silicon film using the thermal CVD method, if monosilane (SiUS) is used as the raw material gas, it is necessary to raise the substrate temperature to a high temperature of 600 to 650 °C, which is necessary to compensate for structural defects in the film. The amount of bonded hydrogen was extremely small and the properties of the film were poor.
ジシラン（ＳｉＪｉ）を用いた場合、基板温度４００〜
５００℃で適当に水素を含むアモルファスシリコン膜が
形成できるとの報告が、Ｙｏｓｈｉｎｏｒｉ ＡＳＨＩ
［ｌＡら（Ｙｏｓｈｉｎｏｒｉ ＡＳＨＩＤＡ、Ｙａｓ
ｕｙｏｓｈｉ ＭＩＳ）ＩＩｆ’ｌＡ、Ｍａｓａｔａｋ
ａ旧ＲＯＳＥ、Ｙｕｋｉｏ ０５ＡＫＡ ａｎｄ Ｋｅ
ｎｉｃｈｉ ＫＯＪＩＭＡ、 Ｊｊ。When using disilane (SiJi), the substrate temperature is 400~
Yoshinori ASHI reported that an amorphous silicon film containing appropriate hydrogen can be formed at 500°C.
[lA et al. (Yoshinori ASHIDA, Yas.
uyoshi MIS) IIf'lA, Masatak
a Old ROSE, Yukio 05AKA and Ke
nichi KOJIMA, Jj.
Ａｐｐｌ、Ｐｈｙｓ、 ２３（１９８４） １２９）に
よりなされている。Appl, Phys, 23 (1984) 129).
しかし、従来のジシランによる熱ＣＶＤ法では基板加熱
以外に、チャンバーも加熱するホットウォール型の反応
装置を用いていた。ホントウオール型ではデポジション
レートは高いもののチャンバー内壁の不純物をシリコン
膜中にとり込み易く改質の向上がむずかしい。また、気
相反応により基板表面にシリコン粒子が堆積し、表面が
荒れてしまうという問題があった。However, the conventional thermal CVD method using disilane uses a hot wall type reaction device that not only heats the substrate but also heats the chamber. Although the real wall type has a high deposition rate, impurities on the inner wall of the chamber are easily incorporated into the silicon film, making it difficult to improve the modification. Additionally, there is a problem in that silicon particles are deposited on the substrate surface due to the gas phase reaction, resulting in a rough surface.
一方、チャンバーは加熱せず基板のみを加熱すルコール
ドウォール型の反応装置ではデポジションレートが低い
という問題があった。On the other hand, a cold wall type reactor in which only the substrate is heated without heating the chamber has a problem in that the deposition rate is low.
そこで、この発明はコールドウオール型の反応装置にお
いても低い基ＦＡＡ度で十分なデポジションレートがあ
り、良好な電気特性をもつ安定なアモルファスシリコン
膜の形成を目的としている。Therefore, the present invention aims to form a stable amorphous silicon film having a sufficient deposition rate with a low group FAA degree and good electrical properties even in a cold wall type reactor.
この発明では、原料ガスにトリシラン以上の高次シラン
を用い、ｐｃｖｏにおける成膜条件とシリコン膜の特性
の関係を明らかにすることにより問題を解決した。In this invention, the problem was solved by using a higher-order silane higher than trisilane as the raw material gas and clarifying the relationship between the film forming conditions in PCVO and the characteristics of the silicon film.
ジシランに比ベトリシラン以上の高次シランは反応性が
高いので、十分なデポジションレートがあり、膜質に関
係する基板温度、反応圧力等の成膜条件を最適化するこ
とができる。Higher-order silanes, which are more reactive than disilane than betrisilane, have a sufficient deposition rate and can optimize film-forming conditions such as substrate temperature and reaction pressure, which are related to film quality.
まず、この発明に用いる装置例を第１図（ａｌおよびＣ
ｂ）により説明する。First, an example of the apparatus used in this invention is shown in FIG. 1 (al and C
This is explained by b).
第１図（ａ）において、１はチャンバーで、内部にヒー
ター等の基板加熱手段２を有し、熱伝専の良いサセプタ
ー３が固定され、加熱される。サセプター３上には石英
板、ガラス板、ステンレス板。In FIG. 1(a), a chamber 1 has a substrate heating means 2 such as a heater inside, and a susceptor 3 with good heat transfer is fixed thereon and heated. On the susceptor 3 are a quartz plate, a glass plate, and a stainless steel plate.
シリコンウェハー等の基板４が載せられている（下向き
等の場合には止め金具等で固定される）。A substrate 4 such as a silicon wafer is placed thereon (if it is facing downward, it is fixed with a stopper or the like).
さらに、基板４の近傍にガス吹出部５を形成し、ガス供
給手段６とチャンバー１内を排気手段５がチャンバー１
に接続されている。ガス供給手段６からガス吹出部まで
の系はヒーター等により原料ガスの沸点（トリシランで
は５３，１℃）以上の温度に保たれている。このほか、
必要に応じて、チャンバー１の側面に真空ゲージ、観察
窓等が設けられ、冷却のための空冷ないしは水冷パイプ
が接続されている。Further, a gas blowing part 5 is formed near the substrate 4, and an exhaust means 5 is connected to the gas supply means 6 and the inside of the chamber 1.
It is connected to the. The system from the gas supply means 6 to the gas blowing section is maintained at a temperature higher than the boiling point of the raw material gas (53.1° C. for trisilane) by a heater or the like. other than this,
If necessary, a vacuum gauge, an observation window, etc. are provided on the side surface of the chamber 1, and an air cooling or water cooling pipe for cooling is connected thereto.
第１図ｆｂｌは、基板加熱手段２にランプ加熱を用いた
場合で、チャンバー１は光吸収の少ない石英。FIG. 1fbl shows a case where lamp heating is used as the substrate heating means 2, and the chamber 1 is made of quartz that absorbs little light.
サセプター３は光吸収の良いカーボン等の材質のものを
各々用いる。The susceptor 3 is made of a material such as carbon that has good light absorption.
このような装置において基板温度を４００ ℃程度に加
熱し、トリシラン以上の高次シランをチャンバー１内に
導入すると、熱分解反応により、基板４表面にアモルフ
ァスシリコン膜を形成することができる。この場合、チ
ャンバー１の壁面の温度は２００℃前後であるが、さら
に冷却する場合は、空気、Ｎ２ガス等をチャンバー１外
から吹きつければよい。以下にデポジションの詳細な条
件を示す。In such an apparatus, when the substrate temperature is heated to about 400° C. and a higher-order silane of trisilane or higher is introduced into the chamber 1, an amorphous silicon film can be formed on the surface of the substrate 4 through a thermal decomposition reaction. In this case, the temperature of the wall surface of the chamber 1 is around 200° C., but if further cooling is desired, air, N2 gas, etc. may be blown from outside the chamber 1. Detailed conditions for deposition are shown below.
第２図は１００％トリシランを用いた石英基板上へのア
モルファスシリコン膜のデポジションレートのデータの
一例を示すものである。第３図で横軸は基板温度Ｔｓｕ
ｂの逆数（１／Ｋ） 、縦軸はデポジションレート （
人／ ｍ１ｎ）であり、△１０．○、◇。FIG. 2 shows an example of data on the deposition rate of an amorphous silicon film on a quartz substrate using 100% trisilane. In Figure 3, the horizontal axis is the substrate temperature Tsu
The reciprocal of b (1/K), the vertical axis is the deposition rate (
person/m1n) and △10. ○、◇.
印はそれぞれ反応圧力が１． ２． ５．１０．１２Ｔ
ｏｒｒの場合である。１０ Ｔｏｒｒ、 ４２０℃で６
０人／ｍｉｎのデポジションレートがあり、半導体素子
を生産するのに十分な値である。Each mark indicates a reaction pressure of 1. 2. 5.10.12T
This is the case of orr. 6 at 10 Torr, 420℃
There is a deposition rate of 0 person/min, which is sufficient for producing semiconductor devices.
）ＩＺ＋ Ｎｚ、 Ｈｅ、 Ａｒ等の雰囲気ガスでｎ訳
した場合のデポジションは、トリシランの分圧が第３図
の反応圧力と同じなら、デポジションレートもほぼ等し
くなる。)IZ+ If the partial pressure of trisilane is the same as the reaction pressure in FIG. 3, the deposition rate will be approximately the same when translated into n using an atmospheric gas such as Nz, He, or Ar.
第３図は１００％トリシランを用いて反応圧力５Ｔｏｒ
ｒの場合の光学バンドギャップと結合水素工の基板温度
依存性の一例を示したものである。、ｌ＋Ｎ温度が４８
０℃以下では光学バンドギャップは約１゜６５ｅＶ 、
結合水素量は約７，５％でほぼ一定である。Figure 3 shows a reaction pressure of 5 Torr using 100% trisilane.
This figure shows an example of the substrate temperature dependence of the optical bandgap and bonded hydrogen in the case of r. , l+N temperature is 48
At temperatures below 0°C, the optical bandgap is approximately 1°65 eV,
The amount of bound hydrogen is approximately constant at about 7.5%.
基板温度が４８０℃を越える温度では光学バンドギャッ
プ、結合水素量ともに減少する。これよりトリシラン以
上の高次シランの熱ＣＶ Ｄでは基板温度４８０℃を越
える温度で水素脱離が起こることが解った。When the substrate temperature exceeds 480° C., both the optical band gap and the amount of bonded hydrogen decrease. From this, it was found that in thermal CVD of higher order silanes than trisilane, hydrogen desorption occurs at substrate temperatures exceeding 480°C.
第４図は、１００％トリシランを用いて反応圧力５ Ｔ
ｏｒｒの場合の暗導電率（Ｏ印）とＡＭＩスペクトラム
６０ｎ Ｗ／ｃａｌの光照射での光導電率（Ｏ印）の基
板温度依存性を示したものである。光導電率は高（ない
が、光ぷ電率と暗導電率の比は３桁以上ある。また、基
板温度４８０℃を越える温度では、水素脱離により光導
電率、暗導電率ともに低下する。Figure 4 shows a reaction pressure of 5 T using 100% trisilane.
The graph shows the substrate temperature dependence of the dark conductivity (marked with O) in the case of orr and the photoconductivity (marked with O) when irradiated with light of 60 nW/cal in the AMI spectrum. The photoconductivity is high (although not, the ratio of photoconductivity to dark conductivity is more than 3 digits).In addition, at substrate temperatures exceeding 480°C, both photoconductivity and dark conductivity decrease due to hydrogen desorption. .
第５図は、赤外吸収特性の一例を示したものである。−
般に２０００ｃｍ−’付近にピークを持つＳｉＨ結合の
伸縮振動と２１００ｃ＋＋＋−’付近にピークを持つＳ
ｉＪ結合の伸１１振動が観察されるが、トリシランの熱
ＣＶＤによるアモルファスシリコン膜では５ｉｌｔ結合
のピークはほとんど観測されず、５ｉｌｌ結合が主であ
り良質な膜であるといえる。FIG. 5 shows an example of infrared absorption characteristics. −
In general, the stretching vibration of SiH bonds has a peak around 2000 cm-' and the S vibration has a peak around 2100 c+++-'.
Although elongation 11 vibrations of iJ bonds are observed, in the amorphous silicon film produced by thermal CVD of trisilane, almost no peak of 5ilt bonds is observed, and it can be said that the film is of good quality, with 5ill bonds being the main component.
以上のデポジションのデータを利用して作成した薄膜ト
ランジスタの断面図の一例を第６図に示す。低抵抗ｐ型
シリコン基板を利用したゲート６と、前記シリコン基板
を１１００℃、 ｄｒｙＯ□雰囲気中で熱酸化した約９
００ 人のゲート絶縁膜７の上に、トリシラン以上の高
次シランの熱ｃｖｏによるノンドープアモルファスンリ
コン膜８を約５００人デポジションする。さらにｎ°ア
モルファスシリコン層とＮｉ等の金属層の二層よりなる
ソース９及びトレイン１０を形成する。FIG. 6 shows an example of a cross-sectional view of a thin film transistor created using the above deposition data. A gate 6 using a low-resistance p-type silicon substrate and a gate 6 made by thermally oxidizing the silicon substrate at 1100° C. in a dryO□ atmosphere.
On the gate insulating film 7 of about 500 people, a non-doped amorphous silicon film 8 is deposited by thermal CVO of higher-order silane of trisilane or higher by about 500 people. Furthermore, a source 9 and a train 10 made of two layers, an n° amorphous silicon layer and a metal layer such as Ni, are formed.
第７図は実際の薄膜トランジスタの出力特性の一例であ
る。ゲート・ソース電圧は２０〜３０Ｖまで２■ステツ
プで変化させ、チャネル幅−とチャネル長しの比は−／
Ｌ ＝ ４０である。ソース・ドレイン電圧を０−１Ｏ
−ＯＶと掃引した場合のヒステリシスは非常に小さく安
定である。この薄膜トランジスタの０Ｎ１０ＦＦ電流比
は６桁以上あり、飽和領域から求めたしきい値電圧と電
子移動度は各々１８■。FIG. 7 shows an example of the output characteristics of an actual thin film transistor. The gate-source voltage was varied from 20 to 30 V in 2-inch steps, and the ratio of channel width to channel length was -/
L=40. Source-drain voltage 0-1O
The hysteresis when swept to -OV is very small and stable. The 0N10FF current ratio of this thin film transistor is more than 6 digits, and the threshold voltage and electron mobility determined from the saturation region are each 18 cm.
０、ＩＣｌ１ｌ／Ｖ−５と良好なものであった。0, ICl1l/V-5, which was good.
ドレイン電流１ｄの時間変化を、モノシランのプラズマ
ＣＶＤで作製した薄膜トランジスタと比較して第８図に
示す、プラズマＣＶＤ試料は熱Ｃ■Ｄと同じチャンバー
を用い、基板温度３００℃１反応圧力０．７Ｔｏｒｒ、
高周波電力ＬＯＷで製膜したちのである。第９図の横軸
は、ドレイン電流を１μＡ流すのに必要なバイアスを印
加してからの時間。Figure 8 shows a comparison of the time change of the drain current 1d with a thin film transistor fabricated by monosilane plasma CVD.The plasma CVD sample used the same chamber as the thermal CD, and the substrate temperature was 300°C and the reaction pressure was 0.7 Torr. ,
The film was formed using low-frequency high-frequency power. The horizontal axis in FIG. 9 represents the time after applying the bias necessary to cause a drain current of 1 μA to flow.
縦軸はドレイン電流の初期値１ｄ（０）に対する各時間
における値１ｄの比である。実線が熱ＣＶＤ、破線がプ
ラズマＣＶＤによる薄膜トランジスタの場合である。熱
ＣＶＤによる薄膜トランジスタの方が、プラズマＣＶＤ
によるものよりドレイン電流の時間変化が小さく安定で
ある。The vertical axis is the ratio of the drain current value 1d at each time to the initial value 1d(0). The solid line is for a thin film transistor formed by thermal CVD, and the broken line is for a thin film transistor formed by plasma CVD. Thin film transistors made by thermal CVD are better than those made by plasma CVD.
The time change in drain current is smaller and more stable than that of the conventional method.
第９図（ａｌ及びｔｂｌはそれぞれ実際のデポジション
の手順の一例を示したもので、横軸は時間、縦軸はチャ
ンバー圧と基板温度を示している。第９図（ａｌは１０
０％トリシランの場合で、真空引きしたチャンバー１に
トリシランを導入するとデポジションが始まる。この時
、チャンバー圧が急に増加すると基板加熱手段２とサセ
プター３．及びサセプター３と基板４間の熱伝導が良（
なり、基板温度が２０℃程度も上昇する。しばらくする
と温度制御が追従し、基板温度が安定する。チャンバー
圧が１０Ｔｏｒｒ以上でこの現象は顕著である。このデ
ポジション開始時の基板温度変化は、デポジション時間
が短い場合、膜厚の制御や膜質の均一性を悪くする。FIG. 9 (al and tbl each show an example of an actual deposition procedure, the horizontal axis shows time, and the vertical axis shows chamber pressure and substrate temperature.
In the case of 0% trisilane, deposition begins when trisilane is introduced into the evacuated chamber 1. At this time, if the chamber pressure suddenly increases, the substrate heating means 2 and the susceptor 3. and good heat conduction between the susceptor 3 and the substrate 4 (
As a result, the substrate temperature rises by about 20°C. After a while, the temperature control will follow suit and the substrate temperature will stabilize. This phenomenon is remarkable when the chamber pressure is 10 Torr or more. This change in substrate temperature at the start of deposition deteriorates control of film thickness and uniformity of film quality when the deposition time is short.
そこで、第９図（ｂｌに示すように、あらかじめＨ２゜
Ｎｚ、 Ｈｅ、Ａｒ等の希釈ガスを１０Ｔｏｒｒ以上チ
ャンバー１内に導入しておき、基板温度が安定してから
トリシランを与太すると、基板温度の変化は１℃以下に
おさえることができ、安定なデポジションを行うことが
できる。この安定化効果は５ Ｔｏｒｒ前後のチャンバ
ー圧でも認められた。Therefore, as shown in Fig. 9 (bl), a diluent gas such as H2°Nz, He, Ar, etc. is introduced into the chamber 1 at a pressure of 10 Torr or more, and after the substrate temperature has stabilized, trisilane is applied thickly. The temperature change can be suppressed to 1° C. or less, and stable deposition can be performed. This stabilizing effect was observed even at a chamber pressure of around 5 Torr.
以上詳細に説明したように、どの発明はトリシラン以上
の高次シランを用いて基板温度４８０℃以下で熱ＣＶＤ
を行った場合、電気特性の良い安定なアモルファスシリ
コン膜が得られる利点がある。As explained in detail above, which invention involves thermal CVD at a substrate temperature of 480°C or less using a higher-order silane higher than trisilane.
When carried out, there is an advantage that a stable amorphous silicon film with good electrical properties can be obtained.
また、雰囲気ガスをあらかしめチャンバー内に導入し、
基板温度が安定した後に原料ガスを導入して熱ＣＶＤを
行うと、成膜時の基板温度変化を非常に小さくすること
ができる。In addition, atmospheric gas is introduced into the chamber,
If the source gas is introduced and thermal CVD is performed after the substrate temperature has stabilized, changes in the substrate temperature during film formation can be made very small.
さらに、低温でしかも荷電粒子のダメージのないプロセ
スであることから、ＬＳＩ等のプロセスと組合せた場合
でも、既に形成済みの他の素子に悪い影響を与えること
がないことは明白である。Furthermore, since the process is performed at a low temperature and does not cause damage from charged particles, it is clear that even when combined with a process for LSI, etc., there will be no adverse effect on other devices that have already been formed.
第１図（８１はこの発明に用いるヒーター加熱による装
置の断面略図、第１図ｔｂｌは同様にランプ加熱による
装置の断面略図、第２図はこの発明の１００％トリシラ
ンを用いた熱ＣＶＤのデポジションレートの基板温度依
存性を示す図、第３図は、この発明の光学バンドギャッ
プと水素含有率の基板温度依存性を示す図、第４図はこ
の発明の導電率の基板温度依存性を示す図、第５図はこ
の発明のシリコン膜の赤外吸収特性図、第６図は第２図
から第５図までのデータを利用して作製した薄膜トラン
ジスタの断面図、第７図は第６図の薄膜トランジスタの
出力特性図、第８図は同じく、ドレイン電流の時間変化
を示す図、第９図（ａ）は１００％トリシランを用いた
場合のデポジションの手順例を示す図、第９図へ）は同
様に雰囲気ガスで希釈した場合のデポジションの手順例
を示す図である０図中、１はチャンバー、２は基板加熱
手段、３はサセプタ、４は基板、５はガス吹出部、６は
ガス供給手段、７は排気手段、８はシリコン膜、９はソ
ース、１０はドレインである。
以上
出 願 人 工業技術院長
信越化学工業株式会社
セイコー電子工業株式会社
指定代理人 工業技術院電子技術総合研究所所長佐藤
孝平
４代 理 人 弁理士 最 上 １１ｔ （他１名
）第１凶（ａ）
基板温度（０Ｃ）
１０００／Ｔｓｕｂ （１／に）
デボシ゛シ３ンし一トΦ肪暴し！壱に杓峠缶を、ホＴｆ
ｆｉ第２図
導 電 早 （Ｓ−ｃｍ−〇
に％＞−二ｔ″Ｇ−７（ｅＶ） ７關に、４ｉＬ
（％）：ＪＬ数（ｃｍ−’）
赤外吸家符性図
第５図
ＮＦ２．ｒラシシ“スタの迂γ面図
第６図
ドレイン・ソース電圧 （Ｖ）
薄４片費、トランジズタの出力特十往図第 ７ 図
バイアス卵１ａｇ７−月ノつ’（ｈｏｕｒンドしイ〕電
麦の片開変化をホＴＩＩＫ
第８図
ミ午間 （ｍｉｎン
テ゛ホ５５Ｇのす櫃１烈１ホＴ図
第９図（ａ）
Ｂ′ｒ 閣 （ｍｉｎン
テホ゛ジシｊ二の計慣例１ホＴ図
第９図（ｂ）Figure 1 (81 is a schematic cross-sectional view of a device heated by a heater used in this invention, Figure 1 tbl is a schematic cross-sectional view of a device heated by a lamp, and Figure 2 is a schematic cross-sectional view of a device heated by a lamp of this invention). FIG. 3 is a diagram showing the substrate temperature dependence of the position rate. FIG. 3 is a diagram showing the substrate temperature dependence of the optical band gap and hydrogen content of the present invention. FIG. 4 is a diagram showing the substrate temperature dependence of the conductivity of the present invention. 5 is an infrared absorption characteristic diagram of the silicon film of the present invention, FIG. 6 is a cross-sectional view of a thin film transistor manufactured using the data from FIGS. 2 to 5, and FIG. The output characteristics of the thin film transistor shown in the figure, Figure 8 is also a diagram showing the change in drain current over time, and Figure 9 (a) is a diagram showing an example of the deposition procedure when using 100% trisilane. Figure 1) is a diagram showing an example of the deposition procedure when diluted with atmospheric gas. 6 is a gas supply means, 7 is an exhaust means, 8 is a silicon film, 9 is a source, and 10 is a drain. Applicants: Shin-Etsu Chemical Co., Ltd., Director of the Agency of Industrial Science and Technology; Seiko Electronics Co., Ltd., designated agent; Kohei Sato, 4th Director, Electronics Technology Research Institute, Agency of Industrial Science and Technology; Attorney: Patent Attorney Mogami 11t (1 other person) Daiichi Kouhei (a) ) Substrate temperature (0C) 1000/Tsub (to 1/) Deboss 3 and expose the Φ fat! Ichitoge can, ho Tf
fi Diagram 2 Conductivity (S-cm-〇%＞-2t″G-7 (eV) 7, 4iL
(%): JL number (cm-') Infrared fluctuating sign diagram Figure 5 NF2. Fig. 6 Drain-source voltage (V) Thin 4-channel transistor output characteristic diagram Fig. 7 Bias Fig. 8 (min. (b)
Claims (2)
ガス供給手段とが接続された装置を用い、原料ガスとし
てトリシラン（Ｓｉ＿３Ｈ＿２）以上の高次シランを前
記チャンバー内に導入し、基板温度４８０℃以下で、か
つ前記チャンバー壁面の温度を前記基板温度より低く保
ち、熱ＣＶＤによりシリコン膜を成長させることを特徴
とするシリコン膜の製造方法。(1) Using a device in which an exhaust means and a gas supply means are connected to a chamber containing a substrate heating means, a higher order silane of trisilane (Si_3H_2) or higher is introduced into the chamber as a raw material gas, and the substrate temperature is 480°C. A method for manufacturing a silicon film as described below, characterized in that the temperature of the wall surface of the chamber is kept lower than the temperature of the substrate, and the silicon film is grown by thermal CVD.
あらかじめ前記チャンバー内に導入し、基板温度が安定
した後に、原料ガスを導入してシリコン膜を成長させる
ことを特徴とする特許請求範囲第１項記載のシリコン膜
の製造方法。(2) The scope of the claim characterized in that an atmospheric gas (H_2, N_2, He, Ar, etc.) is introduced into the chamber in advance, and after the substrate temperature is stabilized, a source gas is introduced to grow a silicon film. 2. The method for manufacturing a silicon film according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14738086A JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14738086A JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS633414A true JPS633414A (en) | 1988-01-08 |
| JPH0556852B2 JPH0556852B2 (en) | 1993-08-20 |
Family
ID=15428933
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14738086A Granted JPS633414A (en) | 1986-06-24 | 1986-06-24 | Manufacture of silicon film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS633414A (en) |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0335535A (en) * | 1989-06-30 | 1991-02-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film field effect transistor |
| US5607724A (en) * | 1991-08-09 | 1997-03-04 | Applied Materials, Inc. | Low temperature high pressure silicon deposition method |
| US5614257A (en) * | 1991-08-09 | 1997-03-25 | Applied Materials, Inc | Low temperature, high pressure silicon deposition method |
| US6716751B2 (en) | 2001-02-12 | 2004-04-06 | Asm America, Inc. | Dopant precursors and processes |
| US6815007B1 (en) | 2002-03-04 | 2004-11-09 | Taiwan Semiconductor Manufacturing Company | Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| US7092287B2 (en) | 2002-12-18 | 2006-08-15 | Asm International N.V. | Method of fabricating silicon nitride nanodots |
| US7186630B2 (en) | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| US7294582B2 (en) | 2002-07-19 | 2007-11-13 | Asm International, N.V. | Low temperature silicon compound deposition |
| US7297641B2 (en) | 2002-07-19 | 2007-11-20 | Asm America, Inc. | Method to form ultra high quality silicon-containing compound layers |
| US7427571B2 (en) | 2004-10-15 | 2008-09-23 | Asm International, N.V. | Reactor design for reduced particulate generation |
| JP2009071290A (en) * | 2007-08-17 | 2009-04-02 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| US7553516B2 (en) | 2005-12-16 | 2009-06-30 | Asm International N.V. | System and method of reducing particle contamination of semiconductor substrates |
| US7629270B2 (en) | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7674726B2 (en) | 2004-10-15 | 2010-03-09 | Asm International N.V. | Parts for deposition reactors |
| US7674728B2 (en) | 2004-09-03 | 2010-03-09 | Asm America, Inc. | Deposition from liquid sources |
| US7691757B2 (en) | 2006-06-22 | 2010-04-06 | Asm International N.V. | Deposition of complex nitride films |
| US7732350B2 (en) | 2004-09-22 | 2010-06-08 | Asm International N.V. | Chemical vapor deposition of TiN films in a batch reactor |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
| US7851307B2 (en) | 2007-08-17 | 2010-12-14 | Micron Technology, Inc. | Method of forming complex oxide nanodots for a charge trap |
| US9443730B2 (en) | 2014-07-18 | 2016-09-13 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US9837271B2 (en) | 2014-07-18 | 2017-12-05 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| US10460932B2 (en) | 2017-03-31 | 2019-10-29 | Asm Ip Holding B.V. | Semiconductor device with amorphous silicon filled gaps and methods for forming |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59126680A (en) * | 1983-01-11 | 1984-07-21 | Mitsui Toatsu Chem Inc | Amorphous silicon solar battery and manufacture thereof |
-
1986
- 1986-06-24 JP JP14738086A patent/JPS633414A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59126680A (en) * | 1983-01-11 | 1984-07-21 | Mitsui Toatsu Chem Inc | Amorphous silicon solar battery and manufacture thereof |
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|---|---|---|---|---|
| JPH0335535A (en) * | 1989-06-30 | 1991-02-15 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film field effect transistor |
| US5607724A (en) * | 1991-08-09 | 1997-03-04 | Applied Materials, Inc. | Low temperature high pressure silicon deposition method |
| US5614257A (en) * | 1991-08-09 | 1997-03-25 | Applied Materials, Inc | Low temperature, high pressure silicon deposition method |
| US5700520A (en) * | 1991-08-09 | 1997-12-23 | Applied Materials, Inc. | Low temperature, high pressure silicon deposition method |
| US5874129A (en) * | 1991-08-09 | 1999-02-23 | Applied Materials, Inc. | Low temperature, high pressure silicon deposition method |
| US5876797A (en) * | 1991-08-09 | 1999-03-02 | Applied Materials, Inc. | Low temperature high pressure silicon deposition method |
| US6821825B2 (en) | 2001-02-12 | 2004-11-23 | Asm America, Inc. | Process for deposition of semiconductor films |
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| US8921205B2 (en) | 2002-08-14 | 2014-12-30 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
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| US7629270B2 (en) | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7674728B2 (en) | 2004-09-03 | 2010-03-09 | Asm America, Inc. | Deposition from liquid sources |
| US7732350B2 (en) | 2004-09-22 | 2010-06-08 | Asm International N.V. | Chemical vapor deposition of TiN films in a batch reactor |
| US7966969B2 (en) | 2004-09-22 | 2011-06-28 | Asm International N.V. | Deposition of TiN films in a batch reactor |
| US7674726B2 (en) | 2004-10-15 | 2010-03-09 | Asm International N.V. | Parts for deposition reactors |
| US7427571B2 (en) | 2004-10-15 | 2008-09-23 | Asm International, N.V. | Reactor design for reduced particulate generation |
| US7553516B2 (en) | 2005-12-16 | 2009-06-30 | Asm International N.V. | System and method of reducing particle contamination of semiconductor substrates |
| US7691757B2 (en) | 2006-06-22 | 2010-04-06 | Asm International N.V. | Deposition of complex nitride films |
| US7851307B2 (en) | 2007-08-17 | 2010-12-14 | Micron Technology, Inc. | Method of forming complex oxide nanodots for a charge trap |
| US8203179B2 (en) | 2007-08-17 | 2012-06-19 | Micron Technology, Inc. | Device having complex oxide nanodots |
| JP2009071290A (en) * | 2007-08-17 | 2009-04-02 | Semiconductor Energy Lab Co Ltd | Method for manufacturing semiconductor device |
| US9054206B2 (en) | 2007-08-17 | 2015-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
| US9443730B2 (en) | 2014-07-18 | 2016-09-13 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
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| US10460932B2 (en) | 2017-03-31 | 2019-10-29 | Asm Ip Holding B.V. | Semiconductor device with amorphous silicon filled gaps and methods for forming |
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| Publication number | Publication date |
|---|---|
| JPH0556852B2 (en) | 1993-08-20 |
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