JPS63316133A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To reduce an additional overhead and to contrive the speed up of an arithmetic processing, by providing a macroinstruction sequence processor other than a host processor, and taking over a direct instruction designating operation to an arithmetic unit by the processor. CONSTITUTION:The macroinstruction sequence processor 3 which issues an arithmetic execution instruction to the arithmetic unit 1 corresponding to a macroinstruction from the host processor 2 is also provided other than the processor 2. The interface 10 of the processor 3 is controlled via the interface 7 of the processor 2, and the processor 3 is operated synchronizingly with the processor 2, and the instruction of an arithmetic operation under execution for the unit 1 by the processor 3 via a multiplex unit 4 and data transfer by the processor 2, etc., are performed in parallel. In such a way, it is possible to reduce the additional overhead on the host processor, and to perform the arithmetic processing at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an arithmetic processing device that performs calculations such as numerical calculations, and in particular, by enabling parallel operation of an instruction execution sequence and a data input/output sequence, The present invention relates to a method for implementing an arithmetic processing device suitable for applications that can speed up arithmetic processing.

[Conventional technology]

Conventionally, when a host processor is connected to an arithmetic processing unit such as a floating point unit (FPU) to configure an arithmetic processing device that operates under the control of the host processor, for example, when performing scalar processing such as random arithmetic, The operation execution time is determined by the total value of overhead such as the transfer of operand data from the host processor to the arithmetic unit, the instruction of the arithmetic instruction, the execution of the operation by the arithmetic unit, and the transfer of result data from the arithmetic unit to the host processor. . In addition, when performing vector operations, transfer vector data of sufficient vector length from the host processor to the vector register of the vector operation unit, instruct vector operation instructions from the host processor to the vector operation unit, and The above two examples involve overheads such as performing vector arithmetic processing on all of the vector data and transferring the result data from the vector register to the main memory of the host processor. It's decided. This is because the arithmetic unit and host processor are connected on a one-to-one basis, and while the arithmetic unit is executing an arithmetic instruction, the host processor cannot access the register file in the arithmetic unit or perform the next instruction instruction operation. be. Note that this type of device is described in the literature [Nikkei Electronics 1986.7.14 (no.
399) J's P172. At P173, there is an arithmetic processing unit consisting of a conventional host processor and an arithmetic unit.

[Problem that the invention attempts to solve]

In the above-mentioned conventional technology, consideration is not given to random operations (scalar processing) and small-scale vector operations that require real-time processing, and in particular, the actual operation execution part, which involves a large amount of overhead, is based on VLSI technology. Nowadays, speeds are rapidly increasing due to advances, and in the above-mentioned random operations and small-scale vector operations, additional overhead such as necessary data and instruction exchange between the host processor and the operation unit is required, rather than the execution of the operation by the operation unit. is becoming much larger, which prevents improvements in speed and cost performance.

An object of the present invention is to provide a means for configuring an arithmetic processing device that can reduce the additional overhead associated with the arithmetic processing discussed above, reduce the overall arithmetic execution time, and increase the speed. be.

[Means for solving problems]

The above object is to provide a macro instruction sequence processor which is a second processor that shares an arithmetic unit in addition to the host processor, and to perform at least the instruction instruction operation ( The macro instruction sequence processor is equipped with a function equivalent to the function (program for describing the execution sequence of the arithmetic units supported on the host processor), and this second processor is responsible for directly issuing instructions to the arithmetic units. By replacing the access operation to the register file of the arithmetic unit performed by the host processor for the exchange of necessary data, the execution instruction operation of the arithmetic unit by the macro instruction sequence processor, and the actual operation of the arithmetic unit realized thereby. This is achieved by running the calculation execution process in parallel and additionally reducing overhead.

Instruction instruction operations between the host processor and the macro instruction sequence processor are performed by converting an operation execution sequence instruction instruction program to the arithmetic unit of the macro instruction sequence processor into macro instructions in units of one instruction or multiple instruction steps along the execution sequence. A method is adopted in which the host processor sequentially instructs the macroinstruction sequence processor to execute the sequence of macroinstructions using a simpler command instruction operation. Specifically, the host processor gives the number of instructions to be executed by the arithmetic unit as a macro instruction to the macro instruction sequence processor, while a counter counts the number of instructions executed by the arithmetic unit after the macro instruction is given. , means is provided to stop the operation of the macro instruction sequence processor when the number of instructions matches the number of instructions specified by the macro instruction, and to place the processor in a waiting state for the next macro instruction instruction.

On the other hand, as long as they do not match, it is assumed that the macro instruction is being executed, and means is provided for making the instruction of the next macro instruction wait until the execution is completed. In addition, the register file in the arithmetic unit is provided with a means that can be accessed without contradiction from the host processor even during the execution of an arithmetic operation, and the macro instruction sequence processor issues the number of arithmetic instructions to the arithmetic unit specified by the macro instruction. In parallel with this, the host processor performs operations such as transferring data required for the next macro instruction onto the register file of the arithmetic unit and obtaining past operation results from the register file of the arithmetic unit. conduct.

[Effect]

With the above means, even for random operations and small-scale vector operations, the only arithmetic processing overhead for the host processor is the transfer processing of operand data etc. and the instruction operation of very simple macro instructions, and these are Because the operation overlaps with the complex calculation instruction operation by the processor to the calculation unit,
Substantial additional overhead compared to traditional methods.

can be reduced and also has real-time performance.
゛It doesn't hurt that much. Especially regarding vector processing,
A relatively large number of arithmetic instructions can be combined into macro instructions, and most of the substantial overhead is vector data transfer processing. In addition, in vector processing, vector data is placed continuously in the main memory or the register file of the arithmetic unit, so data can be moved at high speed using transfer instructions, DMA, etc., making it possible to further reduce overhead. .

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 6.

FIG. 1 shows a block diagram of an arithmetic processing device of the present invention. This arithmetic processing device includes an arithmetic unit 1, a host processor 2 in which an arithmetic instruction sequence program is stored, and a host processor 2 that realizes a user's desired arithmetic function using the program.
．． It is composed of a macro instruction sequence processor 3 that instructs an operation unit in an operation execution sequence, and a multiplex unit 4 that is a means for the host processor 1 and the macro instruction sequence processor 3 to share the operation unit 1. Ru.

FIG. 2 shows a conventional arithmetic processing device composed of a host processor and an arithmetic unit.

The host processor 2 consists of a main memory 6, a CPU 5 and an interface circuit 7 which provides the necessary signals to the arithmetic unit. The interface circuit 7 does not need to be located on the host processor side;
and arithmetic unit 1.

Alternatively, the calculation unit 1 may be located on the calculation unit 1 side, and the calculation unit 1 is the micro sequencer 15. Macro code memory 16, control line generation circuit 17, execution unit 18 (ALU, multiplier, etc.) that executes calculations, register file 22
．． An instruction decoder 19 that analyzes instructions, and an internal path Q
Path buffer 2 for communicating the host processor to 1
Consists of 3rd class. In the arithmetic unit 1, addition, subtraction, multiplication, division, and various defined functions regarding the data on the register file 22 are realized as minimum arithmetic unit (basic arithmetic) functions. In this method, the host processor uses the interface circuit 7 and the path buffer 26 to instruct the register file 22 with the necessary address (corresponding to the register number), transfers the necessary data, and first sends an instruction to the instruction decoder 19. The microsequencer 15 is instructed to start up and perform necessary calculations. The host processor is made to wait for accessing the register file 22 and sending out the next instruction until the execution of the operation is completed, and when the operation is completed, the opening of the path buffer 23 is permitted by the control line Q2. FIG. 3 shows the calculation execution sequence. Data input/output between the host processor 2 and the arithmetic unit 1 is shown as D1 to D4, and steps 1 to 4 represent the sending of arithmetic instructions from the host processor 2 to the arithmetic unit 1, and steps 1 to 4 represent the sending of arithmetic instructions from the host processor 2 to the arithmetic unit. The execution is shown in E1-E4. The up and down arrows indicate the flow of operations. As shown in Figure 6, the flow of processing is serial, and each unit has a lot of idle time (indicated by dotted lines in the figure).

In the embodiment shown in FIG. 1, in addition to the host processor 2, there is provided a macro instruction sequence processor 3 capable of instructing the arithmetic unit 1 to instruct instructions in an arithmetic execution sequence. Macro instruction sequence processor 3
is CPU8. It has a local memory 9 and an interface circuit 10 that supplies necessary signals to the arithmetic unit, and has at least a connection path to an instruction decoder 19 in the arithmetic unit 1, and transmits arithmetic instructions to the arithmetic unit on behalf of the host processor. Commands must be possible. In this embodiment, the host processor 2 and the macro instruction sequence processor 3 share the arithmetic unit 1 through the multiplex unit 4. The multiplex unit 4 includes a multiplexer 11 that multiplexes instruction sending decoder lines, and a multiplexer 13 that multiplexes lines that input and output addresses and data necessary for arithmetic processing.
The arbiter 12 performs arbitration for the multiplex 13, and the arbiter 14 performs arbitration for the multiplex 13. In this example, the host processor and macro instruction sequence processor share only the instruction sending line,
Only a multiplexer 11 and an arbiter 12 are provided.

The roles of the host processor and the macro instruction sequence processor are completely separated, with the host processor 2 specializing in data input/output and receiving and waiting, and the macro instruction sequence processor 3 being specialized in sending arithmetic instructions to the arithmetic unit 1. In addition, the interface circuits 7 and 10 may include data lines for issuing macro commands from the host processor 2 to the macro command sequence processor 3 and for synchronizing processing sequences. It has a function to generate Q8. With this method, it is possible to operate at least data input/output operations from the host processor 2 and arithmetic instruction instruction operations from the macro instruction sequence processor 3 in parallel.

Inside the arithmetic unit 1, either an internal bus Q1 consisting of a data bus on the execution unit 18 side and an address bus Qss from the control line generation circuit 17, or a pass line Q4 on the host processor 2 side is connected to the register file 22. Switch control is performed by an arbiter circuit 20 that arbitrates and activates the access request and permission line Q11 from the microsequencer side and the access request and permission line Q6 from the host processor side. . by this,
Even when the execution unit 18 is operating, the register file 22
Most of the time that is not considered to be used by the execution unit can be used by the host processor 2 to access the register file 22. Therefore, data input/output operations of the host processor 2 and arithmetic execution processing of the arithmetic unit 1 can be operated in parallel.

FIG. 4 shows the arithmetic processing of this embodiment described above, and is shown in correspondence with FIG. 3 which is a conventional example. First, the host processor 2 loads the data Di and D2 onto the register file 22 in the arithmetic unit 1, and then instructs the macro instruction sequence processor 3 to issue the first macro instruction MII. Macro instruction instructions execute simplified code, so execution time can be shortened. The macro instruction MII indicates two groups MIOI of actual basic unit instructions II and I2 in the arithmetic unit 1, and the macro instruction sequence processor 3 sends instructions II and I2 to the arithmetic unit 1 in the order. , returns to the state of waiting for the next macro instruction. On the other hand, the arithmetic unit 1 executes basic arithmetic operations El corresponding to I1 and E2.

E2 is executed, during which the host processor 2 transfers the next required data D3 and D4 to the register file 2 in parallel.
2. Perform the operation to load onto the screen. It can be seen that the idle time of each unit is shortened and the efficiency is nearly twice that of the conventional example shown in FIG. 3, in which processing is subsequently executed in the same manner.

FIG. 5 shows a block diagram of a macro instruction instruction circuit from the host processor 2 to the macro instruction sequence processor 3 in the interface 10, and a circuit necessary for sequence synchronization between the two processors. The interface 10 generates a signal line UXO that sends instruction data to the multiplexer 11, requests the arbiter 12 to access the instruction decoder 19 of the arithmetic unit 1, and generates a grant line QIZ and a pulse every time an instruction is sent. A signal control circuit 23 that generates a signal line Q9 that sends a signal line Q9 to the clock input of a counter circuit 24 from a signal of the CPU 8, and a counter circuit 24 that counts the number of executed operation instructions. and a latch circuit 25 that latches the number of execution instructions sent from the host processor 2.

FIG. 6 shows the composition means and execution method of macro instructions sent from the host processor 2 to the macro instruction sequence processor. From host processor 2, OUT
A simple instruction having a short execution time, such as an instruction, instructs the number of calculation instructions to be executed next by the macro instruction sequence processor 3 and the calculation unit 1. The designated number of instructions is stored in the latch circuit 25 in FIG. 5, and this becomes the macro instruction itself. If the previous macro instruction has been completed, the latch data is loaded into the counter circuit 24, and each time an arithmetic instruction is sent out, it is decremented by 1 by a pulse signal from the signal line QB, until the counter value becomes zero. At this time, a zero count signal is sent to signal line Q7. When the signal line Q7 is activated by the zero count signal, the host processor 2 knows that the next macro instruction can be specified, and sends the number of arithmetic instructions to be executed next to the latch circuit 25 as a macro instruction. As shown in Figure 6, macro instruction 1 (MII) is a command to execute three operation instructions, and is written as 0UT3 (to execute n instructions, it is written as 0UTn). . When this is sent to the macro instruction sequence processor 3, if the previous macro instruction processing has not been completed, the host processor 2 side, as indicated by MI3 in the figure, is forced to wait until the currently executing macro instruction is completed. Similarly, if there is a delay in sending a macro instruction from the host processor 2 side, the macro instruction sequence processor 3 side will have to wait until the next macro instruction is instructed (indicated by WAIJ in the figure), and the arithmetic unit 1 will , the basic operation instructions (If, Iz
,...) are executed as they are (El, Ex...).

According to this method, the macro instruction sequence processor 3
The program on the side can be written as a conventional operation execution sequence, and it can be freely divided into macro instructions. Therefore, the object program executed by the macro instruction sequence processor 3 can be run as is on the host processor 2. In addition, the macro instruction instruction can be a simple one such as an OUT instruction, and if the address output line is used, it can be realized with one machine instruction.This, together with the effect of consolidating operations, reduces the overhead associated with instruction instruction. can do.

〔Effect of the invention〕

According to the present invention, the data input/output operation between the host processor and the arithmetic unit necessary for instruction processing, the arithmetic instruction instruction operation executed by the macro instruction sequence processor, and the arithmetic execution processing in the arithmetic unit are operated in parallel. Therefore, it is possible to reduce the additional overhead associated with calculation processing, shorten the overall calculation processing time, and speed up the processing.

[Brief explanation of drawings]

Fig. 1 shows an embodiment of the present invention, Fig. 2 shows a conventional example, Fig. 3 shows an arithmetic processing sequence in the conventional example, and Fig. 4 shows an arithmetic processing sequence in this embodiment. FIG. 5 is a block diagram of the macro instruction instruction circuit section, and FIG. 6 is a diagram showing the macro instruction configuration means and execution method. 1... Arithmetic unit, 2... Host processor, 3
... Macro instruction sequence processor, 4... Multiplex unit, 10... Interface, 1
8... Execution unit, 19... Instruction decoder, 20
... bus arbiter, 21 ... multiplexer, 22
...Register file, 24...Counter circuit, 2
5...Latch circuit. Figure B

Claims (1)

[Scope of Claims] 1. Includes an arithmetic unit that executes arithmetic processing, a first processor that has an instruction instruction function for an arithmetic execution sequence to be executed by the arithmetic unit, and a data input/output operation function necessary for the arithmetic operation. The arithmetic processing device includes a second processor that shares an arithmetic unit with the first processor and has at least the instruction instruction function, and the instruction instruction operations of the arithmetic execution sequence of the second processor are summarized for each instruction step. , an arithmetic processing device characterized in that the first processor instructs the assembled instruction steps to the second processor to control an instruction instruction sequence to an arithmetic unit of the second processor. 2. The arithmetic processing device according to claim 1, wherein the first processor and the second processor operate according to the same machine instruction. 3. The arithmetic processing device according to claim 1, wherein the first processor has a data transfer function with a register file of the arithmetic unit. 4. The arithmetic processing device according to claim 1, wherein the instruction step is at least one instruction step that is executed continuously. 5. An arithmetic processing device that includes an arithmetic unit that executes arithmetic processing, and a first processor that has an instruction instruction function for an arithmetic execution sequence to be executed by the arithmetic unit and an input/output function for data necessary for the arithmetic operation; a second processor that shares an arithmetic unit with the first processor and has at least the instruction instruction function; a means for summarizing the instruction instruction operations of the arithmetic execution sequence of the second processor into macro instructions for each instruction step; and summarization thereof; 1. An arithmetic processing device, comprising means for parallelly executing an arithmetic execution operation of the second processor and a data transfer operation with an arithmetic unit by the first processor, which are executed for each macro instruction issued by the second processor. 6. The arithmetic processing device according to claim 5, wherein the data transfer operation is a data transfer operation between a storage means of the first processor and a register file of the arithmetic unit. 7. An arithmetic processing device including a first processor having an arithmetic unit that executes arithmetic processing, a command instruction function for an arithmetic execution sequence to be executed by the arithmetic unit, and an input/output function for data necessary for the arithmetic operation, a second processor that shares an arithmetic unit with the first processor and has at least the instruction instruction function; a means for organizing instruction instruction operations of the operation execution sequence of the second processor into macro instructions for each instruction step; A means for instructing a macro instruction, which is the number of arithmetic instructions to be executed in an arithmetic unit, from a first processor to a second processor, and a means for latching the instructed number of instructions and executing a macro instruction each time an instruction is executed in an arithmetic unit. means for counting the number of arithmetic instructions for operating a second processor until the number matches the number of instructed instructions; An arithmetic processing device comprising means for stopping the operation of a first processor until execution of a macro instruction therein is completed.