JPS63313839A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63313839A JPS63313839A JP14905087A JP14905087A JPS63313839A JP S63313839 A JPS63313839 A JP S63313839A JP 14905087 A JP14905087 A JP 14905087A JP 14905087 A JP14905087 A JP 14905087A JP S63313839 A JPS63313839 A JP S63313839A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- layer
- electrode
- silver paste
- oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000010931 gold Substances 0.000 claims abstract description 33
- 229910052737 gold Inorganic materials 0.000 claims abstract description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052709 silver Inorganic materials 0.000 claims abstract description 10
- 239000004332 silver Substances 0.000 claims abstract description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 1
- 239000011651 chromium Substances 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000010936 titanium Substances 0.000 claims 1
- 229910052720 vanadium Inorganic materials 0.000 claims 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 16
- 239000000463 material Substances 0.000 abstract 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
この発明は、 IC,LSI、)ランシスター、ダイ
オード等の半導体素子から電気信号を人出方する電極部
分の構造を改良した半導体装置に関する。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) This invention improves the structure of the electrode part that outputs electrical signals from semiconductor elements such as ICs, LSIs, Runsisters, and diodes. The present invention relates to a semiconductor device.
(従来の技術)
従来、半導体素子から信号を取出す場合、半導体素子上
に形成されたアルミニウム電極にAuワイヤーをボンデ
ングする方法とか、電極上にAuメツキでパッドを形成
しリードを熱圧着するTABと呼ばれる方法などがある
。(Prior art) Conventionally, when extracting signals from a semiconductor element, there have been methods such as bonding an Au wire to an aluminum electrode formed on the semiconductor element, and TAB, which forms a pad with Au plating on the electrode and thermocompresses the lead. There are many ways to call it.
これ等の方式では、 ICからリードを取出して基板に
取付けるスペースが必要で、ICの大きさよシも敷地面
積が数倍大きくなる。These methods require space to take out the leads from the IC and attach them to the board, and the site area becomes several times larger than the size of the IC.
例えば第4図(a)では、ワイヤーボンディングを示し
ているが、 ICの大きさをA%敷地面積をBとしであ
る。第4図(b)では、 TABの場合を示し同様にI
Cの大きさをA1敷地面積なりとしである。For example, FIG. 4(a) shows wire bonding, where the IC size is A and the site area is B. Figure 4(b) shows the case of TAB and similarly I
The size of C is the area of A1 site.
いずれもBがAの2倍よ)大きい。In both cases, B is twice as large as A).
この様な問題が無い方法としては、半田をバンプとして
ICの上に形成する方法もある。この様な方法では、基
板とICが強固に接着される為、熱膨張のストレスが不
均一にかかる事も多く、接続の信頼性に問題が多い。As a method that does not have such problems, there is also a method of forming solder as bumps on the IC. In such a method, since the substrate and the IC are firmly bonded, stress due to thermal expansion is often applied unevenly, and there are many problems with connection reliability.
゛以上のような問題点を解決する方法として、ICよシ
直接配線を施す方法も提案されている。この方法の一つ
として、ICをプラスチックシートに埋め込み、 IC
の電極に直接配線を施す方法も取られている。A method of directly wiring the IC has also been proposed as a method to solve the above-mentioned problems. One way to do this is to embed an IC in a plastic sheet.
Another method is to directly wire the electrodes.
この様な方式の問題点は1.υ電極の表面が酸化してい
て1M電極と銀ペーストの間にオーミックコンタクトが
取れず、抵抗が大きくなるという問題が有シかつ信号の
電圧降下が大きく動作しなくなる事も多い。The problems with such a method are 1. Since the surface of the υ electrode is oxidized, ohmic contact cannot be made between the 1M electrode and the silver paste, resulting in a problem of increased resistance and a large voltage drop in the signal, often resulting in inoperability.
(発明が解決しようとする問題点)
この問題点を解決する方法として、M電極上にAuポー
ルをボンディングする方法も提案されている。しかし、
この様な方法ではAuボールをボンディングする作業が
繁雑であシ、高価であるという問題がある。(Problem to be Solved by the Invention) As a method for solving this problem, a method of bonding an Au pole onto the M electrode has also been proposed. but,
This method has the problem that the work of bonding the Au balls is complicated and expensive.
本発明は、この様な問題を解決するために低価格で信頼
性の高い接続構造をもった半導体装置を提案するもので
ある。The present invention proposes a semiconductor device having a low cost and highly reliable connection structure in order to solve such problems.
(問題点を解決するための手段と作用)本発明は、si
基板上のAJ電極上に、Cr/Au。(Means and effects for solving the problems) The present invention provides si
Cr/Au on the AJ electrode on the substrate.
Cr/Pd/Au 、Ti/Au 、Ti/Pd/Au
、Ti/Ni/Au 、Cr/Pd/Auの層を形成
したあと、この表面に銀エポキシペーストにて接続した
電極を有する半導体であl:r 、AIの生じる酸化物
を導電性酸化物に変換することにより、得られる低価格
で信頼性の高い半導体装置である。Cr/Pd/Au, Ti/Au, Ti/Pd/Au
After forming layers of , Ti/Ni/Au, Cr/Pd/Au, a semiconductor having electrodes connected to the surface with silver epoxy paste is used. This conversion results in a low-cost and highly reliable semiconductor device.
(実施例) 本発明の実施例を図にて説明する。(Example) Embodiments of the present invention will be described with reference to the drawings.
第1図に於いて、基板1には、 St、GaAs等の半
導体素子が設けられている。この素子の上には、υ電極
(2)とM(2)の上に形成されたCr (3)、 A
u (4)が設けられている。In FIG. 1, a substrate 1 is provided with semiconductor elements such as St and GaAs. On this element, Cr(3) and A are formed on the υ electrode (2) and M(2).
u (4) is provided.
Cr0代わシにTI%又は、Auと接着層の間に拡散防
止層としてPd 、Ni等をCrとAuまたは、Tiと
Au0間に入れてもよい。Instead of Cr0, TI% or Pd, Ni, etc. may be inserted between Cr and Au or between Ti and Au0 as a diffusion prevention layer between Au and the adhesive layer.
この様な接着層、拡散防止層およびAuの組合わせであ
るCr/Au、Crハ1/Au、Ti/Au、Ti/P
d/Au。Such combinations of adhesive layer, diffusion prevention layer and Au such as Cr/Au, Cr1/Au, Ti/Au, Ti/P
d/Au.
T 1 /N i/Au 、 Cr/P d/Au等メ
タライゼーションはよく知られたメタライゼーシヨンで
ある。Metalizations such as T 1 /N i /Au, Cr/P d /Au, etc. are well-known metallizations.
しかし、半導体素子のM電極上にT1またはCrを形成
する事によル1.υの表面を酸化から保護すると同時に
、薄い酸化膜でもTI tたけCrの酸化生成自由エネ
ルギーにより、新たに、 Aloの形からAlto−C
rまたはAI!−0−TIの導電性酸化物へ変化して、
信頼性の高いものとなる。However, by forming T1 or Cr on the M electrode of the semiconductor element, method 1. At the same time, it protects the surface of υ from oxidation, and even with a thin oxide film, due to the free energy of oxidation of Cr, the shape of Alto-C is changed from Alo to Alto-C.
r or AI! -0-TI changes into a conductive oxide,
It becomes highly reliable.
を極部分の断面を第2図に示す。又、同時に。Figure 2 shows a cross section of the pole part. Also, at the same time.
金と銀ペーストが接触して安定になる。この接触抵抗の
変化を、@3図に示めす。第3図で#′i、AI *極
に銀ペーストを付けた場合とAu電極に銀ペーストを付
けた場合を比較したものを示す。The gold and silver paste come into contact and become stable. This change in contact resistance is shown in Figure @3. FIG. 3 shows a comparison between the case where silver paste is attached to the #'i, AI* electrode and the case where silver paste is attached to the Au electrode.
AI電極に銀ペーストを付けた場合は、電流が増加する
にしたがって接触抵抗が増大するのに対して%Au電極
に銀ペーストを付けた場合Fi、接触抵抗が増大しない
。この様に、A11を極にCr/Au。When the silver paste is attached to the AI electrode, the contact resistance increases as the current increases, whereas when the silver paste is attached to the Au electrode, the contact resistance does not increase. In this way, Cr/Au with A11 as the pole.
Cr/N i/Au 、T i/Au 、T i/Pd
/Au 、T i/N1/Atr 。Cr/N i/Au , T i/Au , T i/Pd
/Au, T i/N1/Atr.
Cr/Pd/Auを付ける方法としては、蒸着、スパッ
ターあるいはイオンブレーティング等がある。パッドの
形状には、フォトリソグラフィーを用いる事が出来る。Methods for applying Cr/Pd/Au include vapor deposition, sputtering, and ion blasting. Photolithography can be used to shape the pad.
実際に用いたCrとT1の厚さは50nm〜500 n
m 、NiとPdの厚さは0〜500mm である。辷
れは、 TABやワイヤボンディングの場合のように、
金の厚さを厚くする必要が無いことを示してお〕、本発
明が資源を節約する方法であるζとを示している。The thickness of Cr and T1 actually used was 50 nm to 500 nm.
m, the thickness of Ni and Pd is 0 to 500 mm. As in the case of TAB and wire bonding,
This shows that there is no need to increase the thickness of the gold and shows how the invention saves resources.
本発明によれば、低価格で、安定性の高い接続構造を有
する半導体装置を構成できる。According to the present invention, a semiconductor device having a highly stable connection structure can be constructed at low cost.
第1図は本発明の実施例の要部を示す部分断面図、第2
図は本発明の他の実施例を示す部分断面図、第3図は本
発明の詳細な説明する曲線図、第4図は従来の半導体装
置を示す平面図である。
l・・・基板、 2・・・11% 3・・・Cr、’4
・・・Aug1代理人 弁理士 則 近 憲 佑
同 松山光之
rlJe恒−AL!ぺ一人ト
電流
へハFIG. 1 is a partial sectional view showing the main parts of an embodiment of the present invention, and FIG.
The figure is a partial sectional view showing another embodiment of the present invention, FIG. 3 is a curve diagram explaining the present invention in detail, and FIG. 4 is a plan view showing a conventional semiconductor device. l...Substrate, 2...11% 3...Cr, '4
...Aug1 agent Patent attorney Nori Chika Ken Yudo Mitsuyuki Matsuyama rlJe Tsune-AL! To personal current
Claims (7)
アルミニウム層と、このアルミニウム層の表面に設けら
れアルミニウムの酸化により生ずる酸化物を導電性酸化
物に変換する物質からなる接着層と、この接着層の表面
に設けた金層と、この金層に接して設けられ電気を取出
す銀ペーストとで構成した電極部を具備したことを特徴
とする半導体装置。(1) an aluminum layer provided on the surface of the semiconductor substrate and forming part of the electrode; an adhesive layer provided on the surface of the aluminum layer and made of a substance that converts an oxide produced by oxidation of aluminum into a conductive oxide; A semiconductor device characterized by comprising an electrode portion comprising a gold layer provided on the surface of the adhesive layer and a silver paste provided in contact with the gold layer to extract electricity.
ことを特徴とする特許請求の範囲第1項記載の半導体装
置。(2) The semiconductor device according to claim 1, wherein the gold layer is formed to have a thickness of 50 to 500 nm.
いずれか一種からなることを特徴とする特許請求の範囲
第1項記載の半導体装置。(3) The semiconductor device according to claim 1, wherein the adhesive layer is made of any one of chromium, titanium, and vanadium.
ることを特徴とする特許請求の範囲第3項記載の半導体
装置。(4) The semiconductor device according to claim 3, wherein the adhesive layer is formed to have a thickness of 50 to 500 nm.
特徴とする特許請求の範囲第1項記載の半導体装置。(5) The semiconductor device according to claim 1, characterized in that a diffusion prevention layer is provided between the adhesive layer and the gold layer.
徴とする特許請求の範囲第5項記載の半導体装置。(6) The semiconductor device according to claim 5, wherein the diffusion prevention layer is made of nickel or lead.
いることを特徴とする特許請求の範囲第6項記載の半導
体装置。(7) The semiconductor device according to claim 6, wherein the diffusion prevention layer is formed to have a thickness of 0 to 500 nm.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14905087A JPS63313839A (en) | 1987-06-17 | 1987-06-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14905087A JPS63313839A (en) | 1987-06-17 | 1987-06-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63313839A true JPS63313839A (en) | 1988-12-21 |
Family
ID=15466555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14905087A Pending JPS63313839A (en) | 1987-06-17 | 1987-06-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63313839A (en) |
-
1987
- 1987-06-17 JP JP14905087A patent/JPS63313839A/en active Pending
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