JPS63307758A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPS63307758A JPS63307758A JP14461287A JP14461287A JPS63307758A JP S63307758 A JPS63307758 A JP S63307758A JP 14461287 A JP14461287 A JP 14461287A JP 14461287 A JP14461287 A JP 14461287A JP S63307758 A JPS63307758 A JP S63307758A
- Authority
- JP
- Japan
- Prior art keywords
- fuse
- film
- integrated circuit
- cavity
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 239000011521 glass Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000007575 Calluna vulgaris Nutrition 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 240000002804 Calluna vulgaris Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路装置に関し、特に多結晶７リコンから
なるヒユーズを有する集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having a fuse made of a polycrystalline 7-licon.
従来、多結晶シリコンからなるヒユーズ（以下単にヒー
スと称す）を有する集積回路装置においては、ヒユーズ
は、拡散領域または、多結晶シリコン等で形成した抵抗
の微調整の手段として多く使用されており、抵抗値の違
う何種類かの抵抗に各々並列にヒユーズを接続し、順次
このヒユーズを切断することで微調整が行なわれる。Conventionally, in integrated circuit devices having fuses made of polycrystalline silicon (hereinafter simply referred to as heathers), the fuses are often used as a means for finely adjusting resistance formed in diffusion regions or polycrystalline silicon, etc. Fine adjustment is performed by connecting fuses in parallel to several types of resistors with different resistance values, and sequentially cutting the fuses.
このヒースの切断は、ヒユーズの両端に電圧を印加して
切断するか、或はレーザーにて切断する方法が用いられ
ている。The heather is cut by applying a voltage to both ends of the fuse or by using a laser.
第３図は一般に使用されている集積回路のヒユーズの切
断部近傍の断面図を示している。また第４図（ａｌはヒ
ユーズの切断金谷易にするためヒユーズの上面及び側面
の保護膜であるリンガラス膜４及びＳ ｉ ３ Ｎ４膜
１１を除去した構造の断面図である。FIG. 3 shows a cross-sectional view of the vicinity of the cut portion of a commonly used integrated circuit fuse. FIG. 4 (al) is a cross-sectional view of the structure in which the phosphor glass film 4 and the Si 3 N 4 film 11, which are protective films on the upper and side surfaces of the fuse, have been removed to facilitate cutting of the fuse.
この場合、ヒユーズ３を切断したのちは第４図（ｂｌに
示すように、耐湿性向上のため切断部を含む全面に保護
膜としてＳ＋３Ｎ４膜１３等が被服される。In this case, after the fuse 3 is cut, as shown in FIG. 4 (bl), the entire surface including the cut portion is coated with an S+3N4 film 13 or the like as a protective film to improve moisture resistance.
しかしながら、第３図に示したような構造のヒユーズに
電圧を印加して切断する場合は、切断されたヒユーズの
多結晶シリコンが切断箇所に散乱して再付着するため、
高抵抗で接続しｒ２）、集積回路装置の動作中における
、熱或は電界等のストレスなどにより再接続する場合が
あり信頓性上問題があった。However, when applying a voltage to a fuse with the structure shown in FIG.
When connected with high resistance (r2), reconnection may occur due to stress such as heat or electric field during operation of the integrated circuit device, which poses a reliability problem.
また第４図（ａｌに示したように、ヒユーズ上に穴を明
ける構造の場合は、前述のような問題は生じないが、切
断した箇所には保護膜がないため湿気等の侵入により再
接続されることがある。この対策としては、耐湿性の良
いケースを使用して湿気の侵入を防ぐか、或は第４図（
ｂｌのようにヒユーズを切断した後、再び保護膜を被服
することで対処可能でちる。しかし前者は耐湿性の良い
ケースを使用するため高価なものになり、後者は一度ワ
エバーテスターにて切断した後、保護膜を被服するため
、製造工程が複雑になる他、保護膜を被膜することで調
整した抵抗値が変化することがあるなどの欠点がある。In addition, as shown in Figure 4 (al), in the case of a structure in which a hole is drilled above the fuse, the above-mentioned problem does not occur, but since there is no protective film at the cut point, reconnection may occur due to intrusion of moisture etc. To prevent this, use a moisture-resistant case to prevent moisture from entering, or use the case shown in Figure 4 (
This can be dealt with by cutting the fuse as in bl and then covering it again with a protective film. However, the former is expensive because it uses a case with good moisture resistance, and the latter is cut with a Waeber tester and then coated with a protective film, which complicates the manufacturing process and requires the use of a protective film. This has the disadvantage that the adjusted resistance value may change.
一方第３図に示した構造のヒユーズをレーザーにて切断
する場合は、とニーズと同時にその上におる保護膜にも
穴があけられるため、再付着による問題は生じないが、
湿気等に対しては第４図（ａ）に示したものと同様の問
題がある。On the other hand, when cutting the fuse with the structure shown in Figure 3 using a laser, a hole is made in the overlying protective film at the same time as the fuse is cut, so there is no problem with re-adhesion.
Regarding moisture, etc., there is a problem similar to that shown in FIG. 4(a).
本発明の目的は、多結晶シリコンからなるヒエーズ企切
断した場合、散乱した多結晶シリコンにより再接続する
ことがなく、シかも耐湿性の良好な集積回路装置を提供
することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device that does not cause reconnection due to scattered polycrystalline silicon when a wire made of polycrystalline silicon is cut, and has good moisture resistance.
本発明の集積回路装置は、半導体基板上に絶縁＠を介し
て形成された多結晶クリコ／からなるヒユーズを有する
集積回路であって、前記ヒユーズの切断領域部の上部近
傍に空洞部を設けたものである。The integrated circuit device of the present invention is an integrated circuit having a fuse made of polycrystalline Crico formed on a semiconductor substrate with an insulator interposed therebetween, wherein a cavity is provided in the vicinity of the upper part of the cutting area of the fuse. It is something.
次に、不発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（Ｃ）は本発明の一実施例の平面図、Ａ
−Ａ’ 線断面図及びＢ−Ｂ’線断面図であり、平面図
は特にヒユーズのみを示している。FIGS. 1(a) to 1(C) are plan views of one embodiment of the present invention, A
-A' line sectional view and BB' line sectional view, and the plan view particularly shows only the fuse.
第１図（ａ）〜（Ｃ１において、シリコン基板１上ｖｃ
は、５ｉ０２膜２を介して多結晶シリコンからなるヒユ
ーズ３が形成されており、その周辺にはリンガラス膜４
ｇ ８１３ Ｎ４膜８．１１が形成されているが、特
にヒユーズ３の切断領域部の上部近傍には空洞部１２が
設けられている。In FIGS. 1(a) to (C1, vc on silicon substrate 1)
A fuse 3 made of polycrystalline silicon is formed through a 5i02 film 2, and a phosphorus glass film 4 is formed around it.
Although the g 813 N4 film 8.11 is formed, a cavity 12 is provided particularly near the upper part of the cutting area of the fuse 3.
次に本実施例の製造方法について第２図を併用して説明
する。Next, the manufacturing method of this example will be explained with reference to FIG. 2.
まず第２図（ａｌに示すように、８ｉ０ｚ膜２の形成さ
れたシリコン基板１上に多結晶シリコン膜を形成し、バ
ターニングしてヒユーズ３を形成する。次で全面にリン
ガラス膜を形成する。First, as shown in FIG. 2 (al), a polycrystalline silicon film is formed on the silicon substrate 1 on which the 8i0z film 2 is formed, and then buttered to form the fuse 3. Next, a phosphor glass film is formed on the entire surface. do.
次に第２図（ｂｌに示すように、レジスト膜５をマスク
にしてヒユーズ３の切断領域部近傍のリンガラス膜４を
エラテンブレ除去する。Next, as shown in FIG. 2 (bl), using the resist film 5 as a mask, the phosphor glass film 4 in the vicinity of the cutting area of the fuse 3 is removed as an eternity.
次に第２図（Ｃ）に示すように、レジスト＠５を除去し
た部分を含む全面にアルミニワム膜６ｆｔ形成する０
次に第２図（ｄ）に示すように、レジスト膜７をマスク
にして、アルミニツム膜６の不要な領域を除去する。Next, as shown in FIG. 2(C), 6ft of aluminum film is formed on the entire surface including the part where the resist@5 was removed.Next, as shown in FIG. 2(d), using the resist film 7 as a mask, , removing unnecessary areas of the aluminum film 6.
次に第２図（ｅｌに示すように、レジスト膜７を除去し
た後、８ｉ１Ｎ４膜８を形成し、さらにレジスト膜９を
マスクにしてアルミニツム膜６上のＳ ｉ ｓ Ｎ４膜
８の一部を除去し開孔部１４を形成する。Next, as shown in FIG. 2 (el), after removing the resist film 7, an 8i1N4 film 8 is formed, and using the resist film 9 as a mask, a part of the SiS N4 film 8 on the aluminum film 6 is removed. The opening portion 14 is then removed.
次に第２図げ）に示すように、レジスト膜９を除去した
のち、新たに形成したレジスト膜１０をマスクにしてア
ルミニツム膜６をドライまたはシェツトエツチング法に
より除去する。Next, as shown in Figure 2), after removing the resist film 9, the aluminum film 6 is removed by dry or sheet etching using the newly formed resist film 10 as a mask.
次に全面に保護膜として８ｉ１Ｎ４膜１１を形成するこ
とにより、第１図（ｂｌに示したように、ヒユーズ３の
切断領域部近傍に空洞部１２を有する集積回路装置が完
成する。Next, by forming an 8i1N4 film 11 as a protective film over the entire surface, an integrated circuit device having a cavity 12 near the cutting area of the fuse 3 is completed, as shown in FIG.
以上説明した構造のヒユーズは、従来の集積回路の製造
工程に第２図（ｆｌの工程を追加するだけで実現できる
。The fuse having the structure described above can be realized by simply adding the step shown in FIG. 2 (fl) to the conventional integrated circuit manufacturing process.
例えばＭＯ８型集積回路装置の場合第２図（ａ）に示し
たヒユーズ３は多結晶シリコンからなるゲート電極の形
成工程で、第２図（ｂ）に示したリンガラス層４の除去
は、拡散層との接続を得るための工程で、第２図（Ｃ）
及び（ｄ）に示したアルミニクム膜６の形成とエツチン
グはアルミニクム配線工程で、また第２図＜６）〜（ｆ
）に示した工程は、保護膜形成工程でそれぞれ同時に行
なえる。For example, in the case of an MO8 type integrated circuit device, the fuse 3 shown in FIG. 2(a) is formed in the step of forming a gate electrode made of polycrystalline silicon, and the removal of the phosphor glass layer 4 shown in FIG. 2(b) is performed by diffusion. Figure 2 (C)
The formation and etching of the aluminum film 6 shown in FIG.
The steps shown in ) can be performed simultaneously in the protective film forming step.
このように構成された本実施例においては、ヒユーズ切
断領域部の上部近傍に空洞部１２が形成されているため
、ヒユーズを切断した場合でも、ヒ為−ズを構成する多
精晶シリコンは広い空洞部に散乱するためヒユーズが再
接続されることはない。更に、空洞部はＳｉ３Ｎ４膜１
１で密封され勉るため、耐湿性も向上したものとなる。In this embodiment configured in this way, since the cavity 12 is formed near the upper part of the fuse cutting area, even if the fuse is cut, the polycrystalline silicon constituting the fuse is wide. The fuse is not reconnected because it is scattered into the cavity. Furthermore, the cavity is covered with a Si3N4 film 1.
Since it is sealed in 1, it has improved moisture resistance.
尚、本発明は多層配線構造の集積回路装置にも適用でき
る。例えばアルミニクムの２層配線構造の場合は第２図
（ｆ）に示した工程の後にレジスト膜１０を除去し第２
のアルミニワム膜１４を形成すればよく、この状態を第
２図（ｇ）に示す。Incidentally, the present invention can also be applied to an integrated circuit device having a multilayer wiring structure. For example, in the case of a two-layer wiring structure made of aluminum, the resist film 10 is removed after the step shown in FIG.
It is sufficient to form an aluminum wafer film 14 of 1500 mL, and this state is shown in FIG. 2(g).
以上説明したように本発明は、集積回路装置に形成した
多結晶シリコンからなるヒーズの切断領域部の上部近傍
に空洞部を設けることにより、ヒユーズ切断時に多結晶
シリコンが散乱して再付着しても、散乱する領域が広い
ためヒユーズが再接続するのを防止できる効果がある。As explained above, the present invention provides a cavity in the vicinity of the upper part of the cutting region of the fuse made of polycrystalline silicon formed in the integrated circuit device, so that the polycrystalline silicon is scattered and reattached when the fuse is cut. Also, since the scattering area is wide, it is effective in preventing the fuse from reconnecting.
また、空洞部を絶縁膜で密封することにより耐湿性も向
上するため安価な樹脂ケースを使用することもできる。Further, by sealing the cavity with an insulating film, moisture resistance is improved, so an inexpensive resin case can be used.
第１図（ａ）〜（Ｃ１は本発明の一実施例の上面図、Ａ
ＡＦ線断面図及びＢ−Ｂ’線断面図、第２図（ａｌ〜（
ｇ）は本発明の一実施例の製造方法を説明するための工
程順に示した半導体チップの断面図、第３図及び第４図
（ａｌ 、 （ｂｌは従来の集積回路装置の断面図であ
る。
１・・・・・・シリコン基板、２・・・・・・５ｉ０１
膜、３・・・・・・ヒユーズ、４・・・・・・リンガラ
ス膜、５・・・・・・レジスト膜、６・・・・・・アル
ミニワム膜、７・・・・・・レジスト膜、８・・・・・
・８ｉ３Ｎ４膜、９．１０・・・・・・レジスト膜、１
１・・・・・・Ｓｉ３Ｎ４膜５１２・・・・・・空洞部
、１３・・・・・・Ｓｔ、Ｎ４膜、１４・・・・・・ｔ
ＩＪ′ｌ托部。
男ｊ図FIGS. 1(a) to (C1 are top views of one embodiment of the present invention, A
AF line sectional view and BB' line sectional view, Figure 2 (al~(
g) is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method of an embodiment of the present invention, and FIGS. 3 and 4 (al and (bl) are cross-sectional views of a conventional integrated circuit device. 1...Silicon substrate, 2...5i01
Film, 3... Fuse, 4... Phosphorous glass film, 5... Resist film, 6... Aluminum membrane, 7... Resist. Membrane, 8...
・8i3N4 film, 9.10...Resist film, 1
1...Si3N4 film 512...Cavity part, 13...St, N4 film, 14...T
IJ'l Tsubu. man j figure
Claims (2)
シリコンからなるヒューズを有する集積回路装置におい
て、前記ヒューズの切断領域部の上部近傍に空洞部を設
けたことを特徴とする集積回路装置。(1) An integrated circuit device having a fuse made of polycrystalline silicon formed on a semiconductor substrate with an insulating film interposed therebetween, characterized in that a cavity is provided in the vicinity of the upper part of the cutting region of the fuse. Device.
とする特許請求範囲（１）項記載の集積回路装置。(2) The integrated circuit device according to claim (1), wherein the cavity is sealed with an insulating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14461287A JPS63307758A (en) | 1987-06-09 | 1987-06-09 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14461287A JPS63307758A (en) | 1987-06-09 | 1987-06-09 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63307758A true JPS63307758A (en) | 1988-12-15 |
Family
ID=15366076
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14461287A Pending JPS63307758A (en) | 1987-06-09 | 1987-06-09 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63307758A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0783182A3 (en) * | 1996-01-08 | 1998-01-21 | Siemens Aktiengesellschaft | Fuse in a semiconductor integrated circuit |
| EP1032040A2 (en) * | 1999-02-26 | 2000-08-30 | International Business Machines Corporation | Metal wire fuse structure with cavity |
| WO2001018863A1 (en) * | 1999-09-09 | 2001-03-15 | Infineon Technologies North America Corp. | Method for manufacturing fusible links in a semiconductor device |
| US6524941B2 (en) | 1998-06-08 | 2003-02-25 | International Business Machines Corporation | Sub-minimum wiring structure |
| WO2007017672A1 (en) * | 2005-08-05 | 2007-02-15 | Cavendish Kinetics Ltd | Method of integrating an element |
| JP2008258536A (en) * | 2007-04-09 | 2008-10-23 | Denso Corp | Semiconductor fuse device and its manufacturing method |
| US7615395B2 (en) | 2003-12-24 | 2009-11-10 | Cavendish Kinetics Limited | Method for containing a device and a corresponding device |
| US7989262B2 (en) | 2008-02-22 | 2011-08-02 | Cavendish Kinetics, Ltd. | Method of sealing a cavity |
| US7993950B2 (en) | 2008-04-30 | 2011-08-09 | Cavendish Kinetics, Ltd. | System and method of encapsulation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134437A (en) * | 1983-12-23 | 1985-07-17 | Nippon Telegr & Teleph Corp <Ntt> | Fusing device and manufacture thereof |
-
1987
- 1987-06-09 JP JP14461287A patent/JPS63307758A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60134437A (en) * | 1983-12-23 | 1985-07-17 | Nippon Telegr & Teleph Corp <Ntt> | Fusing device and manufacture thereof |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6303980B1 (en) | 1996-01-08 | 2001-10-16 | Infineon Technologies Ag | Fusible link in an integrated semiconductor circuit and a memory cell of a semiconductor component |
| US6080649A (en) * | 1996-01-08 | 2000-06-27 | Siemens Aktiengesellschaft | Fusible link in an integrated semiconductor circuit and process for producing the fusible link |
| EP0783182A3 (en) * | 1996-01-08 | 1998-01-21 | Siemens Aktiengesellschaft | Fuse in a semiconductor integrated circuit |
| US6524941B2 (en) | 1998-06-08 | 2003-02-25 | International Business Machines Corporation | Sub-minimum wiring structure |
| US6566238B2 (en) | 1999-02-26 | 2003-05-20 | Infineon Technologies Ag | Metal wire fuse structure with cavity |
| US6268638B1 (en) | 1999-02-26 | 2001-07-31 | International Business Machines Corporation | Metal wire fuse structure with cavity |
| EP1032040A3 (en) * | 1999-02-26 | 2001-11-21 | International Business Machines Corporation | Metal wire fuse structure with cavity |
| EP1032040A2 (en) * | 1999-02-26 | 2000-08-30 | International Business Machines Corporation | Metal wire fuse structure with cavity |
| KR100385799B1 (en) * | 1999-02-26 | 2003-06-02 | 인터내셔널 비지네스 머신즈 코포레이션 | Metal wire fuse structure with cavity |
| WO2001018863A1 (en) * | 1999-09-09 | 2001-03-15 | Infineon Technologies North America Corp. | Method for manufacturing fusible links in a semiconductor device |
| US7615395B2 (en) | 2003-12-24 | 2009-11-10 | Cavendish Kinetics Limited | Method for containing a device and a corresponding device |
| USRE44246E1 (en) | 2003-12-24 | 2013-05-28 | Cavendish Kinetics Limited | Method for containing a device and a corresponding device |
| WO2007017672A1 (en) * | 2005-08-05 | 2007-02-15 | Cavendish Kinetics Ltd | Method of integrating an element |
| JP2008258536A (en) * | 2007-04-09 | 2008-10-23 | Denso Corp | Semiconductor fuse device and its manufacturing method |
| US7989262B2 (en) | 2008-02-22 | 2011-08-02 | Cavendish Kinetics, Ltd. | Method of sealing a cavity |
| US8395249B2 (en) | 2008-02-22 | 2013-03-12 | Cavendish Kinetics, Ltd. | Sealed cavity |
| US7993950B2 (en) | 2008-04-30 | 2011-08-09 | Cavendish Kinetics, Ltd. | System and method of encapsulation |
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