JPS63307547A - Cpu monitor circuit - Google Patents

Abstract

PURPOSE:To effectively cope even with an unexpected jump or runaway of software by resetting a watchdog timer only when the coincidence is obtained between a key word and a reset word and resetting immediately a CPU when no coincidence is obtained between both words. CONSTITUTION:A key word written through a scheduler 1 is held by a key word register 7; while the reset words written through tasks 21-24 are held by a reset word register 6. Then the outputs of a pair of registers 1 and 6 are compared with each other. A watchdog timer 9 is reset by the output of coincidence obtained from said comparison and counts the output pulses of an oscillator 10. Then a CPU 11 is reset by an OR between the output of discrepancy of said comparison and the time-out output of the timer 9. Thus it is possible to effectively cope even with an unexpected jump or runaway of software.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a CPU monitoring circuit, and particularly to monitoring of CPU inoperation and runaway.

(Prior Art) Conventionally, this type of CPU monitoring circuit has the following structure as shown in FIG.
During normal operation, the control flow 2 is executed by reset commands distributed among the software tasks 221 to 224.
31 to 234, the reset word is output to the CPU monitoring circuit 24 via the port, and the internal watchdog timer 2S is reset within a certain period of time. However, the CPU 2 or peripheral circuits (not shown)
If there is an abnormality in the watchdog timer 2S, it becomes impossible to reset the watchdog timer 2S using the reset words 231-234. At this time, when the counter is incremented by the input from the oscillator 26 and a timeout output is input to the CPU 27, the CPU 2 is reset.

(Problems to be Solved by the Invention) The above-mentioned conventional CPUIR'! In the circuit, the watchdog timer is also reset by A-shifted reset commands placed in various parts of the software, so it is effective in detecting a malfunction due to a failure in the CPU or peripheral circuits, but it is also effective in detecting an unexpected jump in the software, The drawback is that it is not necessarily effective against runaway behavior.

An object of the present invention is to hold a keyword written from a schedule in a keyword register, hold a reset word written from each task in a reset word register, and compare the outputs of these pair of registers. By using a watchdog counter that is reset by the coincidence output of the oscillator and counts the output pulses of the oscillator, the discordance output of the comparison is logically summed with the timeout output of the counter, and the CPU is reset by that output. A CPU monitoring circuit designed to eliminate defects and operate effectively against unexpected software jumps and runaways.
The goal is to provide the following.

(Means for Solving the Node Point) The CPU monitoring circuit according to the present invention includes a keyword register, a reset word register, a comparator, a 9-way dog timer, and an OR gate. be.

The keyword register is written by the scheduler.
The reset word register is used to hold the reset word written by each task.

The comparator is for comparing the contents of the keyword register and the contents of the reset word register.

The watchdog timer is reset by the coincidence output of the comparator and is used to count and time the output pulses of the TB and the TB.

The OR gate is used to calculate the logical sum of the mismatch output of the comparator and the output of the watchdog timer.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CPU monitoring circuit according to the present invention.

11, 1 is a scheduler, 21 to 24 are task areas, 31 to 34 are reset word signal paths, 13 is a software system, and S is a CP
6 is a reset word register, 7 is a keyword register, 8 is a comparison 4.9 is a watchdog timer, 10 is an oscillator, 11 is a CPU, and 12 is an OR gate.

The software 7 system 13 operates under the scheduler 1, and each task 21 to 24 operates in sequence. When the scheduler 1 starts each of the tasks 21 to 24, it writes a keyword uniquely assigned to the task to be started into the keyword register according to the control flow f'L4. The contents of keyword register 7 are then stored in scheduler 1.
is held until another word is written. As a precaution, the keyword representing the above content is held in the keyword register 7 until control is transferred to another task.

, 1-d A command is placed inside the Q task. According to the above command, a reset word corresponding to the keyword of the scheduler 1 is written to the reset word register 6 within a certain period of time according to the control flows 31 to 34. The written running reset word is compared with the contents of keyword register 7 by comparator 8. If both match, the match output is signal 1 line 14
is output from the signal line 15 to the reset terminal of the watchdog timer 9, and if there is a mismatch, the mismatch output is sent from the signal line 15 to the reset terminal of the watchdog timer 9.
Output as a PU reset signal.

The watchdog timer 9 counts the clock pulses from the oscillator 10, and if there is a matching output from the comparator 8, it times out and resets the CPU to output all outputs.

The CPU reset signal output from the comparator 8 and the watchdog timer 9 is combined by an OR gate 12 and then input to the CPU 11.

If the CPU 11 is operating normally, each task will correctly write a reset word to the reset word register 6 before the watchdog timer 9 times out, and the watchdog timer 9 will be reset accordingly.

Therefore, the CPU 11 is not reset during normal operation. On the other hand, if an abnormality occurs in the CPU 1 or the circuit on the same side and the reset word cannot be written, the watched timer 9 times out and the CPU 1 is reset.

Furthermore, if the CPU 11 goes out of control and another task is executed illegally, a reset word that does not match the keyword is written, a mismatch signal is outputted to the signal line 15 by the comparator 8, and the CPU 11 is immediately reset. Ru.

(Effects of the Invention) As explained above, the present invention completely compares the keyword written by the scheduler with the reset word written by the reset command inside each task, and only when the above two match, the watchdog timer By resetting the CPU immediately if the above two do not match, the CPU will not be reset until the watchdog timer times out, even if the CPU is running out of control, and data will be destroyed during this time. This has the effect of reducing the possibility of transmitting an erroneous I10 output.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the CPU1fi visual circuit according to the present invention. The second page 4 is a block diagram showing an example of a CPU monitoring circuit according to the prior art. 1.21...Scheduler 21-24.221-224...Task S, 24...
・CPU Irrigation circuit 6...Reset word register...Keyword register 811...Comparator 9.25...and watchdog timer 10.26@-Oscillator 11.27--@CPU 12... OR gate 13...Software systems 31-34, 4, 231-234--Processing flow

Claims (1)

[Claims] A keyword register for holding keywords written from the scheduler, a reset word register for holding reset words written from each task, and a register for comparing the contents of the keyword register and the reset word register. a comparator, a watchdog timer that is reset by the coincidence output of the comparator and for counting and timing the output pulses of the oscillator, and calculating the logical sum of the mismatch output of the comparator and the output of the watchdog timer. A CPU monitoring circuit characterized in that it is configured to include an OR gate for.